An injection-locked ring oscillator-based phase-locked-loop targeting clock recovery for space application at 3.2 GHz is presented here. Most clock recovery circuits need a very low phase noise and jitter performance and are thus based on LC-type osc...
Phase-Locked Loops (PLLs) are fundamental building blocks in modern electronic systems, enabling precise frequency synthesis, signal synchronization, and clock generation. This paper provides a comprehensive system-level analysis of PLLs, covering th...
The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are...
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD)...
The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1....
This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and...
In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design...
This paper proposes the enhancement of a synchronous reference frame phase-locked loop in terms of its dynamic response and disturbance rejection capability. The improvements were undertaken in order to upgrade the converter grid support capability r...
The use of renewable energy sources is the need of the hour, but the highly intermittent nature of the wind and solar energies demands an efficient controller be connected with the system. This paper proposes an adept control algorithm for an isolate...
This paper demonstrates the design and implementation of an all-digital phase-locked loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique to show the feasibility and effectiveness of the ADPLL in the early desi...
In this paper, we report on our simulation and design of a photonic integrated circuits (PIC)-based heterodyne optical phase-locked loop (OPLL). Our simulation reveals that the OPLL operation can be in one of three states, i.e., absolutely stable, me...
Synchronization of large acquisition bandwidth brings great challenges to the traditional second-order phase-locked loop (PLL). To address the contradiction between acquisition bandwidth and noise suppression capability of the traditional PLL, a new...
The precise control of output power by grid-connected converters relies on the correct identification and tracking of a grid voltage’s phase at the converter terminal. During severe grid faults, large disturbances cause the converter’s op...
The optical signal propagation used in satellite uplinks and downlinks is influenced by absorption, scattering, and changes in the atmospheric refractive index or turbulence, causing optical signal attenuation. A free space optics (FSO) communication...
This paper presents a novel frequency-locked-loop (FLL) scheme that provides estimates of the in-phase and square-phase fundamental components of a distorted single-phase reference signal and an estimate of its fundamental angular frequency. The main...
In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by supple...
This paper proposes an effective algorithm; this algorithm is updating the phase-locked loop (PLL) gains according to the value of the short circuit ratio that will decrease the weak grid effect in the PLL controllers to reduce problems related to re...
This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential s...
This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed...
Determining the loop noise bandwidth and the coherent integration time is essential and important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite system (GNSS) receivers. In general, designers set such par...
Synchronous-reference-frame phase-locked loop (SRF-PLL) is widely used in grid synchronization applications. However, under unbalanced, distorted and DC offset mixed grid conditions, its performance tends to worsen. In order to improve the filtering...
This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a
MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibrati...
An existing phase-locked-loop (PLL) based contact-resonance measurement system is studied and optimized. Improvements to the electronics’ circuit to reduce both nonlinear behavior and noise are realized and experimentally tested. The improvements ena...
This paper proposes an enhanced Type 3 phase-locked loop (ET3-PLL) to improve the frequency estimation performance of the conventional Type 3 synchronous reference frame PLL (SRF-PLL) under harmonic distortion. Frequency response analysis of the conv...
In recent years, the doubly fed induction generator (DFIG) operates in a weak grid, rather than a strong grid due to the high proportion of wind energy into the power grid. The impedance interaction between the DFIG system and series and parallel com...
Synchronization is a crucial problem in the grid-connected inverter’s control and operation. A phase-locked loop (PLL) is a typical grid synchronization strategy, which ought to have a high resistance to power system uncertainties since its sen...
Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device p...
With the development of space exploration technologies, space-grade CMOS image sensors require high-performance on-chip clock circuits with low jitter, low power consumption, small area, and excellent radiation robustness. This paper presents a radia...
An adaptive digital phase-locked loop (DPLL) continually adjusts the noise bandwidth of the loop filter in global navigation satellite system (GNSS) receivers to track signals by measuring the signal-to-noise ratio and/or dynamic stress. Such DPLLs h...
In distributed energy grid-connected systems, fast and accurate grid synchronization technology is crucial for system stability. This article proposes an improved phase-locked loop (FECSOGI-PLL) based on frequency error compensation. By introducing a...
The goal of this paper is to explore the effect of various parameters on the information geometric structure of the phase-locked loop (PLL) statistics, both transient and stationary. Comprehensive treatment on the behavior of PLL statistics will be g...
This paper presents an all-digital fractional-N phase-locked loop (ADPLL) operating in the 2.86–3.2 GHz range, optimized for IoT and high-frequency RF transceiver applications demanding stringent phase noise performance, fast settling time, and...
In traditional sensorless control of the interior permanent magnet synchronous motors (IPMSMs) for medium and high speed domains, a control strategy based on a sliding-mode observer (SMO) and phase-locked loop (PLL) is widely applied. A new strategy...
This work proposes a structural enhancement and a new technique to design the loop filter (LF) of a third-order phase-locked loop (PLL) to enhance the PLL dynamic performance under abnormal grid conditions. The proposed PLL combines a moving average...
The moving average filter-based phase-locked loop (MAF-PLL) can obtain grid synchronization signals accurately under adverse grid conditions with a large amount of harmonics due to the high filtering capability of the MAF. However, MAF-PLL cannot ach...
Traditional low-order flux sliding mode observer (FSMO) and quadrature phase-locked loop (QPLL) structures generally encounter issues such as estimated signal chattering and inadequate dynamic performance. To overcome these challenges, this paper pro...
To address the challenges posed by harmonic distortion and DC offset in the power grid, this paper proposes a novel Phase-Locked Loop (PLL) architecture tailored for single-phase grid-connected systems. The design integrates an Enhanced Adaptive Seco...
The dynamic monitoring, control, and protection of modern power systems in real time require time-stamped electrical measurements to accurately estimate the bus voltage phasors using the state estimation function under normal and abnormal conditions....
A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse sw...
The quartz crystal microbalance (QCM) has been widely used in laboratory settings as an analytical tool for recognizing and discriminating biological and chemical molecules of interest. As a result, recent studies have shown there to be considerable...
Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the...
Traditional zero-compensation techniques employed to improve sub-sampling phase-locked loop (SSPLL) stability often exacerbate spur degradation or incur excessive area overhead, rendering them unsuitable for high-resolution image sensor applications....
In a distributed generation system, the all-pass-filter phase-locked loop (APF-PLL) is a commonly used method for grid synchronization. However, the coupling effect between APF-PLL and current control loop increases the risk of oscillation instabilit...
The stability and dynamic performance of the grid-connected converter is greatly affected by the coupling between the phase-locked loop (PLL) and the current loop control under weak grid conditions. The traditional control strategies use PLL to obtai...
In renewable energy generation applications, phase locked loop (PLL) is one of the most popular grid synchronization technique. The main objective of PLL is to rapidly and precisely extract phase and frequency especially when the grid voltage is unde...
In a phase-locked loop (PLL) synchronized inverter grid-connected system, its equivalent damping coefficient is nonlinearly coupled with the operation power angle. Therefore, under a large disturbance, the indefinite damping increases the risk of tra...
When three-phase voltages are polluted with unbalance, DC offsets, or higher harmonics, it is a challenge to quickly detect their parameters such as phases, frequency, and amplitudes. This paper proposes a phase-locked loop (PLL) for the three-phase...
A high-accuracy demodulation algorithm is required to estimate angular position and angular velocity from resolver signals. In order to improve the estimation accuracy of conventional phase-locked loop (PLL) based demodulation method, a Chebyshev fil...
This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-doma...
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