A Simplified G_m − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

Abstract

This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a $G_m-C$ filter is proposed. The reference spur is improved by 7 dB when compared with one without any $G_m-C$ filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The $G_m-C$ filter block consumes 200 $\mathsf{\mu }$A current. The wideband voltage-controlled oscillator (VCO) oscillates from $1.6$ GHz to $3.2$ GHz having a tuning range (TR) of $40\%$, achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈$-116$ dBc/Hz at a 1 MHz offset, respectively.

1. Introduction

Extreme accuracy is needed for the growing demand for location-based services (LBSs), particularly for space applications or rescue and search operations [1]. To attain the necessary location accuracy, LBSs need either a single global navigation satellite system (GNSS) frequency or several GNSS frequencies [2]. Numerous global navigational systems exist, including GLONASS (Russia), Galileo (EU), and BeiDou (China). A system specifically designed for the Indian subcontinent is the Indian Regional Navigation Satellite System (IRNSS). This system uses navigation signal frequencies between $1.17$ GHz to $2.5$ GHz. The received signal is weak (≈−130 dB), hence a high-sensitivity receiver is required for proper reception because IRNSS receivers are designed for critical applications like real-time monitoring and precise location positioning. Any receiver’s sensitivity depends on the local oscillator’s (LO) phase noise (PN), spectrum purity, and low spurs [3,4,5,6,7,8,9,10,11,12,13], which makes the design of the phase-locked loop (PLL) complicated [1,14]. In applications of transceivers, it is important to maintain a pure, single-tone spectrum, without unwanted tones to avert a corruption of required data.

This work presents a $G_m-C$ filtering technique for the reference spur reduction of a wideband PLL. Firstly, a brief overview of PLLs implemented for IRNSS applications is discussed. Then, the reasons and parameters affecting the reference spur generation is presented. After that, the proposed $G_m-C$ filter technique for reference spur reduction is analyzed. Finally, PLL measurement results and a performance comparison with other latest works are presented and a conclusion of the work is drawn.

1.1. Overview of IRNSS PLL

The L5 and S frequency bands are where the IRNSS receiver typically operates. There are single voltage-controlled oscillator (VCO) [15], multiple VCO PLLs’ [16], and rotatory traveling wave oscillator [17] architectures described in the literature. The most recent research covers both bands with a single broadband voltage-controlled oscillator (VCO) [18]. To achieve this, the PLL must operate at a reasonable power consumption with an acceptable quality factor (Q) and have stability throughout the whole range. In other works, these bands are covered by various PLLs [2]. The feedback divider, which must work over several ranges, is one of the factors contributing to the use of numerous PLLs. A PLL using an extended range divider is presented in [19,20].

Thus, high-performance PLLs mainly require better phase noise and low reference spurs simultaneously. To accomplish this in L5 and S bands, this work provides a wideband integer-N PLL using a single VCO. The wideband PLL covers multiple bands using a single VCO but comes at the cost of extra power to maintain an acceptable inductor’s Q-factor. To maintain PLL stability, the charge pump current ($I_{CP}$) needs to have programmability. The wideband VCO also has a variable VCO gain ($K_{VCO}$), which, along with $I_{CP}$, affects the reference spur of the PLL.

1.2. Reference Spur in PLL

Ideally in the frequency domain, a PLL should generate a single tone. In reality, this signal is not a single tone because of the unwanted noise added at various points of the PLL, making the spectrum impure. A conventional type-II PLL highlighting the non-idealities causing the reference spur is shown in Figure 1. The phase frequency detector (PFD) senses the error between the reference signal ($F_{REF}$) and the feedback signal ($F_{DIV}$). A proportional source/sink current is provided by the charge pump (CP), which is converted as a control voltage ($V_{tune}$) and passed on to the VCO that generates the output frequency. The feedback divider divides the high-frequency output into a low-frequency signal that is given as input to the PFD.

Non-idealities of the PFD and CP circuits like PFD output mismatch, $I_{CP}$ mismatch, PFD-to-CP propagation delay mismatch, clock feed-through, etc., generate a periodic variation on $V_{tune}$. In the frequency domain, this periodic variation is visualized as signals at $F_{REF}$ and at its offsets from the VCO output.

Some detailed analyses of spurs due to the above non-idealities are discussed in [21]. The spur level depends on $K_{VCO}$ and on the order of the low-pass filter (LPF). The magnitude of the spur reference is shown in (1) [22] (units are in dBc):

$$A_{spur}=20log\left(\frac{N·{\varphi }_e·{\omega }_{LBW}}{{\omega }_{REF}·\sqrt{2}}\right)-20log\left(\frac{{\omega }_{REF}}{{\omega }_P}\right)$$

(1)

where ${\varphi }_e$ is the phase offset due to the leakage current, ${\omega }_P$ is the out-of-band pole frequency, ${\omega }_{REF}$ is the reference frequency, and ${\omega }_{LBW}$ is the loop bandwidth frequency of the PLL as given in (2).

$${\omega }_{LBW}\approx \left(\frac{I_{CP}·R_1·K_{VCO}}{N}\right)$$

(2)

1.3. Spur Reduction Techniques

Several methods of spur reduction for PLLs have been published. In [3,4,5,6,7,8,9,10,11,12,13], the authors utilized the higher-order loop filter to achieve an acceptable spur level (<$-65$ dBc). However, a higher-order loop filter affects the PLL phase margin which might make the system unstable. Figure 2 shows the open-loop gain of a type-II PLL built using second-order and third-order loop filters.

From (1), the reference spur expression for the second- and third-order loop filter is given by (3) and (4), respectively.

$$A_{spur,2^{nd}order}=20log\left(\frac{N.{\varphi }_e.{\omega }_{LBW}}{{\omega }_{REF}.\sqrt{2}}\right)-\Delta B$$

(3)

$$A_{spur,3^{rd}order}=20log\left(\frac{N.{\varphi }_e.{\omega }_{LBW}}{{\omega }_{REF}.\sqrt{2}}\right)-\Delta B-\Delta A$$

(4)

Thus, the spur level is improved by $\Delta A$ when the loop filter order is increased from two to three. The amount of spur reduction mainly depends on out-of-band poles, i.e., ${\omega }_{P1}$ and ${\omega }_{P2}$. From (1), one can observe that the magnitude of the spur is directly proportional to $K_{VCO}$ and inversely proportional to ${\omega }_{REF}$. A lower $K_{VCO}$ has the effect of reducing the total VCO frequency bandwidth. This can be overcome by an additional switched capacitor array (SCA) [23], but it adds to the noise and circuit complexity.

In [24], a smaller VCO gain and loop bandwidth achieved low spur levels at the cost of a reduced frequency range and longer settling time. A charge distribution method used on the VCO control voltage was presented in [25] to reduce the spur level. This method shifted the spur frequency from the reference to a higher frequency, thus suppressing the spur effectively. This was achieved by either using multiple PFD-CP paths with different delays or using cascaded PLLs [26]. Additionally, sampling between the reference signal and VCO output signal to reduce the spur was proposed in [27]. Both techniques add extra noise to the PLL and thus are not preferred. A frequency boost circuit to minimize the spur level was also shown in [21]. Thus, there are many trade-offs when choosing a method to reduce reference spur.

1.4. $G_m-C$ Filter Technique for Reference Spur Reduction

The LC-based notch filter at the loop filter input as shown in Figure 3 is proposed to reduce the reference spur. The notch filter, which attenuates a particular frequency component, does not affect the PLL stability. An active inductor is designed to achieve this which also reduces the chip area.

This approach was presented in [28] (see Figure 4) where the active inductor was implemented using an operational amplifier. Though it provides programmability, it adds extra complexity to the system. Another implementation of an active inductor for a $G_m-C$ notch filter was presented in [29]. There, the target was to improve the close-in blocker tolerance of a receiver. A fully differential operational amplifier was designed, adding more complexity to the circuit.

2. Proposed ${\mathit{G}}_{\mathit{m}}\mathbf{-}\mathit{C}$ Filter Technique

The goal of this PLL is to achieve an acceptable reference spur with less complexity. The block level implementation of a simple active inductor circuit based on a capacitor/gyrator combination is shown in Figure 5a and the circuit level realization is shown in Figure 5b. The passive capacitor and two back-to-back transconductance amplifiers are connected to mimic the operation of an inductor. Here, $Z_L$ is the load impedance and $g_{ma}$ and $g_{mb}$ represent the effective transconductance gain of two amplifiers, respectively. To acquire a value for the effective inductance ($L_{eq}$), the two amplifiers are treated as ideal and a voltage $V_{in}$ is enforced at the input of the active inductor. The current at the first amplifier output, $i_a$, is given by (5).

$$i_a=g_{ma}.V_a=g_{ma}.V_{in}$$

(5)

$V_o$ is the output voltage at the load, which can be expressed in (6) as

$$V_o=i_a.Z_L=g_{ma}.Z_L.V_{in}$$

(6)

$i_{in}$ is the input referred feedback current given by (7):

$$i_{in}=-i_b=-(V_o.(-g_{mb}))=g_{ma}.g_{mb}.Z_L.V_{in}$$

(7)

$Z_{in}$ is the effective input impedance given by (8):

$$Z_{in}=\frac{v_{in}}{i_{in}}=\frac{1}{g_{ma}.g_{mb}.Z_L}$$

(8)

The gyrator circuit therefore both inverts the impedance $Z_L$ and also scales it by a factor of $g_{ma}.g_{mb}$. When the load impedance $Z_L$ is formed by some ideal capacitance $C_L$ (see Figure 5), such that

$$Z_L=\frac{1}{s{C}_L},$$

(9)

the input impedance is equal to

$$Z_{in}=\frac{s{C}_L}{g_{ma}.g_{mb}}$$

(10)

Therefore, the gyrator, in this case, behaves as an inductor with an equivalent inductance of $L_{eq}$. The equivalent inductance is given by (11).

$$L_{eq}=\frac{C_L}{g_{ma}.g_{mb}}$$

(11)

The tank circuit resonant frequency is adjusted by varying the transconductance $g_{ma}$ and $g_{mb}$ (see Figure 5a). The main advantage of this implementation is that it requires a small area and straightforward implementation along with providing a very large tuning range. The Q-factor of the $G_m-C$ filter is shown in Figure 6 and the impact on PLL stability is shown in Figure 7. The Q-factor is obtained by the s-parameter analysis of the $G_m-C$ filter, while the stability result is captured from the stability analysis performed on the PLL.

From Figure 7, it is clear that in both cases, viz., without $G_m-C$ and with $G_m-C$, the loop bandwidth is ≈187 kHz, and the phase margin is ≈55°. Thus, the proposed technique does not impact the PLL stability. The reference spur of the PLL output spectrum in both cases, viz., without $G_m-C$ and with $G_m-C$, is also shown in Figure 8. This is achieved by plotting the fast Fourier transform (FFT) of the PLL output after settling, in both the cases.

The reference spur without the $G_m-C$ is ≈57 dBc. After incorporating $G_m-C$, the reference spur is ≈67 dBc, improving the reference spur level by ≈10 dB. This exercise was performed at a $2.4$ GHz carrier with a 25 MHz reference. The same can be programmed for other reference values. The resonance frequency of the $G_m-C$ filter may vary across process, voltage, and temperature (PVT). To maintain the resonance frequency across PVT, the resistor $R_S$ (see Figure 5) can be designed as a programmable resistor. Also, the $G_m-C$ filter linearity is discussed in [28]. The estimate up to which the $G_m-C$ filter should be linear is analyzed in [28]. This work followed the same method, and the $G_m-C$ filter was designed such that the targeted frequency (23 MHz to 27 MHz) is in the linear range across PVT.

2.1. Phase-Locked Loop Design

The integer-N PLL using a wideband VCO is shown in Figure 3. The PLL crystal operates between 23 and 27 MHz, acting as the baseband and PLL clocks at the same time. A D-flip-flop-based PFD and programmable CP are designed to maintain stable loop dynamics. A second-order passive on-chip loop filter is selected to meet acceptable loop bandwidth and phase margin. A differential LC-VCO is used, followed by a high-speed current-mode logic (CML) divide by 2. The output of the LC-VCO and the divide by 2 are routed to the I/O pads through CML MUX. The PLL loop parameters and target PN at 100 kHz and 1 MHz offsets are tabulated in

Table 1. PLL Loop parameters.

Parameter	Value
Crystal frequency (MHz)	23 to 27
VCO range (GHz)	1.6 to 3.2
VCO gain (MHz/V)	80 to 120
$I_{CP}$ (mA)	0.1 to 1
Division ratio	64 to 127
Loop bandwidth (kHz)	160 to 240
Phase margin (°)	54 to 59
PN @ 100 kHz (dBc/Hz)	−90 to −95
PN @ 1 MHz (dBc/Hz)	−115 to −120

.

2.1.1. PFD and Charge Pump

A NAND gate-based PFD is implemented in this PLL [30]. It generates four outputs (UP, UPB, DN, and DNB) which are connected to the CP. A delay of ≈300 ps is added in the reset path to overcome the dead-zone issue. A programmable CP is designed to maintain an acceptable loop bandwidth and phase margin over the entire frequency range [30]. The $I_{CP}$ is programmable from 100 $\mathsf{\mu }$A to 1 mA (see Figure 9).

2.1.2. Second-Order Loop Filter

A Second-order passive loop filter for the charge-pump PLL is shown in Figure 10. There are two capacitors and one resistor. $C_1$ produces the first pole at the origin for this PLL. This is the largest capacitor, hence, it is a key integration bottleneck of the PLL and is used to generate a zero for loop stability. $C_2$ is used to smooth the control voltage ripples and to generate the second pole. The loop filter transimpedance, Z(s), is given by (12):

$$Z\left(s\right)=\frac{V_{tune}\left(s\right)}{I_{cp}\left(s\right)}=\frac{1+s{T}_z}{s(C_1+C_2)(1+s{T}_p)}$$

(12)

where $T_z$= $R_1·C_1$ and $T_p$ = ($R_1·C_1·C_2)/(C_1+C_2)$. After considering the stability criterion and settling time, the loop filter parameters are decided. The loop filter has a large capacitor ($C_1$) to maintain better stability. This capacitor occupies the major area of the chip. The large spur attenuation requirement along with a large phase margin (≈60°) yields a large total integrated capacitance value that makes its integration challenging.

2.1.3. VCO and CML Divider

The VCO operates from $1.6$ GHz to $3.2$ GHz and generates the S-band from the VCO output in a differential way. The divide by 2 output generates the $L5$-band, which is quadratic in nature. Figure 11 shows the detailed schematic of the wideband LC-VCO. A complementary cross-coupled LC-VCO core is shown in Figure 11a. A dual-bias varactor shown in Figure 11b is used for fine tuning. The switched-capacitor array (SCA) structure implemented in [15] is used for discrete tuning as shown in Figure 11c.

2.1.4. Feedback Divider

Figure 12 shows an input ($f_{in}$) and output ($f_{out}$) of a typical multi-modulus divider (MMD). The programming pin ($P_i$), where i = 0 to N, and modulus control ($MI$) govern the division ratio. A suitable modulus out ($MO$) is generated based on the selection of $MI$ and $P_i$, acting as $MI$ to the subsequent stage. A divide by three is produced when $MI$ and $P_i$ are high. The $2/3$ cell functions in a divide-by-two mode when $MI$ is logic low, regardless of what $P_i$ is. An independent $2/3$ MMD cell’s functioning is summed up in

Table 2. Working of standalone $2/3$ MMD cell.

$\mathit{Input}\left(\mathit{IN}\right)$	${\mathit{P}}_{\mathit{i}}$	$\mathit{MI}$	$\mathit{Output}\left(\mathit{OUT}\right)$
$f_{in}$	X	0	$f_{in}/2$
$f_{in}$	0	1	$f_{in}/2$
$f_{in}$	1	1	$f_{in}/3$

. The division ratio can be increased by inserting more of these $2/3$ cells. In such cases, the $MI$ of the final $2/3$ stage is connected to the supply ($V_{DD}$).

If the required division ratio of a PLL band falls outside the MMD range, this structure fails. The MMD division range is given by (13):

$$N=2^0{P}_0+2^1{P}_1+2^2{P}_2+\cdots +2^n{P}_n$$

(13)

where n is the total number of $2/3$ divider cells (n = 0, 1, 2, so on) and $P_i$, where i = 0 to n, is the $2/3$ cell digital control. Hence, the conventional MMD division range is limited from $2^n$ to $2^{n+1}-1$. In this design, an MMD operating from 64 to 127 is incorporated in the feedback path.

3. Measurement Results

The wideband PLL was fabricated in UMC 65 nm CMOS. The PLL operated from a supply voltage of $2.5$ V for all blocks except the feedback divider which operated at $1.2$ V. The VCO and the CML divider consumed 4 mA each, making the two most power-hungry blocks in the PLL. The complete PLL core area was $0.8$ ${\mathrm{mm}}^2$.

The area of the VCO was $0.25$ ${\mathrm{mm}}^2$ (see Figure 13). A larger chip area was expected due to the on-chip inductor. The $G_m-C$ notch filter had minimal area overhead ($0.2$% of the loop filter). The test board with the die packaged in a 68-pin quad flat no-lead (QFN) package is shown in Figure 13. The measurement setup for the PLL is shown in Figure 14 [31].

The spectrum and phase noise were measured using an Agilent EXA N9010A signal analyzer. A function generator was used to provide the reference frequency to the PLL. The 25 MHz square-wave signal with a $50\%$ duty cycle was provided as the reference signal at the input of the PLL through the function generator. The proper control bits to generate $2.4$ GHz output were chosen. The PLL output was connected to the spectrum analyzer using a radio frequency (RF) probe, and the phase noise was measured. The extracted simulation phase noise of the PLL with and without $G_m-C$ and the measured phase noise of the PLL at a frequency of $2.4$ GHz are shown in Figure 15.

The PLL spectrum at a $2.4$ GHz LO frequency and reference spur at a 25 MHz offset is shown in Figure 16. A reference spur of ≈$-64$ dBc was measured, which matched with the simulation results. Thus, the reference spur level was ≈7 dB better with the proposed $G_m-C$ filter technique. The architecture comparison with other state-of-the-art active inductor based $G_m-C$ filter implementations is shown in

Table 3. Architecture comparison between various $G_m-C$ filter implementation techniques.

	This Work	[28]	[29]
Supply (V)	2.5	1.3	1.8
$G_m-C$ Architecture (V)	Single ended	Differential	Differential
Operational amplifier in $L_{eq}$ implementation	No	Yes (Single ended)	Yes (Fully differential)
Circuit Complexity	Low	Moderate	High
Current (mA)	0.2	0.4	1.5
Compatible with lower supply	Yes	No	No
Programmability	No †	Yes	Yes

† Programmability can be added but was not added in this work.

. The current consumption and circuit complexity of the proposed technique is lower compared to other works. Even though the supply of this work was $2.5$ V, the proposed architecture is suitable for designs using a lower supply.

The performance comparison of the wideband PLL with state-of-the-art PLLs is summarized in

Table 4. Performance comparison of wideband PLLs.

	This Work	[18]	[26]	[32]
Technology (nm)	65	65	65	14
Supply (V)	2.5/1.2	1.2	1.3	1/0.8
Frequency (GHz)	1.6–3.2	1.17–2.5	0.8	5–7
Reference (MHz)	23–27	23–27	50	76.8
PN (dBc/Hz) @ 1 MHz	−116/−122	−116	−110	−122
Area (${\mathrm{mm}}^2$)	0.8	0.25	0.935	0.31
Power (mW)	30	15.7	4.8	14.2
Ref. spur (dBc)	−64 (−57 ‡)	NA	−68.57	−69.6
FoM †	171.3	165.4	161.25	186.6

† FoM $=10\times \log \left[{\left(f_{vco}/\Delta f\right)}^2.\left(1mW/Pow.\right)\right]-PN$. ‡ Extracted simulation without $G_m-C$.

. This work achieved the best figure of merit ($FoM$) of $171.3$ dBc/Hz for the S-band compared to other works related to GPS applications. The $FoM$ of the proposed wideband PLL was better than [18]. The reference spur in [26] was better but it came at the cost of an inferior PN, which is reflected in its $FoM$. The work in [32] was designed at a smaller power supply and lower technology node and achieved a better reference spur. The power consumption of this work is a bottleneck and can be reduced by lowering the supply and replacing the high-speed divide by two implemented using CML logic with TSPC logic.

4. Conclusions

An integer-N PLL for IRNSS applications was presented. The $G_m-C$ filter design for reference spur reduction was analyzed. The simulation results showed that the proposed technique had no impact on the stability of the PLL. The Q factor of the $G_m-C$ filter was also discussed. This design achieved a spur reduction with minimal area and power overhead. The design details of the PLL were discussed followed by measurement results to validate the design. The wideband PLL was incorporated with the proposed $G_m-C$ filter-based spur reduction technique, which reduced the reference spur by ≈7 dB. This design thus offers a spur reduction technique with a simple approach rather than a complex amplifier approach. The only drawback of the proposed structure is the lack of programmability present in other works. In the future, programmability can be added in the $G_m-C$ filter. A simple way is by replacing the $C_L$ with a varactor.