Electronics — Open Access Journal

When applied to road vehicle electrification, inductive power transfer (IPT) technology has the potential to boost the transition from combustion engines to electric motors powered by a battery pack. This work focuses on the validation of a PSpice circuit model developed as a replica of a 2-kW IPT prototype with series-series compensation operating at 18.65 kHz. The laboratory prototype has the three stages commonly found in an IPT system: an inverter, controlled by the phase-shift technique, a coil coupling and a load. Simulations were run with the circuit model for three different distances between the two coils of the inductive coupling, all of which are of interest for practical chargers: 125, 150 and 175 mm. The validation approach was based on tuning the magnetic coupling factor for each distance and a set of ten load resistances, until the best match between the simulated and the experimental peak currents supplied by the inverter was found in each case. The coupling factors obtained from the simulation work are in good agreement with their experimental counterparts for the three distances, provided the duty cycle of the inverter output voltage is not too small. The circuit model developed is, therefore, able to reproduce the behavior of the laboratory prototype with sufficient accuracy over a wide range of distances between coils and loading conditions. Full article

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case. Full article

This paper is concerned with a novel event-triggered sliding mode variable structure control (ESMC) scheme to achieve robust stabilization of memristive systems (MSs). First, a memory-based sliding surface, including the past and the current information of the system states, is introduced. Two switching gain matrices of such kinds of switching surfaces, which satisfy the guaranteed cost performance of the sliding reduced order dynamics, are achieved by employing linear matrix inequality techniques. Second, a sliding mode controller using an event-triggered mechanism is constructed to ensure that the trajectories of the uncertain MS slide towards the proposed memory-based switching hyperplane, and thus, the stabilization of entire MSs is reached. Finally, the effectiveness of the proposed results is demonstrated through simulations. Full article

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the $0.35\mathsf{\mu }$m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications. Full article

Multi-protocol label switching (MPLS) is a promising solution to implement high-speed internet protocol (IP) networks by reducing the layer number. To meet the increasing demand for data traffic, optical packet switching (OPS) is integrated under IP to provide high bandwidth to end users. Generalized MPLS (GMPLS) is perfectly compatible with the routing algorithm in IP/MPLS as it supports packet-switching functions. In this paper, we investigate the label stacking scenarios in GMPLS networks. In GMPLS, label stacking is done to reduce the node complexity by appending multiple labels to a single packet. Wavelength-division multiplexing (WDM) and optical code-division multiplexing (OCDM) signals have been widely used as identifying labels. As the labels can be permutated among the wavelengths or code dimensions, the structure of a label stack can be varied. However, studies on the relationship between label stacking scenarios and network performance are limited. To investigate this issue, we propose three label stacking models: sequential code distribution; sequential wavelength distribution, and random label distribution. The simulation results show that the sequential wavelength assignment, wherein the labels are uniformly distributed among the wavelengths, exhibits the best system performance in terms of the label-error rate (LER). Full article

Source anonymity in wireless sensor networks (WSNs) becomes a real concern in several applications such as tracking and monitoring. A global adversary that has sophisticated resources, high computation and full view of the network is an obvious threat to such applications. The network and applications need to be protected and secured to provide the expected outcome. Source anonymity is one of the fundamental WSNs security issues. It is all about preventing the adversary from reaching the origin by analyzing the traffic of the network. There are many methods to provide source anonymity, which is also known as Source Location Privacy (SLP). One of these methods is based on dummy packets. The basic notion is to inject the network with dummy packets to confuse the adversary about the location of the transmitting source node. This paper provides a survey of protocols for anonymity that use dummy packet injections. We discuss each technique from the point of their advantages and disadvantages. Further, We provide a comparison for the most promising techniques provided in the literature which use dummy packet injections. A comparison for the adversary assumptions and capabilities will be provided as well. Full article

In this paper, we present a comprehensive study of smart grid security against cyber-physical attacks on its distinct functional components. We discuss: (1) a function-based methodology to evaluate smart grid resilience against cyber-physical attacks; (2) a Bayesian Attack Graph for Smart Grid (BAGS) tool to compute the likelihood of the compromise of cyber components of the smart grid system; (3) risk analysis methodology, which combines the results of the function-based methodology and BAGS to quantify risk for each cyber component of the smart grid; and (4) efficient resource allocation in the smart grid cyber domain using reinforcement learning (extension of BAGS tool) to compute optimal policies about whether to perform vulnerability assessment or patch a cyber system of the smart grid whose vulnerability has already been discovered. The results and analysis of these approaches help power engineers to identify failures in advance from one system component to another, develop robust and more resilient power systems and improve situational awareness and the response of the system to cyber-physical attacks. This work sheds light on the interdependency between the cyber domain and power grid and demonstrates that the security of both worlds requires the utmost attention. We hope this work assists power engineers to protect the grid against future cyber-physical attacks. Full article

Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications. Full article

In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products. Full article

High-power plasma power supply is very useful for many industrial and medical applications. Plasma is generated artificially in the laboratory or industry by applying the electric or magnetic field. In this manuscript, we presented the simple 4T analog MOS control high voltage high frequency inverter circuit as a plasma power supply using modulation index technique. The presented plasma power supply operated at 25 kHz frequency and 10 kV peak to peak voltage. It generates a 0 V to 10 kV controllable electric field. The generated electric field is applied and produces plasma, which can be used for many industrial applications. A 10 kV to 5 kW plasma power supply has been practically developed based on the proposed topology and experimentally tested and, additionally, excellent output power conversion efficiency is achieved. From these results, the 4T analog MOS control high voltage high frequency (HVHF) plasma switching power supply is verified. Full article

The visual tracking algorithm based on discriminative correlation filter (DCF) has shown excellent performance in recent years, especially as the higher tracking speed meets the real-time requirement of object tracking. However, when the target is partially occluded, the traditional single discriminative correlation filter will not be able to effectively learn information reliability, resulting in tracker drift and even failure. To address this issue, this paper proposes a novel tracking-by-detection framework, which uses multiple discriminative correlation filters called discriminative correlation filter bank (DCFB), corresponding to different target sub-regions and global region patches to combine and optimize the final correlation output in the frequency domain. In tracking, the sub-region patches are zero-padded to the same size as the global target region, which can effectively avoid noise aliasing during correlation operation, thereby improving the robustness of the discriminative correlation filter. Considering that the sub-region target motion model is constrained by the global target region, adding the global region appearance model to our framework will completely preserve the intrinsic structure of the target, thus effectively utilizing the discriminative information of the visible sub-region to mitigate tracker drift when partial occlusion occurs. In addition, an adaptive scale estimation scheme is incorporated into our algorithm to make the tracker more robust against potential challenging attributes. The experimental results from the OTB-2015 and VOT-2015 datasets demonstrate that our method performs favorably compared with several state-of-the-art trackers. Full article

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA. Full article

Stepper motors are employed in a wide range of consumer and industrial applications. Their use is simple: a digital device generates pulse-bursts and a direction bit towards a power driver that produces the 2-phase currents feeding the motor windings. Despite its simplicity, this open-loop approach fails if the torque load exceeds the motor capacity, so the motor and driver should be oversized at the expense of efficiency and cost. Field-Oriented closed-loop Control (FOC) solves the problem, and the recent availability of low cost electronics devices like Digital Signal Processors, Field Programmable Gate Arrays (FPGA), or even Microcontrollers with dedicated peripherals, fostered the investigation and implementation of several variants of the FOC method. In this paper, a simple and economic FOC torque control method for hybrid stepper motors is presented. The load angle is corrected accordingly to the actual shaft position through pulse-bursts and direction commands issued towards a commercial stepper driver, which manages the 2-phase winding currents. Thanks to the FPGA implementation, the control loop updates the electrical position every 50 μs only, thus allowing a load angle accuracy of −1/100 rad for a rotor velocity up to 750 rev/min, as shown in the reported experiments. Full article

In this work, a new real-time Simulation method is designed for nonlinear control techniques applied to power converters. We propose two different implementations: in the first one (Single Hardware in The Loop: SHIL), both model and control laws are inserted in the same Digital Signal Processor (DSP), and in the second approach (Double Hardware in The Loop: DHIL), the equations are loaded in different embedded systems. With this methodology, linear and nonlinear control techniques can be designed and compared in a quick and cheap real-time realization of the proposed systems, ideal for both students and engineers who are interested in learning and validating converters performance. The methodology can be applied to buck, boost, buck-boost, flyback, SEPIC and 3-phase AC-DC boost converters showing that the new and high performance embedded systems can evaluate distinct nonlinear controllers. The approach is done using matlab-simulink over commodity Texas Instruments Digital Signal Processors (TI-DSPs). The main purpose is to demonstrate the feasibility of proposed real-time implementations without using expensive HIL systems such as Opal-RT and Typhoon-HL. Full article

The implementation of a printed circuit board (PCB) drilling machine using recyclable materials and computer-aided control is presented. A mechanical system using a DC motor for movement on the X and Y axes, and a transmission mechanism by belts, pulleys, and a worm screw was made. For the Z axis, a mechanism based on a worm screw, nuts, and a stepper motor was implemented. The main board has two microcontrollers communicating in a master-slave configuration via a serial protocol. A real-time operating system (OSA) was implemented to optimize the data flow to the computer using the USB protocol, for communication with the slave microcontroller, positioning the Cartesian axes, and control the motors. The slave is responsible for monitoring the status of the encoders and limit switches, as well as the information delivery to the master. A Matlab-based user interface was developed to determine the coordinates of the holes to be drilled by processing a jpg image. This also allows the user to control the DC motors using PWM signals via configurable parameters of PID controllers. The end result is a drilling machine which able to operate both manually and via a computer, for drilling PCBs of a maximum size of 24 × 40 cm. Full article

In this paper, a novel transmission strategy for Mutliple Input Multiple Output Wideband Code Division Multiple Access (MIMO-WCDMA) orientations operating in frequency-selective fading environments is investigated, in terms of overall algorithmic complexity reduction. To this end, Principal Component Analysis (PCA) is employed on the received data matrix, in order to define the significant terms that are taken into account during transmission matrix formulation. According to the presented results, feedback information of only the primary eigenvector of the corresponding covariance matrix of the received data matrix is required, in order to maintain the mean Bit Error Rate (BER) at acceptable levels. In particular, a complexity reduction of up to 10% can be achieved, when comparing BER values derived by the selection of all components of the received covariance matrix during transmission matrix formulation, and the corresponding BER when selecting half of the components. This reduction is maintained to 10%, when considering a realistic four-element antenna design; however, in this case mean BER inaccuracy is further reduced to 1%. Full article

To handle the fast-growing demand for high data rate applications, the capacity of cellular networks should be reinforced. However, the available radio resources in cellular networks are scarce, and their formulation is expensive. The state-of-the art solution to this problem is a new local networking technology known as the device-to-device (D2D) communication. D2D communications have great capability in achieving outstanding performance by reusing the existing uplink cellular channel resources. In D2D communication, two devices in close proximity can communicate directly without traversing data traffic through the evolved-NodeB (eNB). This results in a reduced traffic load to the eNB, reduced end-to-end delay, and improved spectral efficiency and system performance. However, enabling D2D communication in an LTE-Advanced (LTE-A) cellular network causes severe interference to traditional cellular users and D2D pairs. To maintain the quality of service (QoS) of the cellular users and D2D pairs and reduce the interference, we propose a distance-based resource allocation and power control scheme using fractional frequency reuse (FFR) technique. We calculate the system outage probability, total throughput and spectrum efficiency for both cellular users and D2D pairs in terms of their signal-to-interference-plus-noise ratio (SINR). Our simulation results show that the proposed scheme reduces interference significantly and improves system performance compared to the random resource allocation (RRA) and resource allocation (RA) without sectorization scheme. Full article

The temperature of laminated busbars has to be limited to prevent their inner electrical insulators from over-heating. In that purpose, Finite Elements Method (FEM) simulations are usually conducted to evaluate the busbar's temperature. However, the thermal influence of external heat sources such as power modules has to be considered to obtain an accurate temperature repartition estimation. In this paper, the thermal influence of power modules on busbar temperature is first evaluated through simulation and experimental works. Then, a method based on the use of electrical equivalent circuits as boundary conditions is proposed to consider this issue and reduce the computation time. Full article