# Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Design of CPPLL

#### 2.1. Phase Frequency Detector (PFD)

_{max}) of PFD is related to the reset delay time (t

_{reset}), the relationship is f

_{max}≤ 1/2 t

_{reset}, and the reset delay time of the latch depends on the parasitic capacitance. The parasitic capacitance can be decrease by reducing the size of the transistor, so that to achieve faster speed. In addition, the proposed PFD is a fully differential structure, which can better suppress common mode noise.

#### 2.2. Charge Pump (CP)

_{DN1}≥ I

_{UP1}and I

_{DN2}≥ I

_{UP2}, and the unilateral conduction of D1 and D2, switch modules UPN and DNN are closed, and the current of current source module (I

_{UP1}and I

_{UP2}) flow to the current sinks (I

_{DN1}and I

_{DN2}). Therefore, leakage protection in the steady-state technique can prevent the leakage behavior of the capacitor in the loop filter for the current sink module. The charge pump can also appear in a steady state when the current source and current sink do not match. The current sink control module is composed of P1~P4. When V

_{C1}increases, the current of I

_{UP2}and the gate voltage (V

_{F1}) of I

_{DN1}decreases, and the current of I

_{DN1}increase. When V

_{C2}increases, the current of I

_{UP1}and the gate voltage (V

_{F2}) of I

_{DN2}increases, and the current of I

_{DN2}decrease. According to the above analysis, the current sink control module can ensure that the currents of I

_{DN1}and I

_{DN2}change with the currents of I

_{UP1}and I

_{UP2}, respectively. The current sink control technique can reduce the requirement of accurate matching between the current sink and current source. As long as the current of the current sink is greater than or equal to that of the current source, which reduces the difficulty of the design and improves the implement ability of the CP, this permits the output control voltage to remain unchanged when the loop is locked, which meets the demand of the CPPLL.

_{CN}of the charge pump is 5 mA, the static power consumption is 56 mW, and the area is 530 μm × 743 μm.

#### 2.3. Voltage-Controlled Oscillator (VCO)

_{gd}), and a variable capacitor array (C

_{tune}). M1 and M2 provide G

_{m}as negative resistance to compensate for the loss of the LC resonant circuit, which with a common source-amplifier configuration. The resonant circuit can be equivalent to two identical sub-resonant circuits and M1 and M2 provide energy for the two sub-resonant circuits to maintain oscillation through the cross-coupling structure. The differential structure can eliminate the influence of the common mode noise [22,23], and the swing amplitude of the output signal is:

#### 2.4. Frequency Divider (FD)

## 3. Measurement Result and Discussion

## 4. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 3.**The simulation results of PFD: (

**a**) the result of dead time; (

**b**) the result of the maximum operating frequency.

**Figure 7.**The measurement results of the VCO: (

**a**) the spectrum of the VCO; (

**b**) the tuning range of the VCO; (

**c**) the output power of the VCO.

**Figure 11.**The test results when the output signal is 3.584 GHz: (

**a**) the frequency spectrum; (

**b**) the phase noise.

**Figure 12.**The test results when the output signal is 4.021 GHz: (

**a**) the frequency spectrum; (

**b**) the phase noise.

**Figure 13.**The phase noise and output power when the output signal frequency is 3.584 GHz to 4.021 GHz.

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**MDPI and ACS Style**

Zhao, R.; Zhang, Y.; Lv, H.; Wu, Y.
Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process. *Sensors* **2022**, *22*, 504.
https://doi.org/10.3390/s22020504

**AMA Style**

Zhao R, Zhang Y, Lv H, Wu Y.
Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process. *Sensors*. 2022; 22(2):504.
https://doi.org/10.3390/s22020504

**Chicago/Turabian Style**

Zhao, Ranran, Yuming Zhang, Hongliang Lv, and Yue Wu.
2022. "Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process" *Sensors* 22, no. 2: 504.
https://doi.org/10.3390/s22020504