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Memristor-Based Loop Filter Design for Phase Locked Loop

Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USA
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J. Low Power Electron. Appl. 2019, 9(3), 24; https://doi.org/10.3390/jlpea9030024
Received: 30 May 2019 / Revised: 23 July 2019 / Accepted: 26 July 2019 / Published: 29 July 2019
The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations. View Full-Text
Keywords: filter; hysteresis curve; memristor; phase locked loop; voltage controlled oscillator filter; hysteresis curve; memristor; phase locked loop; voltage controlled oscillator
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Adesina, N.O.; Srivastava, A. Memristor-Based Loop Filter Design for Phase Locked Loop. J. Low Power Electron. Appl. 2019, 9, 24.

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