Next Article in Journal
Implementation of Grading Method for Gambier Leaves Based on Combination of Area, Perimeter, and Image Intensity Using Backpropagation Artificial Neural Network
Previous Article in Journal
Technical and Economic Assessment of VSC-HVDC Transmission Model: A Case Study of South-Western Region in Pakistan
Open AccessArticle

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Graduate School of Engineering, Osaka University, Suita-shi, Osaka 565-0871, Japan
Authors to whom correspondence should be addressed.
Electronics 2019, 8(11), 1307;
Received: 14 October 2019 / Accepted: 5 November 2019 / Published: 7 November 2019
(This article belongs to the Section Circuit and Signal Processing)
This paper demonstrates the design and implementation of an all-digital phase-locked loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique to show the feasibility and effectiveness of the ADPLL in the early design stage. A Δ - Σ modulator (DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, which is fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control and fractional tuning range using the DSM. The ring-DCO does not contain library-specific cells and can be synthesized independently of the standard cell library, thus making the design portable and reducing the time required to fit for different semiconductor processes considerably. Implemented ring-DCO has a wide tuning range and high-frequency resolution which meet the demands of system-level integration. The ADPLL implemented in this work has the characteristics of design flexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast response for achieving a locked state. The proposed ADPLL can be easily ported to different processes in a short time. The design adaptation cost is limited to adjustment of loop parameters in the code. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications. View Full-Text
Keywords: all-digital phase-locked loop; digitally controlled oscillator; FPGA all-digital phase-locked loop; digitally controlled oscillator; FPGA
Show Figures

Figure 1

MDPI and ACS Style

Radhapuram, S.; Yoshihara, T.; Matsuoka, T. Design and Emulation of All-Digital Phase-Locked Loop on FPGA. Electronics 2019, 8, 1307.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

Back to TopTop