Design and Emulation of All-Digital Phase-Locked Loop on FPGA
loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique
to show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator
(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, which
is fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control and
fractional tuning range using the DSM. The ring-DCO does not contain library-specific cells and
can be synthesized independently of the standard cell library, thus making the design portable and
reducing the time required to fit for different semiconductor processes considerably. Implemented
ring-DCO has a wide tuning range and high-frequency resolution which meet the demands of
system-level integration. The ADPLL implemented in this work has the characteristics of design
flexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast response
for achieving a locked state. The proposed ADPLL can be easily ported to different processes in
a short time. The design adaptation cost is limited to adjustment of loop parameters in the code.
Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for
System-on-Chip (SoC) applications.
Radhapuram, S.; Yoshihara, T.; Matsuoka, T. Design and Emulation of All-Digital Phase-Locked Loop on FPGA. Electronics 2019, 8, 1307.
Radhapuram S, Yoshihara T, Matsuoka T. Design and Emulation of All-Digital Phase-Locked Loop on FPGA. Electronics. 2019; 8(11):1307.Chicago/Turabian Style
Radhapuram, Saichandrateja; Yoshihara, Takuya; Matsuoka, Toshimasa. 2019. "Design and Emulation of All-Digital Phase-Locked Loop on FPGA." Electronics 8, no. 11: 1307.