Special Issue "Microwave Integrated Circuits Design and Application"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 July 2020).

Special Issue Editor

Prof. Dr. Jung-Dong Park
Website
Guest Editor
Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea
Interests: Analog/RFIC, Microwave Electronics, CMOS, Device, Antennas

Special Issue Information

Dear Colleagues,

Traditionally, the phased array system has been widely applied in military fields, owing to its adaptive and agile beam controllability for multiple target tracking capability. With the advancement of electronic circuit technology, the phased array antenna, which is the smart antenna in a broader sense, has found global attention in commercial sensing and communications, such as autonomous vehicle and 5G mobile applications, which require wideband technology. In order to satisfy the stringent technological requirements in developing the cost-effective, compact, and wideband phased array system for vehicle and 5G mobile applications, significant efforts have been invested in developing new signal processing schemes and wideband analog/RF technologies.

This Special Issue focuses on the analysis, design, and implementation of the analog/RF; mixed circuit blocks; and cost-effective signal processing schemes applicable for the compact wideband phased array system. The topics of interest include, but are not limited to, the following:

  • Analog/RF IC technologies for wideband operation
  • Energy efficient transceiver design and architecture
  • Wideband Tx/Rx module for agile phase shifting
  • True time delay (TTD) phase shifters
  • Cost-effective signal processing scheme for the wideband phased array system
  • Various analog and digital beamforming technologies.

Prof. Dr. Jung-Dong Park
Guest Editor

Manuscript Submission Information

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Published Papers (5 papers)

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Research

Open AccessArticle
A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS
Electronics 2020, 9(9), 1502; https://doi.org/10.3390/electronics9091502 - 13 Sep 2020
Abstract
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. [...] Read more.
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits. Full article
(This article belongs to the Special Issue Microwave Integrated Circuits Design and Application)
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Open AccessArticle
High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler
Electronics 2020, 9(5), 725; https://doi.org/10.3390/electronics9050725 - 28 Apr 2020
Cited by 1
Abstract
This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation [...] Read more.
This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers. Full article
(This article belongs to the Special Issue Microwave Integrated Circuits Design and Application)
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Open AccessFeature PaperArticle
A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process
Electronics 2020, 9(1), 146; https://doi.org/10.3390/electronics9010146 - 12 Jan 2020
Cited by 1
Abstract
In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to [...] Read more.
In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2. Full article
(This article belongs to the Special Issue Microwave Integrated Circuits Design and Application)
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Open AccessArticle
A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS
Electronics 2019, 8(10), 1149; https://doi.org/10.3390/electronics8101149 - 11 Oct 2019
Cited by 1
Abstract
A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance [...] Read more.
A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm2. Full article
(This article belongs to the Special Issue Microwave Integrated Circuits Design and Application)
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Open AccessFeature PaperArticle
A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology
Electronics 2019, 8(9), 1043; https://doi.org/10.3390/electronics8091043 - 17 Sep 2019
Cited by 2
Abstract
We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with [...] Read more.
We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads. Full article
(This article belongs to the Special Issue Microwave Integrated Circuits Design and Application)
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