Journal of Low Power Electronics and Applications — Open Access Journal

Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 $\mathsf{\mu }$ m and 0.35 $\mathsf{\mu }$ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals. Full article

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations. Full article

With the continuous growth of energy consumption, the rationalization of energy has become a priority. The photovoltaic energy sector remains a major occupation for researchers in the field of production optimization or storage methods. The concept developed in this work is a mixed optimization approach for energy management during battery charging with a duty cycle. A selective collaborative algorithm intervenes to choose and use the appropriate results of the few techniques to optimize the charging time of a battery and estimate its state of charge by using the minimum possible tools. This is done using a collective database that is accessible in real time. It also effectively allows the synchronization of information between several customers. This approach is performed on a mobile application on android, through a Google Firebase platform that allows us to secure collaborative access between multiple customers and use the results of the calculations of some algorithms. It gives us the values obtained by the various sensors in real time to accelerate the charging speed of the battery. The validation of this approach led us to practice a few scenarios using an Arduino board to show that this approach has a better performance. Full article

This paper describes an innovative solution for the power supply of a fast field cycling (FFC) nuclear magnetic resonance (NMR) spectrometer considering its low power consumption, portability and low cost. In FFC cores, the magnetic flux density must be controlled in order to perform magnetic flux density cycles with short transients, while maintaining the magnetic flux density levels with high accuracy and homogeneity. Typical solutions in the FFC NMR literature use current control to get the required magnetic flux density cycles, which correspond to an indirect magnetic flux density control. The main feature of this new relaxometer is the direct control of the magnetic flux density instead of the magnet current, in contrast with other equipment available in the market. This feature is a great progress because it improves the performance. With this solution it is possible to compensate magnetic field disturbances and parasitic magnetic fields guaranteeing, among other possibilities, a field control below the earth magnetic field. Experimental results validating the developed solution and illustrating the real operation of this type of equipment are shown. Full article

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature. Full article

Ultrasonic power transfer (UPT) is a promising method for wireless power transfer technology for low-power medical applications. Most portable or wearable medical devices are battery-powered. Batteries cannot be used for a long time and require periodic charging or replacement. UPT is a candidate technology for solving this problem. In this work, a 40-KHz ultrasound transducer was used to design a new prototype for supplying power to a wearable heart rate sensor for medical application. The implemented system consists of a power unit and heart rate measurement unit. The power unit includes an ultrasonic transmitter and receiver, rectifier, boost converter and super-capacitors. The heart rate measurement unit comprises measurement and monitoring circuits. UPT-based transfer power and efficiency were achieved using 1-, 4- and 8-Farad (F) super-capacitors. At 4 F, the system achieved 69.4% transfer efficiency and 0.318 mW power at 4 cm. In addition, 97% heart rate measurement accuracy was achieved relative to the benchmark device. The heart rate measurements were validated with statistical analysis. Our results show that this work outperforms previous works in terms of transfer power and efficiency with a 4-cm gap between the ultrasound transmitter and receiver. Full article

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method. Full article

Scan-based structural testing methods have seen numerous inventions in scan compression techniques to reduce TDV (test data volume) and TAT (test application time). Compression techniques lead to test coverage (TC) loss and test patterns count (TPC) inflation when higher compression ratio is targeted. This happens because of the correlation issues introduced by these techniques. To overcome this issue, we propose a new hybrid scan compression technique, the aggressive exclusion (AE) of scan cells from compression for increasing overall TC and reduce TPC. This is achieved by excluding scan cells which contribute to 12% to 43% of overall care bits from compression architecture, placing them in multiple scan chains with dedicated scan-data-in and scan-data-out ports. The selection of scan cells to be excluded from the compression technique is done based on a detailed analysis of the last 95% of the patterns from a pattern set to reduce correlations. Results show improvements in TC of up to 1.33%, and reductions in TPC of up to 77.13%. Full article

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology. Full article

The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application. Full article

Magnetic tunnel junction (MTJ) with a voltage-controlled magnetic anisotropy (VCMA) effect has been introduced to achieve robust non-volatile writing control with an electric field or a switching voltage. However, continuous technology scaling down makes circuits more susceptible to temporary faults. The reliability of VCMA-MTJ-based magnetoelectric random access memory (MeRAM) can be impacted by environmental disturbances because a radiation strike on the access transistor could introduce write and read failures in 1T-1MTJ MeRAM bit-cells. In this work, Single-Event Transient (SET) effects on a VCMA-MTJ-based MeRAM in 28 nm FDSOI CMOS technology are investigated. Results show the minimum SET charge $Q_c$ required to reach the access transistor associated with the striking time that can lead to an unsuccessful switch, that is, an error in the writing process (write failure). The synchronism between the fluctuations of the magnetic field in the MTJ free layer and the moment of the write pulse is also analyzed in terms of SET robustness. Moreover, results show that the minimum $Q_c$ value can vary more than $100\%$ depending on the magnetic state of the MTJ and the width of the access transistor. In addition, the most critical time against the SET occurrence may be before or after the write pulse depending on the magnetic state of the MTJ. Full article

Flexible electronics is a field gathering a growing interest among researchers and companies with widely varying applications, such as organic light emitting diodes, transistors as well as many different sensors. If the circuit should be portable or off-grid, the power sources available are batteries, supercapacitors or some type of power generator. Thermoelectric generators produce electrical energy by the diffusion of charge carriers in response to heat flux caused by a temperature gradient between junctions of dissimilar materials. As wearables, flexible electronics and intelligent packaging applications increase, there is a need for low-cost, recyclable and printable power sources. For such applications, printed thermoelectric generators (TEGs) are an interesting power source, which can also be combined with printable energy storage, such as supercapacitors. Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate), or PEDOT:PSS, is a conductive polymer that has gathered interest as a thermoelectric material. Plastic substrates are commonly used for printed electronics, but an interesting and emerging alternative is to use paper. In this article, a printed thermoelectric generator consisting of PEDOT:PSS and silver inks was printed on two common types of paper substrates, which could be used to power electronic circuits on paper. Full article

In this paper, the performance of coded systems is considered in the presence of Suzuki fading channels, which is a combination of both short-fading and long-fading channels. The problem in manipulating a Suzuki fading model is the complicated integration involved in the evaluation of the Suzuki probability density function (PDF). In this paper, we calculated noise PDF after the zero-forcing equalizer (ZFE) at the receiver end with several approaches. In addition, we used the derived PDF to calculate the log-likelihood ratios (LLRs) for turbo-coded systems, and results were compared to Gaussian distribution-based LLRs. The results showed a 2 dB improvement in performance compared to traditional LLRs at ${10}^{-6}$ of the bit error rate (BER) with no added complexity. Simulations were obtained utilizing the Matlab program, and results showed good improvement in the performance of the turbo-coded system with the proposed LLRs compared to Gaussian-based LLRs. Full article

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. Full article

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure. Full article

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation. Full article

The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks. Full article

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. Full article

Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead. Full article