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Journal of Low Power Electronics and Applications (ISSN 2079-9268) is an international, interdisciplinary, peer-reviewed, open access journal on low power electronics and is published quarterly online by MDPI.
- Open Access - free for readers, with article processing charges (APC) paid by authors or their institutions.
- High visibility: covered by Inspec (IET) and Scopus.
- Rapid publication: manuscripts are peer-reviewed and a first decision provided to authors approximately 17.8 days after submission; acceptance to publication is undertaken in 6.6 days (median values for papers published in this journal in the second half of 2018).
- Recognition of reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Latest Articles
Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
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J. Low Power Electron. Appl. 2019, 9(1), 12; https://doi.org/10.3390/jlpea9010012 - 11 March 2019
Abstract
With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway
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With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
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Tolerating Permanent Faults in the Input Port of the Network on Chip Router
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J. Low Power Electron. Appl. 2019, 9(1), 11; https://doi.org/10.3390/jlpea9010011 - 27 February 2019
Abstract
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing
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Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
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Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET
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J. Low Power Electron. Appl. 2019, 9(1), 10; https://doi.org/10.3390/jlpea9010010 - 26 February 2019
Abstract
In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving
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In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.
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A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era
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J. Low Power Electron. Appl. 2019, 9(1), 9; https://doi.org/10.3390/jlpea9010009 - 19 February 2019
Abstract
The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the
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The Internet-of-Things (IoT) revolution has shaped a new application domain where low-power RISC architectures constitute the standard computational backbone. The current de-facto design practice for such architectures is to extend the ISA and the corresponding microarchitecture with custom instructions to efficiently manage the complex tasks imposed by IoT applications, i.e., augmented reality, artificial intelligence and autonomous driving, within narrow energy and area budgets. However, the new IoT application domain also offers a unique opportunity to revisit and optimize the RISC microarchitectural design flow from a more communication- and memory-centric viewpoint. This manuscript critically explores and optimizes the design of a RISC CPU front-end for IoT delivering a two-fold objective: (i) provide an optimized CPU microarchitecture; and (ii) present a set of three design guidelines to steer the implementation of IoT CPUs. The exploration sits on a newly proposed Systems-on-Chip (SoC) and RISC CPU implementing the RISC-V/IMF ISA and accounting for area, timing, and performance design metrics. Such SoC offers a reference design to evaluate pros and cons of different microarchitectural solutions. A wide combination of microarchitectures considering different branch prediction schemes, cache design architectures and on-chip bus solutions have been evaluated. The entire exploration is focused on the FPGA-based implementation due to the renewed interest for this technology demonstrated by both the research community and companies. We note that ARM launched the DesignStart FPGA program to make available the Cortex-M microcontrollers on Xilinx FPGAs in the form of IP blocks.
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A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
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J. Low Power Electron. Appl. 2019, 9(1), 8; https://doi.org/10.3390/jlpea9010008 - 14 February 2019
Abstract
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning
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Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.
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DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures
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J. Low Power Electron. Appl. 2019, 9(1), 7; https://doi.org/10.3390/jlpea9010007 - 5 February 2019
Abstract
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used
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Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.
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High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits
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J. Low Power Electron. Appl. 2019, 9(1), 6; https://doi.org/10.3390/jlpea9010006 - 29 January 2019
Abstract
In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net
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In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask.
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Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience
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J. Low Power Electron. Appl. 2019, 9(1), 5; https://doi.org/10.3390/jlpea9010005 - 21 January 2019
Abstract
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not
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Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.
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Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems
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J. Low Power Electron. Appl. 2019, 9(1), 4; https://doi.org/10.3390/jlpea9010004 - 21 January 2019
Abstract
This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results,
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This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption. As in digital systems, a strong architecture theory, based on experimental results, is essential for these opportunities. The recent availability of programmable and configurable analog technologies, as well as the start of analog numerical analysis, makes considering scaling of analog computation more than a purely theoretical interest. Although some aspects nicely parallel digital architecture concepts, analog architecture theory requires revisiting some of the foundations of parallel digital architectures, particularly revisiting structures where communication and memory access, instead of processor operations, that dominates complexity. This discussion shows multiple system examples from Analog-to-Digital Converters (ADC) to Vector-Matrix Multiplication (VMM), adaptive filters, image processing, sorting, and other computing directions.
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A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception
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J. Low Power Electron. Appl. 2019, 9(1), 3; https://doi.org/10.3390/jlpea9010003 - 21 January 2019
Abstract
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such
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Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.
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Modularity for Paralleling Different Rated Power Supplies Using Multi-Phase Switching Methods
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J. Low Power Electron. Appl. 2019, 9(1), 1; https://doi.org/10.3390/jlpea9010001 - 16 January 2019
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This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect
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This paper proposes a modularity for paralleling different rated power supplies without adding a circuit in the feedback loop by using direct and overlapped switching methods. Unlike an isolated output diode, the use of an isolated output switch composed of two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can reduce power dissipation. The control module includes switches and a micro-programmed controlled unit that realizes the modularity by using multi-phase switching methods. The proposed module was studied, and experiments of two rated power supplies (60 and 45 W) were conducted to verify the studied results.
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Design and Evaluation of an Electrical Bioimpedance Device Based on DIBS for Myography during Isotonic Exercises
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J. Low Power Electron. Appl. 2018, 8(4), 50; https://doi.org/10.3390/jlpea8040050 - 15 December 2018
Abstract
Electrical Bioimpedance Spectroscopy (EIS) is a technique used to assess passive electrical properties of biological materials. EIS detects physiological and pathological conditions in animal tissues. Recently, the introduction of broadband excitation signals has reduced the measuring time for application techniques such as Electrical
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Electrical Bioimpedance Spectroscopy (EIS) is a technique used to assess passive electrical properties of biological materials. EIS detects physiological and pathological conditions in animal tissues. Recently, the introduction of broadband excitation signals has reduced the measuring time for application techniques such as Electrical Bioimpedance Myography. Therefore, this work is aimed at proposing a prototype by using discrete interval binary sequences (DIBS), which is based on a system that holds a current source, impedance acquisition system, microcontroller and graphical user interface. Measurements between 5 Ω to 5 kΩ had impedance acquisition and phase angle errors of aproximately 2% and were lower than 3 degrees, respectively. Based on a proposed circuit, bioimpedance of the chest muscle (Pectoralis Major) was measured during isotonic exercise (push-up). As a result, our analyses have detected tiredness and fatigue. We have explored and proposed new parameters which assess such conditions, as both the maximum magnitude and tiredness coefficient. These parameters decrease exponentially with consecutive push-ups and were convergent in the majority of the sixteen days of measurement.
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Enhancing Reliability of Tactical MANETs by Improving Routing Decisions
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J. Low Power Electron. Appl. 2018, 8(4), 49; https://doi.org/10.3390/jlpea8040049 - 28 November 2018
Abstract
Mobile ad-hoc networks (MANETs) have been primarily designed to enhance tactical communications in a battlefield. They provide dynamic connectivity without requiring any pre-existing infrastructure. Their multi-hop capabilities can improve radio coverage significantly. The nature of tactical MANET operations requires more specialized routing protocols
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Mobile ad-hoc networks (MANETs) have been primarily designed to enhance tactical communications in a battlefield. They provide dynamic connectivity without requiring any pre-existing infrastructure. Their multi-hop capabilities can improve radio coverage significantly. The nature of tactical MANET operations requires more specialized routing protocols compared to the ones which are used in commercial MANET. Routing decisions in MANETs are usually conditioned on signal-to-interference-plus-noise ratio (SINR) measurements. In order to improve routing decisions for use in highly dynamic tactical MANETs, this paper proposes to combine two different metrics to achieve reliable multicast in multi-hop ad hoc networks. The resulting protocol combining received signal strength (RSS) with SINR to make routing decisions is referred to as Link Quality Aware Ad-hoc On-Demand Distance Vector (LQA-AODV) routing. The proposed routing protocol can quickly adapt to dynamic changes in network topology and link quality variations often encountered in tactical field operations. Using computer simulations, the performance of proposed protocol is shown to outperform other widely used reactive routing protocols assuming several performance metrics.
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Towards Energy-Efficient and Secure Computing Systems
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J. Low Power Electron. Appl. 2018, 8(4), 48; https://doi.org/10.3390/jlpea8040048 - 27 November 2018
Abstract
Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives
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Countermeasures against diverse security threats typically incur noticeable hardware cost and power overhead, which may become the obstacle for those countermeasures to be applicable in energy-efficient computing systems. This work presents a summary of energy-efficiency techniques that have been applied in security primitives or mechanisms to ensure computing systems’ resilience against various security threats on hardware. This work also uses examples to discuss practical methods for securing the hardware for computing systems to achieve energy efficiency.
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Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse
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J. Low Power Electron. Appl. 2018, 8(4), 47; https://doi.org/10.3390/jlpea8040047 - 24 November 2018
Abstract
This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well
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This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.
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Low-Complexity Loeffler DCT Approximations for Image and Video Coding
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J. Low Power Electron. Appl. 2018, 8(4), 46; https://doi.org/10.3390/jlpea8040046 - 22 November 2018
Abstract
This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature.
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This paper introduced a matrix parametrization method based on the Loeffler discrete cosine transform (DCT) algorithm. As a result, a new class of 8-point DCT approximations was proposed, capable of unifying the mathematical formalism of several 8-point DCT approximations archived in the literature. Pareto-efficient DCT approximations are obtained through multicriteria optimization, where computational complexity, proximity, and coding performance are considered. Efficient approximations and their scaled 16- and 32-point versions are embedded into image and video encoders, including a JPEG-like codec and H.264/AVC and H.265/HEVC standards. Results are compared to the unmodified standard codecs. Efficient approximations are mapped and implemented on a Xilinx VLX240T FPGA and evaluated for area, speed, and power consumption.
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Including Liquid Metal into Porous Elastomeric Films for Flexible and Enzyme-Free Glucose Fuel Cells: A Preliminary Evaluation
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J. Low Power Electron. Appl. 2018, 8(4), 45; https://doi.org/10.3390/jlpea8040045 - 22 November 2018
Abstract
This communication introduces a new flexible elastomeric composite film, which can directly convert the chemical energy of glucose into electricity. The fabrication process is simple, and no specific equipment is required. Notably, the liquid metal Galinstan is exploited with a two-fold objective: (i)
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This communication introduces a new flexible elastomeric composite film, which can directly convert the chemical energy of glucose into electricity. The fabrication process is simple, and no specific equipment is required. Notably, the liquid metal Galinstan is exploited with a two-fold objective: (i) Galinstan particles are mixed with polydimethylsiloxane to obtain a highly conductive porous thick film scaffold; (ii) the presence of Galinstan in the composite film enables the direct growth of highly catalytic gold structures. As a first proof of concept, we demonstrate that when immersed in a 20 mM glucose solution, a 5 mm-long, 5 mm-wide and 2 mm-thick sample can generate a volumetric power density up to 3.6 mW·cm
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A Recent Progress of Spintronics Devices for Integrated Circuit Applications
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J. Low Power Electron. Appl. 2018, 8(4), 44; https://doi.org/10.3390/jlpea8040044 - 13 November 2018
Abstract
Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types
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Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy. The NV memories using STT have been studied and developed most actively and are about to enter into the market by major semiconductor foundry companies. On the other hand, a development of the NV memories using other writing schemes are now underway. In this review article, first, the recent advancement of the spintronics device using STT and the NV memories using them are reviewed. Next, spintronics devices using the other two writing schemes (SOT and E-field) are briefly reviewed, including issues to be addressed for the NV memories application.
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Low-Cost Low-Power Acceleration of a Microwave Imaging Algorithm for Brain Stroke Monitoring
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J. Low Power Electron. Appl. 2018, 8(4), 43; https://doi.org/10.3390/jlpea8040043 - 1 November 2018
Abstract
Microwave imaging can effectively image the evolution of a hemorrhagic stroke thanks to the dielectric contrast between the blood and the surrounding brain tissues. To keep low both the form factor and the power consumption in a bedside device, we propose implementing a
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Microwave imaging can effectively image the evolution of a hemorrhagic stroke thanks to the dielectric contrast between the blood and the surrounding brain tissues. To keep low both the form factor and the power consumption in a bedside device, we propose implementing a microwave imaging algorithm for stroke monitoring in a programmable system-on-chip, in which a simple ARM-based CPU offloads to an FPGA the heavy part of the computation. Compared to a full-software implementation in the ARM CPU, we obtain a 5× speed increase with hardware acceleration without loss in accuracy and precision.
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