Journal of Low Power Electronics and Applications

17 pages, 2015 KB

Open AccessArticle

Efficient Battery State of Health Estimation Using Lightweight ML Models Based on Limited Voltage Measurements

by Mohammad Okour, Mohannad Alkhalil, Mutaz Al Fayad, Juhyun Bak, Kevin R. James, Sulaiman Mohaidat, Xiaoqi Liu, Fadi Alsaleem, Michael Hempel, Hamid Sharif-Kashani and Mahmoud Alahmad

J. Low Power Electron. Appl. 2026, 16(2), 16; https://doi.org/10.3390/jlpea16020016 - 21 Apr 2026

Abstract

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight [...] Read more.

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight SoH-prediction framework validated on both physics-informed synthetic aging data and the NASA battery aging dataset. We evaluated Random Forest (RF) and Feedforward Neural Network (FNN) models that use only a limited number of samples from an early segment of the raw discharge voltage curve as input. Results show that RF consistently outperforms FNN across input sizes in deterministic or noise-free environments, achieving an RMSE of 0.07% SoH using just 5 voltage samples. In inherently stochastic experimental data, however, FNN can achieve an RMSE 50% lower than RF (1.28 vs. 2.87), but requires 37× more mathematical operations per inference. These findings emphasize the predictive value of the early-discharge-voltage region and demonstrate that compact, low-feature-complexity models can deliver accurate SoH estimates. Overall, the approach supports a goal of combining informed synthetic data with limited real measurements to build robust, scalable SoH predictors, reducing dependence on labor-intensive degradation testing and feature-heavy pipelines. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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19 pages, 5661 KB

Open AccessArticle

Low-Cost Smart Ammeter for Autonomous Contactless IoT Power Monitoring

by Nicolas Medrano, Diego Antolin, Daniel Eneriz and Belen Calvo

J. Low Power Electron. Appl. 2026, 16(2), 15; https://doi.org/10.3390/jlpea16020015 - 18 Apr 2026

Abstract

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The [...] Read more.

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The differential configuration of the sensor module and the subsequent fully digital programmability in range and sensitivity, together with the included self-calibration and compensation circuits for mismatching, managed by a microcontroller, allow for optimum detection for both continuous and mains current with a resolution of 10 mA for input ranges of 2 A. The proposed ammeter power consumption and measurement accuracy in different scenarios are tested, including the power monitoring of an IoT-based device, obtaining results matched to those featured by a commercial oscilloscope current probe, which validates its suitability and reliability as autonomous low-cost probe for portable contactless power monitoring. Full article

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16 pages, 1361 KB

Open AccessArticle

RF/mm-Wave Frequency Doublers in CMOS Technology

by Manfredi Caruso, Andrea Ballo, Minoo Eghtesadi and Egidio Ragonese

J. Low Power Electron. Appl. 2026, 16(2), 14; https://doi.org/10.3390/jlpea16020014 - 13 Apr 2026

Abstract

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, [...] Read more.

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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21 pages, 9981 KB

Open AccessArticle

Forward-Flyback Resonant Topology with Edge AI for MPPT Control in Solar Power Generation

by Juan Cruz-Cozar, Javier Mendez, Miguel Molina, Jorge Perez-Martinez, Alberto Martin-Martin, Noel Rodriguez and Diego P. Morales

J. Low Power Electron. Appl. 2026, 16(2), 13; https://doi.org/10.3390/jlpea16020013 - 12 Apr 2026

Abstract

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the [...] Read more.

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology. Full article

(This article belongs to the Special Issue 15th Anniversary of Journal of Low Power Electronics and Applications)

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18 pages, 3099 KB

Open AccessArticle

A 0.3 V Nanowatt Bulk-Driven CCII⁻ in 0.18-µm CMOS for Ultra-Low-Power Current-Mode Interfaces

by Giovanni Nicolini, Alessio Passaquieti, Giuseppe Scotti and Riccardo Della Sala

J. Low Power Electron. Appl. 2026, 16(2), 12; https://doi.org/10.3390/jlpea16020012 - 8 Apr 2026

Abstract

A 0.3 V nanowatt CCII⁻ is presented in 0.18

μ

m TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 [...] Read more.

A 0.3 V nanowatt CCII⁻ is presented in 0.18

μ

m TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are

β_{0} = 0.9452

(−0.48 dB) and

α_{0} = 0.9609

(≈−0.35 dB), with

- 3

dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding

R_{X} = 46.73

M

Ω

,

R_{Z} = 1.204

G

Ω

, and a very high input resistance

R_{Y} = 392

G

Ω

. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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32 pages, 8214 KB

Open AccessArticle

Static Voltage Stability Assessment of Renewable Energy Power Systems Based on DBN-LSTM Power Forecasting

by Qiang Wang, Libo Yang, Mengdi Wang, Bin Ma, Long Yuan, Shaobo Li and Zhangjie Liu

J. Low Power Electron. Appl. 2026, 16(2), 11; https://doi.org/10.3390/jlpea16020011 - 24 Mar 2026

Cited by 1

Abstract

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A [...] Read more.

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A low-conservativeness analytical criterion is first derived for static voltage stability margin assessment. Then, a hybrid Deep Belief Network–Long Short-Term Memory (DBN–LSTM) model is developed for accurate renewable power forecasting, capturing temporal variability and uncertainty. Finally, UFLS-based stability-constrained dispatch is formulated to prevent voltage collapse, enhance the system stability, and minimize RES curtailment. Simulations on a modified IEEE benchmark system demonstrate that the proposed approach improves voltage and frequency stability while maintaining high renewable energy utilization. Full article

(This article belongs to the Special Issue Energy Consumption Management in Electronic Systems)

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13 pages, 4238 KB

Open AccessArticle

An Analog-Inspired Secure 2.4 GHz FSK Transmitter Front-End with Embedded Calibration in 22 nm FDSOI CMOS

by Yu Qi, Hossein Yaghobi and Hossein Miri Lavasani

J. Low Power Electron. Appl. 2026, 16(1), 10; https://doi.org/10.3390/jlpea16010010 - 27 Feb 2026

Abstract

This paper presents a secure 2.4 GHz frequency shift keying (FSK) transmitter front-end with minimal overhead on the data stream using analog obfuscation techniques applied to the modulated waveform. An off-chip true random number generator (TRNG) unit is used to generate the required [...] Read more.

This paper presents a secure 2.4 GHz frequency shift keying (FSK) transmitter front-end with minimal overhead on the data stream using analog obfuscation techniques applied to the modulated waveform. An off-chip true random number generator (TRNG) unit is used to generate the required key for the encryption. Moving away from traditional FSK schemes, which benefit from constant local oscillator (LO) frequency within the channel, the proposed secure FSK scheme shifts the LO frequency in very small steps using an innovative capacitor-bank structure with a calibrated digitally controlled oscillator (DCO). The proposed capacitor bank uses a combination of parallel switches and series capacitors to minimize the impact of the layout parasitics on the minimum capacitor in the bank, thereby reliably creating sub-fF unit capacitors. When combined with the proposed capacitor bank, the cross-coupled CMOS LC voltage-controlled oscillator (VCO) forms a digitally controlled oscillator (DCO). The post-layout simulation results of the DCO reveal that the proposed scheme can achieve a resolution of <20 kHz for the LO frequency shifting while maintaining the phase-noise performance. The reported phase shift allows an equivalent entropy > 6 bits in the implemented analog-inspired secure transmitter front-end. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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19 pages, 1057 KB

Open AccessArticle

Efficient Energy Consumption: Leveraging AI Models for Appliance Detection

by Gerardo Arno Sonck-Martinez, Victor A. Gonzalez-Huitron, Abraham Efraím Rodríguez-Mata, Isidro Robledo-Vega, Guillermo Valencia-Palomo and Jose-Agustin Almaraz-Damian

J. Low Power Electron. Appl. 2026, 16(1), 9; https://doi.org/10.3390/jlpea16010009 - 25 Feb 2026

Abstract

This research addresses the increasing need for efficient energy management in residential settings in response to the increasing global energy demands, focusing on the integration of artificial intelligence to identify energy burdens. We employ and compare some machine learning models, like Decision Trees, [...] Read more.

This research addresses the increasing need for efficient energy management in residential settings in response to the increasing global energy demands, focusing on the integration of artificial intelligence to identify energy burdens. We employ and compare some machine learning models, like Decision Trees, K-nearest neighbors, and Feedforward Neural Networks, with a primary focus on electrical current as a key parameter. The Fine K-NN model shows notable efficiency, achieving an accuracy of 99.1% in the identification of active household appliances using a single sensor. Our methodology encompasses rigorous data acquisition and preprocessing under controlled experimental conditions, ensuring the integrity and reliability of our results. This study contributes to the field by illustrating the effectiveness of specific AI models in energy management under controlled conditions, paving the way for future advancements in AI-driven energy conservation strategies. Full article

(This article belongs to the Special Issue Energy Consumption Management in Electronic Systems)

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35 pages, 9979 KB

Open AccessReview

Applications of MXenes in Neuromorphic Computing and Memristors: From Material Synthesis and Physical Mechanisms to Integrated Sensing, Memory, and Computation

by Yifeng Fu and Jianguang Xu

J. Low Power Electron. Appl. 2026, 16(1), 8; https://doi.org/10.3390/jlpea16010008 - 25 Feb 2026

Abstract

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. [...] Read more.

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti₃C₂T_x) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation. Full article

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17 pages, 4778 KB

Open AccessArticle

A Low-Power LoRa-Based Multi-Nodal Wireless Sensor Network with Custom Communication Framework for Rockfall Monitoring

by Paolo Esposito, Vincenzo Stornelli and Giuseppe Ferri

J. Low Power Electron. Appl. 2026, 16(1), 7; https://doi.org/10.3390/jlpea16010007 - 17 Feb 2026

Abstract

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in [...] Read more.

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in both the node-gateway side and the gateway-user interface side. In particular, the communication framework is entirely IoT-based, featuring both the MQTT protocol, for the direct control of apparatuses from the system user interface, and the more traditional TCP/IP protocol, implemented on NB-IoT. The proposed system is entirely solar-powered and features a 34.68 mWh/day consumption. Around a single communication session, the average power consumption inside the single node amounts to 1.4 mW. This paper gives an overview of the proposed system, with detailed explanations of each part, and measurements retrieved over a wide period to assess the functionality of the system. Full article

(This article belongs to the Topic Application of IOT on Manufacturing, Communication and Engineering, 2nd Volume)

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29 pages, 3191 KB

Open AccessArticle

A Q-Learning-Based Hierarchical Power Delivery Architecture for the Efficient Management of Heterogeneous Loads

by Andreas Tsiougkos, Georgia Amanatiadou and Vasilis F. Pavlidis

J. Low Power Electron. Appl. 2026, 16(1), 6; https://doi.org/10.3390/jlpea16010006 - 28 Jan 2026

Abstract

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), [...] Read more.

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units. Full article

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15 pages, 2557 KB

Open AccessArticle

Post-Implementation Evaluation of CIC Filters for Digital Audio Applications on FPGA

by Elisei Ilies, Magdalena Marinca and Aurel Gontean

J. Low Power Electron. Appl. 2026, 16(1), 5; https://doi.org/10.3390/jlpea16010005 - 26 Jan 2026

Abstract

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and [...] Read more.

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and one generated using an open-source CIC filter architecture. The study compares the efficiency of these three implementations in terms of slice LUTs and slice register usage. The maximum working frequency was also investigated. The results demonstrate that filters generated with the CIC Compiler require fewer FPGA resources, provide optimized multi-channel support, and have the option to utilize DSP48 slices for enhanced performance, while MATLAB-generated filters have higher working frequency and have great flexibility regarding the parameter, like the open-source CIC filter version. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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19 pages, 2028 KB

Open AccessArticle

RSSI-Based Localization of Smart Mattresses in Hospital Settings

by Yeh-Liang Hsu, Chun-Hung Yi, Shu-Chiung Lee and Kuei-Hua Yen

J. Low Power Electron. Appl. 2026, 16(1), 4; https://doi.org/10.3390/jlpea16010004 - 14 Jan 2026

Abstract

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability [...] Read more.

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability and reduce nursing workload. (2) Purpose: This study presents a pragmatic, large-scale implementation and validation of a BLE-based localization system using RSSI measurements. The goal was to achieve reliable room-level identification of smart mattresses by leveraging existing hospital infrastructure. (3) Results: The system showed stable signals in the complex hospital environment, with a 12.04 dBm mean gap between primary and secondary rooms, accurately detecting mattress movements and restoring location confidence. Nurses reported easier operation, reduced manual checks, and improved accuracy, though occasional mismatches occurred when receivers were offline. (4) Conclusions: The RSSI-based system demonstrates a feasible and scalable model for real-world asset tracking. Future upgrades include receiver health monitoring, watchdog restarts, and enhanced user training to improve reliability and usability. (5) Method: RSSI–distance relationships were characterized under different partition conditions to determine parameters for room differentiation. To evaluate real-world scalability, a field validation involving 266 mattresses in 101 rooms over 42 h tested performance, along with relocation tests and nurse feedback. Full article

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14 pages, 3045 KB

Open AccessArticle

Exploring Runtime Sparsification of YOLO Model Weights During Inference

by Tanzeel-ur-Rehman Khan, Sanghamitra Roy and Koushik Chakraborty

J. Low Power Electron. Appl. 2026, 16(1), 3; https://doi.org/10.3390/jlpea16010003 - 13 Jan 2026

Abstract

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present [...] Read more.

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present three sparsification approaches: Homogeneous, Progressive, and Layer-Adaptive, each methodically reducing the model’s complexity without compromising its detection capability. Additionally, we refine the model’s output with a memory-efficient sliding window approach and a Bounding Box Sorting Algorithm, ensuring precise Intersection over Union (IoU) calculations. Our results demonstrate a substantial reduction in computational load by zeroing out over 50% of the weights with only a minimal 6% loss in IoU and 0.6% loss in F1-Score. Full article

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23 pages, 2239 KB

Open AccessArticle

SparseDroop: Hardware–Software Co-Design for Mitigating Voltage Droop in DNN Accelerators

by Arnab Raha, Shamik Kundu, Arghadip Das, Soumendu Kumar Ghosh and Deepak A. Mathaikutty

J. Low Power Electron. Appl. 2026, 16(1), 2; https://doi.org/10.3390/jlpea16010002 - 23 Dec 2025

Abstract

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) [...] Read more.

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths

I C C

trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining

I C C_{m a x}

and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning. Full article

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14 pages, 1157 KB

Open AccessArticle

Hardware-Friendly and Efficient Vision Transformer for Deployment on Low-Power Embedded Device

by Ziyang Chen, Ming Hao, Xinye Cao, Jingwei Zhang, Chaoyao Shen, Guoqing Li and Meng Zhang

J. Low Power Electron. Appl. 2026, 16(1), 1; https://doi.org/10.3390/jlpea16010001 - 22 Dec 2025

Abstract

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained [...] Read more.

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained platforms. To address these challenges, this paper proposes a hardware-friendly CNN-Transformer hybrid pyramid architecture that effectively balances accuracy, efficiency, and deployability. The proposed model integrates convolutional bottlenecks with Transformer encoders to capture both local and global contextual information while maintaining low computational cost. A pyramid feature extraction structure is further introduced to enhance multi-scale semantic representation. To improve hardware efficiency, we redesign key nonlinear components by introducing hardware-friendly activation, normalization, and Softmax approximations. Specifically, GELU and LN are replaced by ReLU and Batch Normalization (BN), and a simplified logarithmic-exponential formulation termed Softmax2 is proposed, which eliminates complex exponential and division operations, significantly reducing hardware implementation cost. Extensive experiments demonstrate the effectiveness of the proposed framework. The experimental results validate that the proposed architecture offers a promising and practical solution for real-time and embedded vision applications. Full article

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13 pages, 3375 KB

Open AccessArticle

A Self-Contained Startup Charging Circuit for Energy-Harvesting Batteryless IoT Devices

by Michelle Libang, Kriz Kevin Adrivan, Jefferson A. Hora, Charade G. Avondo, Robert M. Comaling, Xi Zhu and Yichuang Sun

J. Low Power Electron. Appl. 2025, 15(4), 71; https://doi.org/10.3390/jlpea15040071 - 18 Dec 2025

Abstract

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the [...] Read more.

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C. Full article

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14 pages, 1586 KB

Open AccessArticle

Efficient Error Correction Coding for Physically Unclonable Functions

by Sreehari K. Narayanan, Ramesh Bhakthavatchalu and Remya Ajai Ajayan Sarala

J. Low Power Electron. Appl. 2025, 15(4), 70; https://doi.org/10.3390/jlpea15040070 - 12 Dec 2025

Abstract

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an [...] Read more.

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an efficient scheme that integrates a delay-base d PUF with a Low-Density Parity-Check (LDPC) code. Specifically, a feed-forward PUF is combined with LDPC coding to reliably regenerate the cryptographic key. Our design reproduces the key with minimal error using channel coding. The scheme achieves 96% key-generation reliability, representing a notable improvement over PUF-based key generation without error-correction coding. LDPC decoding with the min-sum algorithm provides better error correction than the bit-flipping algorithm, but it is more computationally intensive. We could design the proposed scheme with minimum hardware resource utilization using Xilinx Vivado 2018.2 and Cadence Genus tools. Full article

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25 pages, 1878 KB

Open AccessArticle

Slope Compensation and Bifurcation in a DC-DC, Single-Input, Multiple-Output, CMOS Integrated Converter Under Current-Mode and Comparator-Based Hybrid Control

by Mathieu Ginet, Eric Feltrin, Nicolas Jeanniot, Bruno Allard and Xuefang Lin-Shi

J. Low Power Electron. Appl. 2025, 15(4), 69; https://doi.org/10.3390/jlpea15040069 - 12 Dec 2025

Abstract

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a [...] Read more.

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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