Journal of Low Power Electronics and Applications

35 pages, 9979 KB

Open AccessReview

Applications of MXenes in Neuromorphic Computing and Memristors: From Material Synthesis and Physical Mechanisms to Integrated Sensing, Memory, and Computation

by Yifeng Fu and Jianguang Xu

J. Low Power Electron. Appl. 2026, 16(1), 8; https://doi.org/10.3390/jlpea16010008 - 25 Feb 2026

Abstract

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. [...] Read more.

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti₃C₂T_x) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation. Full article

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17 pages, 4778 KB

Open AccessArticle

A Low-Power LoRa-Based Multi-Nodal Wireless Sensor Network with Custom Communication Framework for Rockfall Monitoring

by Paolo Esposito, Vincenzo Stornelli and Giuseppe Ferri

J. Low Power Electron. Appl. 2026, 16(1), 7; https://doi.org/10.3390/jlpea16010007 - 17 Feb 2026

Abstract

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in [...] Read more.

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in both the node-gateway side and the gateway-user interface side. In particular, the communication framework is entirely IoT-based, featuring both the MQTT protocol, for the direct control of apparatuses from the system user interface, and the more traditional TCP/IP protocol, implemented on NB-IoT. The proposed system is entirely solar-powered and features a 34.68 mWh/day consumption. Around a single communication session, the average power consumption inside the single node amounts to 1.4 mW. This paper gives an overview of the proposed system, with detailed explanations of each part, and measurements retrieved over a wide period to assess the functionality of the system. Full article

(This article belongs to the Topic Application of IOT on Manufacturing, Communication and Engineering, 2nd Volume)

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29 pages, 3191 KB

Open AccessArticle

A Q-Learning-Based Hierarchical Power Delivery Architecture for the Efficient Management of Heterogeneous Loads

by Andreas Tsiougkos, Georgia Amanatiadou and Vasilis F. Pavlidis

J. Low Power Electron. Appl. 2026, 16(1), 6; https://doi.org/10.3390/jlpea16010006 - 28 Jan 2026

Abstract

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), [...] Read more.

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units. Full article

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15 pages, 2557 KB

Open AccessArticle

Post-Implementation Evaluation of CIC Filters for Digital Audio Applications on FPGA

by Elisei Ilies, Magdalena Marinca and Aurel Gontean

J. Low Power Electron. Appl. 2026, 16(1), 5; https://doi.org/10.3390/jlpea16010005 - 26 Jan 2026

Abstract

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and [...] Read more.

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and one generated using an open-source CIC filter architecture. The study compares the efficiency of these three implementations in terms of slice LUTs and slice register usage. The maximum working frequency was also investigated. The results demonstrate that filters generated with the CIC Compiler require fewer FPGA resources, provide optimized multi-channel support, and have the option to utilize DSP48 slices for enhanced performance, while MATLAB-generated filters have higher working frequency and have great flexibility regarding the parameter, like the open-source CIC filter version. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (3rd Edition))

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19 pages, 2028 KB

Open AccessArticle

RSSI-Based Localization of Smart Mattresses in Hospital Settings

by Yeh-Liang Hsu, Chun-Hung Yi, Shu-Chiung Lee and Kuei-Hua Yen

J. Low Power Electron. Appl. 2026, 16(1), 4; https://doi.org/10.3390/jlpea16010004 - 14 Jan 2026

Abstract

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability [...] Read more.

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability and reduce nursing workload. (2) Purpose: This study presents a pragmatic, large-scale implementation and validation of a BLE-based localization system using RSSI measurements. The goal was to achieve reliable room-level identification of smart mattresses by leveraging existing hospital infrastructure. (3) Results: The system showed stable signals in the complex hospital environment, with a 12.04 dBm mean gap between primary and secondary rooms, accurately detecting mattress movements and restoring location confidence. Nurses reported easier operation, reduced manual checks, and improved accuracy, though occasional mismatches occurred when receivers were offline. (4) Conclusions: The RSSI-based system demonstrates a feasible and scalable model for real-world asset tracking. Future upgrades include receiver health monitoring, watchdog restarts, and enhanced user training to improve reliability and usability. (5) Method: RSSI–distance relationships were characterized under different partition conditions to determine parameters for room differentiation. To evaluate real-world scalability, a field validation involving 266 mattresses in 101 rooms over 42 h tested performance, along with relocation tests and nurse feedback. Full article

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14 pages, 3045 KB

Open AccessArticle

Exploring Runtime Sparsification of YOLO Model Weights During Inference

by Tanzeel-ur-Rehman Khan, Sanghamitra Roy and Koushik Chakraborty

J. Low Power Electron. Appl. 2026, 16(1), 3; https://doi.org/10.3390/jlpea16010003 - 13 Jan 2026

Abstract

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present [...] Read more.

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present three sparsification approaches: Homogeneous, Progressive, and Layer-Adaptive, each methodically reducing the model’s complexity without compromising its detection capability. Additionally, we refine the model’s output with a memory-efficient sliding window approach and a Bounding Box Sorting Algorithm, ensuring precise Intersection over Union (IoU) calculations. Our results demonstrate a substantial reduction in computational load by zeroing out over 50% of the weights with only a minimal 6% loss in IoU and 0.6% loss in F1-Score. Full article

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23 pages, 2239 KB

Open AccessArticle

SparseDroop: Hardware–Software Co-Design for Mitigating Voltage Droop in DNN Accelerators

by Arnab Raha, Shamik Kundu, Arghadip Das, Soumendu Kumar Ghosh and Deepak A. Mathaikutty

J. Low Power Electron. Appl. 2026, 16(1), 2; https://doi.org/10.3390/jlpea16010002 - 23 Dec 2025

Abstract

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) [...] Read more.

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths

I C C

trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining

I C C_{m a x}

and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning. Full article

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14 pages, 1157 KB

Open AccessArticle

Hardware-Friendly and Efficient Vision Transformer for Deployment on Low-Power Embedded Device

by Ziyang Chen, Ming Hao, Xinye Cao, Jingwei Zhang, Chaoyao Shen, Guoqing Li and Meng Zhang

J. Low Power Electron. Appl. 2026, 16(1), 1; https://doi.org/10.3390/jlpea16010001 - 22 Dec 2025

Abstract

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained [...] Read more.

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained platforms. To address these challenges, this paper proposes a hardware-friendly CNN-Transformer hybrid pyramid architecture that effectively balances accuracy, efficiency, and deployability. The proposed model integrates convolutional bottlenecks with Transformer encoders to capture both local and global contextual information while maintaining low computational cost. A pyramid feature extraction structure is further introduced to enhance multi-scale semantic representation. To improve hardware efficiency, we redesign key nonlinear components by introducing hardware-friendly activation, normalization, and Softmax approximations. Specifically, GELU and LN are replaced by ReLU and Batch Normalization (BN), and a simplified logarithmic-exponential formulation termed Softmax2 is proposed, which eliminates complex exponential and division operations, significantly reducing hardware implementation cost. Extensive experiments demonstrate the effectiveness of the proposed framework. The experimental results validate that the proposed architecture offers a promising and practical solution for real-time and embedded vision applications. Full article

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13 pages, 3375 KB

Open AccessArticle

A Self-Contained Startup Charging Circuit for Energy-Harvesting Batteryless IoT Devices

by Michelle Libang, Kriz Kevin Adrivan, Jefferson A. Hora, Charade G. Avondo, Robert M. Comaling, Xi Zhu and Yichuang Sun

J. Low Power Electron. Appl. 2025, 15(4), 71; https://doi.org/10.3390/jlpea15040071 - 18 Dec 2025

Abstract

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the [...] Read more.

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C. Full article

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14 pages, 1586 KB

Open AccessArticle

Efficient Error Correction Coding for Physically Unclonable Functions

by Sreehari K. Narayanan, Ramesh Bhakthavatchalu and Remya Ajai Ajayan Sarala

J. Low Power Electron. Appl. 2025, 15(4), 70; https://doi.org/10.3390/jlpea15040070 - 12 Dec 2025

Abstract

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an [...] Read more.

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an efficient scheme that integrates a delay-base d PUF with a Low-Density Parity-Check (LDPC) code. Specifically, a feed-forward PUF is combined with LDPC coding to reliably regenerate the cryptographic key. Our design reproduces the key with minimal error using channel coding. The scheme achieves 96% key-generation reliability, representing a notable improvement over PUF-based key generation without error-correction coding. LDPC decoding with the min-sum algorithm provides better error correction than the bit-flipping algorithm, but it is more computationally intensive. We could design the proposed scheme with minimum hardware resource utilization using Xilinx Vivado 2018.2 and Cadence Genus tools. Full article

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25 pages, 1878 KB

Open AccessArticle

Slope Compensation and Bifurcation in a DC-DC, Single-Input, Multiple-Output, CMOS Integrated Converter Under Current-Mode and Comparator-Based Hybrid Control

by Mathieu Ginet, Eric Feltrin, Nicolas Jeanniot, Bruno Allard and Xuefang Lin-Shi

J. Low Power Electron. Appl. 2025, 15(4), 69; https://doi.org/10.3390/jlpea15040069 - 12 Dec 2025

Abstract

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a [...] Read more.

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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18 pages, 3817 KB

Open AccessArticle

Analysis of Core Temperature Dynamics in Multi-Core Processors

by Leena Ladge and Y. Srinivasa Rao

J. Low Power Electron. Appl. 2025, 15(4), 68; https://doi.org/10.3390/jlpea15040068 - 2 Dec 2025

Abstract

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by [...] Read more.

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency. Full article

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15 pages, 3792 KB

Open AccessArticle

A Dynamic Current Pulsing Technique to Improve the Noise Efficiency Factor of Neural Recording Amplifiers

by Yujia Huo and Roy H. Olsson III

J. Low Power Electron. Appl. 2025, 15(4), 67; https://doi.org/10.3390/jlpea15040067 - 1 Dec 2025

Abstract

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor [...] Read more.

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor (NEF) beyond that achievable using traditional design. A low NEF of 1.55 is achieved at an average power consumption of 587.8 nW and 5.18 µVrms noise, integrated from 0.1 to 9.8 kHz, inclusive of the impacts of sampling and aliasing. The NEF is improved from 1.76 in the static low current state (LCS) and 1.67 in the static high current state (HCS), measured on the same amplifier chip. Full article

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29 pages, 3796 KB

Open AccessReview

Research on the Security of SRAM-Based FPGAs in the Era of Artificial Intelligence

by Jing Zhou, Xiangyu Zhao, Shengbing Zhang, Lei Chen, Ke Xiao and Shuo Wang

J. Low Power Electron. Appl. 2025, 15(4), 66; https://doi.org/10.3390/jlpea15040066 - 28 Nov 2025

Abstract

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics [...] Read more.

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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17 pages, 6041 KB

Open AccessArticle

An Ultra-Low-Quiescent-Current On-Chip Energy Management Circuit in 65 nm CMOS for Energy Harvesting Applications

by Mehdi Shahabi, Noemi Perez, Hector Solar and Andoni Beriain

J. Low Power Electron. Appl. 2025, 15(4), 65; https://doi.org/10.3390/jlpea15040065 - 13 Nov 2025

Abstract

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems [...] Read more.

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems operating under strict energy limitations. The design relies on a compact latch-based core and avoids the need for extra circuits such as voltage references, comparators, or logic blocks, which helps reduce both area and power. To implement the required high resistance, a series of diode-connected zero-threshold NMOS transistors is used. This approach enables very high resistance in a compact area without additional power consumption or biasing issues at low voltages. A PMOS transistor is also integrated at the EM output to directly control different types of loads. The circuit was designed and fabricated using a 65 nm CMOS standard process. Experimental measurements from the fabricated chips show a quiescent current of 170 nA at 3 V and a voltage hysteresis of over 0.9 V. In addition, temperature and process variation were simulated to verify robust operation. These results confirm that the circuit operates reliably under ultra-low-power conditions and is well-suited for EH systems. Full article

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34 pages, 3920 KB

Open AccessArticle

Towards Memory-Efficient and High-Performance Branch Prediction: The LXOR Architecture for Control Flow Optimization in Embedded and General-Purpose RISC-V Processors

by Devendra G. Sutar and Nitesh B. Guinde

J. Low Power Electron. Appl. 2025, 15(4), 64; https://doi.org/10.3390/jlpea15040064 - 24 Oct 2025

Abstract

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, [...] Read more.

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, PAg, PAp, Gshare, Gselect) that rely on large Pattern History Tables (PHTs) or intricate global/local history combinations, the LXOR predictor employs complemented local history and XOR-based indexing, optimizing table access and reducing aliasing. Implemented and evaluated using the MARSS-RISCV simulator on a 64-bit in-order RISC-V core, the LXOR’s performance was compared against traditional predictors using Coremark and SPEC CPU2017 benchmarks. The LXOR consistently achieved competitive results, with a prediction accuracy of up to 83.92%, lower misprediction rates, and instruction flushes as low as 5.83%. It also attained an IPC rate of up to 0.83, all while maintaining a compact memory footprint of approximately 2 KB, significantly smaller than current alternatives. These findings demonstrate that the LXOR predictor not only matches the performance of more complex predictors but does so with less memory and logic overhead, making it ideal for embedded systems, low-power RISC-V processors, and resource-constrained IoT and edge devices. By balancing prediction accuracy with simplicity, the LXOR offers a scalable and cost-effective solution for next-generation microprocessors. Full article

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16 pages, 955 KB

Open AccessArticle

A Multiplierless Architecture for Image Convolution in Memory

by John Reuben, Felix Zeller, Benjamin Seiler and Dietmar Fey

J. Low Power Electron. Appl. 2025, 15(4), 63; https://doi.org/10.3390/jlpea15040063 - 23 Oct 2025

Abstract

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring [...] Read more.

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring

{(n - (k - 1))}^{2}

Inner Product (IP) computations for convolution of a

n \times n

image with a

k \times k

kernel. For example, for a convolution of a 224 × 224 image with a 3 × 3 kernel, 49,284 IPs need to be computed, where each IP requires nine multiplications and eight additions. This is a major hurdle for in-memory implementation because in-memory adders and multipliers are extremely slow compared to CMOS multipliers. In this work, we revive an old technique called ‘Distributed Arithmetic’ and judiciously apply it to perform image convolution in memory without area-intensive hard-wired multipliers. Distributed arithmetic performs multiplication using shift-and-add operations, and they are implemented using CMOS circuits in the periphery of ReRAM memory. Compared to Google’s TPU, our in-memory architecture requires 56× less energy while incurring 24× more latency for convolution of a 224 × 224 image with a 3 × 3 filter. Full article

(This article belongs to the Special Issue Energy Consumption Management in Electronic Systems)

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19 pages, 9685 KB

Open AccessArticle

Dynamics of a Neuromorphic Circuit Incorporating a Second-Order Locally Active Memristor and Its Parameter Estimation

by Shivakumar Rajagopal, Viet-Thanh Pham, Fatemeh Parastesh, Karthikeyan Rajagopal and Sajad Jafari

J. Low Power Electron. Appl. 2025, 15(4), 62; https://doi.org/10.3390/jlpea15040062 - 13 Oct 2025

Cited by 1

Abstract

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors [...] Read more.

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors (LAMs), with their ability to amplify small perturbations within a locally active domain to generate action potential-like responses, provide powerful building blocks for neuromorphic circuits and offer new perspectives on the mechanisms underlying neuronal firing dynamics. This paper introduces a novel second-order locally active memristor (LAM) governed by two coupled state variables, enabling richer nonlinear dynamics compared to conventional first-order devices. Even when the capacitances controlling the states are equal, the device retains two independent memory states, which broaden the design space for hysteresis tuning and allow flexible modulation of the current–voltage response. The second-order LAM is then integrated into a FitzHugh–Nagumo neuron circuit. The proposed circuit exhibits oscillatory firing behavior under specific parameter regimes and is further investigated under both DC and AC external stimulation. A comprehensive analysis of its equilibrium points is provided, followed by bifurcation diagrams and Lyapunov exponent spectra for key system parameters, revealing distinct regions of periodic, chaotic, and quasi-periodic dynamics. Representative time-domain patterns corresponding to these regimes are also presented, highlighting the circuit’s ability to reproduce a rich variety of neuronal firing behaviors. Finally, two unknown system parameters are estimated using the Aquila Optimization algorithm, with a cost function based on the system’s return map. Simulation results confirm the algorithm’s efficiency in parameter estimation. Full article

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15 pages, 1662 KB

Open AccessArticle

Adaptive Hybrid Switched-Capacitor Cell Balancing for 4-Cell Li-Ion Battery Pack with a Study of Pulse-Frequency Modulation Control

by Wu Cong Lim, Liter Siek and Eng Leong Tan

J. Low Power Electron. Appl. 2025, 15(4), 61; https://doi.org/10.3390/jlpea15040061 - 1 Oct 2025

Abstract

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor [...] Read more.

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers. Full article

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Journal of Low Power Electronics and Applications

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