Journal of Low Power Electronics and Applications

20 pages, 2588 KiB

Open AccessArticle

A 10 V-to-1 V Double Step-Down Buck Converter Using Time-Based Current Mode Control with Minimum Delay Frequency Difference Phase Adder for 1 MHz Operation

by Chong Boon Tan and Liter Siek

J. Low Power Electron. Appl. 2024, 14(4), 58; https://doi.org/10.3390/jlpea14040058 - 6 Dec 2024

Abstract

An extreme step-down ratio buck converter is proposed using a double step-down (DSD) buck converter architecture and a single time-based current mode PWM controller able to generate two non-overlapping control signal phases. Current sampling for two inductors is implemented with a multiplexer and [...] Read more.

An extreme step-down ratio buck converter is proposed using a double step-down (DSD) buck converter architecture and a single time-based current mode PWM controller able to generate two non-overlapping control signal phases. Current sampling for two inductors is implemented with a multiplexer and a pair of VCOs only, which treats the two inductors as one inductor operating at double the frequency. This is achieved without the use of any large external passive components in the controller while remaining stable. The type-II time-based controller uses a VCO, a frequency difference phase adder (FDPA), and a phase detector, generating a control signal with fully integrated components with minimum area. FDPA for proportional control also significantly limits the signal delay of the high gain controller, allowing the use of time-based control technique at <10 MHz, which improves converter efficiency. The proposed time-based current mode controller DSD buck converter is simulated in 130 nm BCD technology operating at 1 MHz for 10 V to 1 V conversion. The simulated peak efficiency is 82.2% at 0.4 A, and recovers from a 1.8 A loading and unloading current step in 5.75

μ

s and 9.9

μ

s, respectively. Full article

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25 pages, 4692 KiB

Open AccessArticle

Reinforcement-Learning-Based Synthesis of Custom Approximate Parallel Prefix Adders

by Apostolos Stefanidis and Giorgos Dimitrakopoulos

J. Low Power Electron. Appl. 2024, 14(4), 57; https://doi.org/10.3390/jlpea14040057 - 6 Dec 2024

Abstract

Approximate hardware units compute a sufficiently accurate result rather than a fully accurate one using fewer transistors or equivalently logic gates than their accurate counterparts. This approach significantly saves energy while maintaining acceptable application-level quality. In this work, we focus on synthesizing custom [...] Read more.

Approximate hardware units compute a sufficiently accurate result rather than a fully accurate one using fewer transistors or equivalently logic gates than their accurate counterparts. This approach significantly saves energy while maintaining acceptable application-level quality. In this work, we focus on synthesizing custom approximate parallel prefix adders tailored to specific applications. The introduced reinforcement learning (RL) framework co-optimizes application performance and hardware complexity. An RL agent learns approximate addition strategies by exploring the entire design space and receiving feedback from hardware synthesis and application performance. Experimental results demonstrate that the synthesized adders can reduce area and power consumption by 12% and 10%, respectively, on average without compromising the error behavior of the application, or can significantly improve the application’s error metrics without degrading area and power consumption for a variety of practical applications. Full article

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26 pages, 4003 KiB

Open AccessArticle

Advanced Modelling and Performance Analysis of a Separately Excited Direct-Current Motor Powered by Photovoltaic Generators Using Maximum Power Point Tracking Techniques

by Feras Alasali, Tha’er O. Sweidan, Mohammed I. Abuashour and William Holderbaum

J. Low Power Electron. Appl. 2024, 14(4), 56; https://doi.org/10.3390/jlpea14040056 - 28 Nov 2024

Abstract

The integration of photovoltaic (PV) systems into DC motor drives has prompted the enhancement of motor performance. This study explores the application of photovoltaic generators (PVs) to independently power and excite a Separately Excited Direct-Current (SEDC) system by utilizing a proportional open-circuit voltage [...] Read more.

The integration of photovoltaic (PV) systems into DC motor drives has prompted the enhancement of motor performance. This study explores the application of photovoltaic generators (PVs) to independently power and excite a Separately Excited Direct-Current (SEDC) system by utilizing a proportional open-circuit voltage method as a strategy for tracking the maximum power point. This approach offers an effective means of optimizing energy output from PV systems. The primary aim was to optimize power output from photovoltaic generators across varying solar intensity levels. This paper describes the nonlinear current/voltage behaviour of PV generators under different levels of irradiation, along with the magnetic characteristics of the core material in an SEDC motor, utilizing advanced polynomial equations for accurate mathematical representation. Furthermore, we conducted a dynamic analysis of the SEDC motor, powered by the PV generators, under varying solar intensities. This study investigates the operational performance of the SEDC motor under varying solar irradiance levels by developing a realistic model using MATLAB software, R2022a, for numerical simulations, followed by implementation on high-performance computing platforms, including a real-time simulator and testbed, using a real-time digital simulator (RTDS). Full article

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19 pages, 6402 KiB

Open AccessReview

Key Role of Cold-Start Circuits in Low-Power Energy Harvesting Systems: A Research Review

by Xiao Shi, Mengye Cai and Yanfeng Jiang

J. Low Power Electron. Appl. 2024, 14(4), 55; https://doi.org/10.3390/jlpea14040055 - 22 Nov 2024

Abstract

The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, [...] Read more.

The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, sound, friction, and pressure, a specific low-power energy harvesting system is required. Due to the absence of an external power supply in such systems, cold-start circuits play a crucial role in igniting the low-power energy harvesting system, ensuring a reliable start-up from the initial state. This paper reviews the categorization and characteristics of energy harvesting systems, with a focus on the design and performance parameters of cold-start circuits. A tabular comparison of existing cold-start strategies is presented herein. The study demonstrates that resonance-based integrated cold-start methods offer significant advantages in terms of conversion efficiency and dynamic range, while ring oscillator-based integrated cold-start methods achieve the lowest start-up voltage. Additionally, the paper discusses the challenges of self-starting and future research directions, highlighting the potential role of emerging technologies, such as artificial intelligence (AI) and neural networks, in optimizing the design of energy harvesting systems. Full article

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23 pages, 8197 KiB

Open AccessArticle

Multi-Timescale Energy Consumption Management in Smart Buildings Using Hybrid Deep Artificial Neural Networks

by Favour Ibude, Abayomi Otebolaku, Jude E. Ameh and Augustine Ikpehai

J. Low Power Electron. Appl. 2024, 14(4), 54; https://doi.org/10.3390/jlpea14040054 - 7 Nov 2024

Abstract

Demand side management is a critical issue in the energy sector. Recent events such as the global energy crisis, costs, the necessity to reduce greenhouse emissions, and extreme weather conditions have increased the need for energy efficiency. Thus, accurately predicting energy consumption is [...] Read more.

Demand side management is a critical issue in the energy sector. Recent events such as the global energy crisis, costs, the necessity to reduce greenhouse emissions, and extreme weather conditions have increased the need for energy efficiency. Thus, accurately predicting energy consumption is one of the key steps in addressing inefficiency in energy consumption and its optimization. In this regard, accurate predictions on a daily, hourly, and minute-by-minute basis would not only minimize wastage but would also help to save costs. In this article, we propose intelligent models using ensembles of convolutional neural network (CNN), long-short-term memory (LSTM), bi-directional LSTM and gated recurrent units (GRUs) neural network models for daily, hourly, and minute-by-minute predictions of energy consumptions in smart buildings. The proposed models outperform state-of-the-art deep neural network models for predicting minute-by-minute energy consumption, with a mean square error of 0.109. The evaluated hybrid models also capture more latent trends in the data than traditional single models. The results highlight the potential of using hybrid deep learning models for improved energy efficiency management in smart buildings. Full article

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16 pages, 3143 KiB

Open AccessArticle

A Low-Power 5-Bit Two-Step Flash Analog-to-Digital Converter with Double-Tail Dynamic Comparator in 90 nm Digital CMOS

by Reena George and Nagesh Ch

J. Low Power Electron. Appl. 2024, 14(4), 53; https://doi.org/10.3390/jlpea14040053 - 4 Nov 2024

Abstract

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control [...] Read more.

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (

V_{k}

). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178

μ

W for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works. Full article

(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)

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18 pages, 11691 KiB

Open AccessArticle

Characterization of the Power Distribution Network for Commercialized STM32s Using a Resonance Frequency Measurement Method

by Marie Peyrard, Gilles Jacquemod and Nicolas Froidevaux

J. Low Power Electron. Appl. 2024, 14(4), 52; https://doi.org/10.3390/jlpea14040052 - 1 Nov 2024

Abstract

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints [...] Read more.

Power integrity is a critical aspect of microcontroller (MCU) system design. The present tendency of increasing current density and operating frequency, along with decreasing operating voltage, significantly diminishes voltage margins. Given the cost efficiency required for MCU systems, this context places important constraints on the design of the power distribution network (PDN), which directly impacts power supply noise. Therefore, characterizing the PDN is necessary. This paper introduces a cost-effective measurement and modeling method to estimate the die-package resonance frequency of the PDN, a major threat to power integrity. The method, applied to two 32-bit MCUs from STMicroelectronics with varying PDN configurations, enables the identification of the die-package resonance frequency. The results lead to the refinement of the die capacitance model for both cases, with a maximum relative error of less than 7%. The final objective is to implement the measurement system in the die in order to adjust the PDN if necessary. Full article

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11 pages, 3506 KiB

Open AccessArticle

Multichannel Sensor Array Design for Minimizing Detector Complexity and Power Consumption in Ionoacoustic Proton Beam Tomography

by Elia Arturo Vallicelli, Alessandro Michele Ferrara, Maurizio Marrale, Mattia Tambaro and Marcello De Matteis

J. Low Power Electron. Appl. 2024, 14(4), 51; https://doi.org/10.3390/jlpea14040051 - 30 Oct 2024

Abstract

Ionoacoustic tomography exploits the acoustic signal generated by the fast energy deposition along the path of pulsed particle beams to reconstruct with sub-mm precision the dose deposition, with promising envisioned applications in hadron therapy treatment monitoring. State-of-the-art ionoacoustic detectors mainly rely on single-channel [...] Read more.

Ionoacoustic tomography exploits the acoustic signal generated by the fast energy deposition along the path of pulsed particle beams to reconstruct with sub-mm precision the dose deposition, with promising envisioned applications in hadron therapy treatment monitoring. State-of-the-art ionoacoustic detectors mainly rely on single-channel sensors and time-of-flight measurements to provide 1D localization of the maximum dose deposition at the so-called Bragg peak. This work investigates the design challenges of multichannel sensors for ionoacoustic tomography in terms of their ability to accurately reconstruct the dose deposition of a 200 MeV clinical proton beam, highlighting the impact of the number of channels in the array and their directivity. A complete acoustic model of the sensors and environment has been developed and used to find an optimum tradeoff between accuracy, evaluated numerically through the gamma index, and hardware complexity due to higher channel numbers, thus minimizing the system-level power consumption of the detector. Full article

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12 pages, 3403 KiB

Open AccessArticle

Phase Change Memory Drift Compensation in Spiking Neural Networks Using a Non-Linear Current Scaling Strategy

by Joao Henrique Quintino Palhares, Nikhil Garg, Yann Beilliard, Lorena Anghel, Fabien Alibart, Dominique Drouin and Philippe Galy

J. Low Power Electron. Appl. 2024, 14(4), 50; https://doi.org/10.3390/jlpea14040050 - 22 Oct 2024

Abstract

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase [...] Read more.

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

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18 pages, 2349 KiB

Open AccessArticle

A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification

by Shuhan Liu, Suhao Chen, Wei Gao, Jiabin Zhang, Dacheng Xu, Fang Chen, Zhenghao Lu and Xiaopeng Yu

J. Low Power Electron. Appl. 2024, 14(4), 49; https://doi.org/10.3390/jlpea14040049 - 8 Oct 2024

Abstract

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a [...] Read more.

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm², and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234

μ

W, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester. Full article

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10 pages, 4646 KiB

Open AccessArticle

Energy Restoration in Data Drivers for Low-Power Digitally Driven OLEDoS Microdisplays

by Sheida Gohardehi and Manoj Sachdev

J. Low Power Electron. Appl. 2024, 14(4), 48; https://doi.org/10.3390/jlpea14040048 - 4 Oct 2024

Abstract

Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic [...] Read more.

Microdisplays are widely used in near-to-eye (NTE) applications that operate with batteries, and reducing the power consumption of microdisplays is key to increasing their battery life. This paper proposes a digital data driver with a data energy recycling feature to reduce its dynamic power consumption. According to the measurement results obtained from a proof-of-concept array fabricated using TSMC 65 nm technology, the power consumption of the display data driver demonstrates an average reduction of 16% when tested with 10 random black-and-white images or a 14.4% decrease when evaluated using four real-life test images. Full article

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17 pages, 5175 KiB

Open AccessArticle

Reliability Enhancement Methods for Relaxation Oscillator with Delay Time Cancellation

by Kunpeng Xu, Hongguang Dai, Zhanxia Wu, Zhibo Huang, Guoqiang Zhang, Xiaopeng Yu, Wechang Wang and Gang Xuan

J. Low Power Electron. Appl. 2024, 14(4), 47; https://doi.org/10.3390/jlpea14040047 - 26 Sep 2024

Abstract

Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the [...] Read more.

Relaxation oscillators are preferred in low-frequency applications due to their lower power consumption and superior temperature stability. However, frequency errors arise from variations in the comparator’s offset voltage and delay time due to PVT changes. To address these issues, this paper proposes the low-power delay time cancellation (DTC) technique and several enhancement methods, including a novel offset trimming approach, an error state detection and recovery (ESDAR) circuit, and a specialized frequency-trimming method. Simulation results for an 8 MHz relaxation oscillator in a 40 nm CMOS process show that the proposed DTC technique and enhancements improve frequency variation due to power supply fluctuations to ±0.05% and reduce temperature-induced frequency variation to ±0.4%. Full article

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17 pages, 4715 KiB

Open AccessArticle

IoT-MFaceNet: Internet-of-Things-Based Face Recognition Using MobileNetV2 and FaceNet Deep-Learning Implementations on a Raspberry Pi-400

by Ahmad Saeed Mohammad, Thoalfeqar G. Jarullah, Musab T. S. Al-Kaltakchi, Jabir Alshehabi Al-Ani and Somdip Dey

J. Low Power Electron. Appl. 2024, 14(3), 46; https://doi.org/10.3390/jlpea14030046 - 5 Sep 2024

Abstract

IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based [...] Read more.

IoT applications revolutionize industries by enhancing operations, enabling data-driven decisions, and fostering innovation. This study explores the growing potential of IoT-based facial recognition for mobile devices, a technology rapidly advancing within the interconnected IoT landscape. The investigation proposes a framework called IoT-MFaceNet (Internet-of-Things-based face recognition using MobileNetV2 and FaceNet deep-learning) utilizing pre-existing deep-learning methods, employing the MobileNetV2 and FaceNet algorithms on both ImageNet and FaceNet databases. Additionally, an in-house database is compiled, capturing data from 50 individuals via a web camera and 10 subjects through a smartphone camera. Pre-processing of the in-house database involves face detection using OpenCV’s Haar Cascade, Dlib’s CNN Face Detector, and Mediapipe’s Face. The resulting system demonstrates high accuracy in real-time and operates efficiently on low-powered devices like the Raspberry Pi 400. The evaluation involves the use of the multilayer perceptron (MLP) and support vector machine (SVM) classifiers. The system primarily functions as a closed set identification system within a computer engineering department at the College of Engineering, Mustansiriyah University, Iraq, allowing access exclusively to department staff for the department rapporteur room. The proposed system undergoes successful testing, achieving a maximum accuracy rate of 99.976%. Full article

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12 pages, 3997 KiB

Open AccessArticle

Split-Voltage Configuration Improves Integrated Amplifier Power-Efficiency

by Sebastian Simmich and Robert Rieger

J. Low Power Electron. Appl. 2024, 14(3), 45; https://doi.org/10.3390/jlpea14030045 - 4 Sep 2024

Abstract

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V [...] Read more.

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. Full article

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16 pages, 667 KiB

Open AccessArticle

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

by Baudouin Chauviere and Kenneth S. Stevens

J. Low Power Electron. Appl. 2024, 14(3), 44; https://doi.org/10.3390/jlpea14030044 - 27 Aug 2024

Abstract

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the [...] Read more.

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing. Full article

(This article belongs to the Special Issue Energy Aware Scientific Computing in Distributed Architectures, Low Power Processors and HPC Hybrid Systems)

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27 pages, 6837 KiB

Open AccessReview

Prospective Review of Magneto-Resistive Current Sensors with High Sensitivity and Wide Temperature Range

by Zicai Yang and Yanfeng Jiang

J. Low Power Electron. Appl. 2024, 14(3), 43; https://doi.org/10.3390/jlpea14030043 - 19 Aug 2024

Abstract

Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research [...] Read more.

Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research process of the current sensors in industrial-level applications. In the review, starting with the development status of the current sensors, the physical mechanisms of the relevant magneto-resistive effects and their early applications as the current sensors are introduced. Several design methods of the magnetic sensors, as well as their merits and shortcomings, are summarized. The performance parameters of the magnetic sensors based on AMR, GMR, TMR and Hall effects are reviewed, including the front-end amplification circuits and conditioning circuits. The industrial applications of the current sensors in the fields of automobiles and photovoltaic inverters are enumerated. The criterions for the current sensors to be used in different scenarios are discussed. In the future, it is imperative to continue the research and development of novel current sensors in order to satisfy the increasingly stringent demands of the industrial developments, in terms of the performance, cost and reliability of the current sensors. Full article

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19 pages, 6482 KiB

Open AccessArticle

Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation

by Martin Valtierra-Rodriguez, Jose-Luis Contreras-Hernandez, David Granados-Lieberman, Jesus Rooney Rivera-Guillen, Juan Pablo Amezquita-Sanchez and David Camarena-Martinez

J. Low Power Electron. Appl. 2024, 14(3), 42; https://doi.org/10.3390/jlpea14030042 - 7 Aug 2024

Abstract

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern [...] Read more.

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip’s resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10⁻³ when compared with results from floating-point processors, highlighting its accuracy. Full article

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15 pages, 4565 KiB

Open AccessArticle

A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses

by Benjamin Villegas and Ioannis Vourkas

J. Low Power Electron. Appl. 2024, 14(3), 41; https://doi.org/10.3390/jlpea14030041 - 5 Aug 2024

Abstract

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a [...] Read more.

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells. Full article

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17 pages, 6867 KiB

Open AccessArticle

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

by Ali Namdari, Orazio Aiello and Daniele D. Caviglia

J. Low Power Electron. Appl. 2024, 14(3), 40; https://doi.org/10.3390/jlpea14030040 - 4 Aug 2024

Abstract

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in [...] Read more.

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)

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