Journal of Low Power Electronics and Applications

12 pages, 2371 KiB

Open AccessCommunication

A 0.8 V Low-Power Wide-Tuning-Range CMOS VCO for 802.11ac and IoT C-Band Applications

by Jung-Jen Hsu, Yao-Chian Lin and Stephen J. H. Yang

J. Low Power Electron. Appl. 2025, 15(2), 32; https://doi.org/10.3390/jlpea15020032 - 16 May 2025

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 [...] Read more.

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices. Full article

► Show Figures

Figure 1

17 pages, 869 KiB

Open AccessArticle

Impact of Mother Wavelet Choice on Fast Wavelet Transform Performances for Integrated ST Segment Monitoring

by Béatrice Guénégo, Caroline Lelandais-Perrault, Emilie Avignon-Meseldzija, Gérard Sou and Philippe Bénabès

J. Low Power Electron. Appl. 2025, 15(2), 31; https://doi.org/10.3390/jlpea15020031 - 12 May 2025

Abstract

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for [...] Read more.

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of

1.18

mm² and a post-layout power consumption of

4.89

μ

W, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of

6.9

dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

► Show Figures

Figure 1

14 pages, 9820 KiB

Open AccessArticle

Design and Analysis of an Ultra-Wideband High-Precision Active Phase Shifter in 0.18 μm SiGe BiCMOS Technology

by Hao Jiang, Zenglong Zhao, Nengxu Zhu and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 30; https://doi.org/10.3390/jlpea15020030 - 7 May 2025

Abstract

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the [...] Read more.

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

► Show Figures

Figure 1

14 pages, 16692 KiB

Open AccessArticle

A New Type of DC-DC Buck Converter with Soft Start Function and Reduced Voltage Stress

by Xin Wang, Zishuo Li, Zhen Lin and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 29; https://doi.org/10.3390/jlpea15020029 - 7 May 2025

Abstract

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, [...] Read more.

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion. Full article

(This article belongs to the Topic Application of Innovative Power Electronic Technologies, 2nd Edition)

► Show Figures

Figure 1

14 pages, 3868 KiB

Open AccessArticle

Analytical Implementation of Electron–Phonon Scattering in a Schottky Barrier CNTFET Model

by Ibrahim L. Abdalla, Fatma A. Matter, Ahmed A. Afifi, Mohamed I. Ibrahem, Hesham F. A. Hamed and Eslam S. El-Mokadem

J. Low Power Electron. Appl. 2025, 15(2), 28; https://doi.org/10.3390/jlpea15020028 - 2 May 2025

Abstract

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron [...] Read more.

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron scattering mechanisms. The analytical model is rooted in the solution of the Landauer integral equation, which is modified to account for non-ballistic transport through a set of approximations applied to the Wentzel–Kramers–Brillouin (WKB) transmission probability and the Fermi–Dirac distribution function. Our proposed model was simulated to evaluate the total current and transconductance, considering scenarios both with and without the electron–phonon scattering effect. The simulation results revealed a substantial decrease of approximately 78.6% in both total current and transconductance due to electron–phonon scattering. In addition, we investigated the impact of acoustic phonon (A-Ph) and optical phonon (O-Ph) scattering on the drain current under various conditions, including different temperatures, gate lengths, and nanotube chiralities. This comprehensive analysis helps in understanding how these parameters influence device performance. Compared with experimental data, the model’s simulation results demonstrate a high degree of agreement. Furthermore, our fully analytical model achieves a significantly faster runtime, clocking in at around 2.726 s. This validation underscores the model’s accuracy and reliability in predicting the behavior of SB-CNTFETs under non-ballistic conditions. Full article

► Show Figures

Figure 1

15 pages, 1313 KiB

Open AccessArticle

mTanh: A Low-Cost Inkjet-Printed Vanishing Gradient Tolerant Activation Function

by Shahrin Akter and Mohammad Rafiqul Haider

J. Low Power Electron. Appl. 2025, 15(2), 27; https://doi.org/10.3390/jlpea15020027 - 2 May 2025

Abstract

Inkjet-printed circuits on flexible substrates are rapidly emerging as a key technology in flexible electronics, driven by their minimal fabrication process, cost-effectiveness, and environmental sustainability. Recent advancements in inkjet-printed devices and circuits have broadened their applications in both sensing and computing. Building on [...] Read more.

Inkjet-printed circuits on flexible substrates are rapidly emerging as a key technology in flexible electronics, driven by their minimal fabrication process, cost-effectiveness, and environmental sustainability. Recent advancements in inkjet-printed devices and circuits have broadened their applications in both sensing and computing. Building on this progress, this work has developed a nonlinear computational element coined as mTanh to serve as an activation function in neural networks. Activation functions are essential in neural networks as they introduce nonlinearity, enabling machine learning models to capture complex patterns. However, widely used functions such as Tanh and sigmoid often suffer from the vanishing gradient problem, limiting the depth of neural networks. To address this, alternative functions like ReLU and Leaky ReLU have been explored, yet these also introduce challenges such as the dying ReLU issue, bias shifting, and noise sensitivity. The proposed mTanh activation function effectively mitigates the vanishing gradient problem, allowing for the development of deeper neural network architectures without compromising training efficiency. This study demonstrates the feasibility of mTanh as an activation function by integrating it into an Echo State Network to predict the Mackey–Glass time series signal. The results show that mTanh performs comparably to Tanh, ReLU, and Leaky ReLU in this task. Additionally, the vanishing gradient resistance of the mTanh function was evaluated by implementing it in a deep multi-layer perceptron model for Fashion MNIST image classification. The study indicates that mTanh enables the addition of 3–5 extra layers compared to Tanh and sigmoid, while exhibiting vanishing gradient resistance similar to ReLU. These results highlight the potential of mTanh as a promising activation function for deep learning models, particularly in flexible electronics applications. Full article

(This article belongs to the Special Issue Advancements in Low-Power Ubiquitous Sensing, Computing, and Communication Interfaces for IoT: Circuits, Systems, and Applications)

► Show Figures

Graphical abstract

10 pages, 2701 KiB

Open AccessArticle

Ultra-Thin Al₂O₃ Grown by PEALD for Low-Power Molybdenum Disulfide Field-Effect Transistors

by Shiwei Sun, Dinghao Ma, Boxi Ye, Guanshun Liu, Nanting Luo and Hao Huang

J. Low Power Electron. Appl. 2025, 15(2), 26; https://doi.org/10.3390/jlpea15020026 - 30 Apr 2025

Abstract

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness [...] Read more.

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

► Show Figures

Figure 1

10 pages, 2362 KiB

Open AccessArticle

Full-Bridge DC-DC Converter with Synchronous Rectification Based on GaN Transistors

by Xin Wang, Qingsong Zhao, Zenglong Zhao and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 25; https://doi.org/10.3390/jlpea15020025 - 22 Apr 2025

Abstract

This study presents a hard-switching full-bridge DC-DC converter with synchronous rectification based on Gallium Nitride (GaN) transistors to evaluate the advantages of GaN devices in power supplies. In comparison to traditional silicon-based devices, GaN transistors are utilized in both the primary and secondary [...] Read more.

This study presents a hard-switching full-bridge DC-DC converter with synchronous rectification based on Gallium Nitride (GaN) transistors to evaluate the advantages of GaN devices in power supplies. In comparison to traditional silicon-based devices, GaN transistors are utilized in both the primary and secondary stages of the converter, exploiting GaN’s lower on-resistance to enhance performance. The converter operates at a switching frequency of 300 kHz, with an input voltage range of 36 V to 75 V, delivering an output of 28 V/42 A. Experimental results show that the GaN-based converter achieves an output power of 1176 W within standard half-brick package dimensions. The measured peak efficiency is 97.1%, and the power density reaches 430 W/in³. These findings demonstrate that GaN-based converters offer superior efficiency and power density compared to conventional silicon-based designs, making them highly suitable for aerospace, automotive, and communication power supplies. Full article

(This article belongs to the Topic Application of Innovative Power Electronic Technologies, 2nd Edition)

► Show Figures

Figure 1

15 pages, 7333 KiB

Open AccessArticle

0.7 V Supply SC Circuits with Relaxed Slew Rate Requirements Using GB-Enhanced Multiple-Output Class AB/AB Op-Amps

by Hector Daniel Rico-Aniles, Anindita Paul, Jaime Ramirez-Angulo, Antonio Lopez-Martin and Ramon G. Carvajal

J. Low Power Electron. Appl. 2025, 15(2), 24; https://doi.org/10.3390/jlpea15020024 - 15 Apr 2025

Abstract

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature [...] Read more.

A family of improved low-voltage switched-capacitor circuits is introduced. It is based on the utilization of multiple-output class AB/AB op-amp architectures that provide true sample and hold outputs that are not subject to a reset phase as with conventional switched-capacitor circuits. This feature essentially relaxes the op-amp slew rate requirements, allowing a higher speed and simple low-voltage operation. A power-efficient GB boosting technique based on resistive local common mode feedback is used to significantly improve the GB and internal/external slew rate of the op-amps with only a 36.5% additional power dissipation. Full article

► Show Figures

Figure 1

17 pages, 6539 KiB

Open AccessArticle

Charge Pump Phase-Locked Loop-Based Frequency Conditioning of a MEMS Resonator

by Xinyuan Hu and Yanfeng Jiang

J. Low Power Electron. Appl. 2025, 15(2), 23; https://doi.org/10.3390/jlpea15020023 - 12 Apr 2025

Abstract

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked [...] Read more.

MEMS resonators have attracted attention for their wide applications in highly accurate clock references, sensors, wireless communications, frequency control, etc. Most of the output frequencies of MEMS resonators require post-processing or calibration to be accurate enough. In this paper, a charge pump phase-locked loop-based frequency conditioning method for MEMS resonators is explored. An optimization scheme is proposed to enhance the frequency stability and signal quality of MEMS resonators. The experimental results show that the method significantly improves the resonator performance and achieves effective control of the resonant frequency. This research provides a new technical path for the design of high-performance MEMS oscillators, which has important theoretical significance and practical application value. Full article

► Show Figures

Figure 1

17 pages, 2374 KiB

Open AccessArticle

A Lightweight and Configurable Flash Filesystem for Low-Power Devices

by Ondrej Kachman, Peter Malík, Marcel Baláž, Libor Majer and Gábor Gyepes

J. Low Power Electron. Appl. 2025, 15(2), 22; https://doi.org/10.3390/jlpea15020022 - 11 Apr 2025

Abstract

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient [...] Read more.

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization, minimize flash wear, and support portability across hardware platforms and operating systems. Reliability mechanisms integrated into CFFS are also discussed. We compare CFFS with widely used low-power embedded filesystems—LittleFS, SPIFFS, and FDS—highlighting its advantages in memory efficiency and reduced flash memory wear. Experimental results demonstrate that CFFS achieves up to 99% memory utilization while significantly reducing erase operations. Full article

► Show Figures

Figure 1

15 pages, 3377 KiB

Open AccessArticle

Machine Learning Using Approximate Computing

by Padmanabhan Balasubramanian, Syed Mohammed Mosayeeb Al Hady Zaheen and Douglas L. Maskell

J. Low Power Electron. Appl. 2025, 15(2), 21; https://doi.org/10.3390/jlpea15020021 - 9 Apr 2025

Abstract

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means [...] Read more.

Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means clustering, one of the more widely used unsupervised machine learning algorithms. The k-means algorithm partitions data into k clusters, where k also denotes the number of centroids, with each centroid representing the center of a cluster. The clustering process involves assigning each data point to the nearest centroid by minimizing the within-cluster sum of squares (WCSS), a key metric used to evaluate clustering quality. A lower WCSS value signifies better clustering. Conventionally, WCSS is computed with high precision using an accurate adder. In this paper, we investigate the impact of employing various approximate adders for WCSS computation and compare their results against those obtained with an accurate adder. Further, we propose a new approximate adder (NAA) in this paper. To assess its effectiveness, we utilize it for the k-means clustering of some publicly available artificial datasets with varying levels of complexity, and compare its performance with the accurate adder and many other approximate adders. The experimental results confirm the efficacy of NAA in clustering, as NAA yields WCSS values that closely match or are identical to those obtained using the accurate adder. We also implemented hardware designs of accurate and approximate adders using a 28 nm CMOS standard cell library. The design metrics estimated show that NAA achieves a 37% reduction in delay, a 22% reduction in area, and a 31% reduction in power compared to the accurate adder. In terms of the power-delay product that serves as a representative metric for energy efficiency, NAA reports a 57% reduction compared to the accurate adder. In terms of the area-delay product that serves as a representative metric for design efficiency, NAA reports a 51% reduction compared to the accurate adder. NAA also outperforms several existing approximate adders in terms of design metrics while preserving clustering effectiveness. Full article

► Show Figures

Figure 1

13 pages, 6647 KiB

Open AccessArticle

A Power-Efficient 50 MHz-BW 76.8 dB Signal-to-Noise-and-Distortion Ratio Continuous-Time 2-2 MASH Delta-Sigma Analog-to-Digital Converter with Digital Calibration

by Zhiyu Li, Xueqian Shang, Haigang Feng and Xinpeng Xing

J. Low Power Electron. Appl. 2025, 15(2), 20; https://doi.org/10.3390/jlpea15020020 - 9 Apr 2025

Abstract

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for [...] Read more.

Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB. Full article

► Show Figures

Figure 1

22 pages, 10817 KiB

Open AccessArticle

Energy Saving in Wireless Sensor Networks via LEACH-Based, Energy-Efficient Routing Protocols

by Georgios Siamantas, Dimitris Rountos and Dionisis Kandris

J. Low Power Electron. Appl. 2025, 15(2), 19; https://doi.org/10.3390/jlpea15020019 - 29 Mar 2025

Cited by 1

Abstract

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of [...] Read more.

Wireless sensor networks are at the center of scientific interest thanks to their ever-growing range of applications. The main weakness of wireless sensor networks is the restricted lifetime of their sensor nodes due to limited energy capacity. The extension of the lifespan of sensor nodes is pursued in various ways. One of them is the usage of protocols that achieve energy-efficient routing. LEACH is one of the pioneering protocols of this type and has numerous descendants. This research article focuses on energy-efficient routing protocols that are based on LEACH. Specifically, a study of LEACH along with many of its successors is provided. In addition, a novel protocol of this kind, named T-LEACH_SAS is introduced. This protocol combines the threshold-based approach for selecting cluster heads that was first introduced in T-LEACH, which is a well-known protocol, along with a mechanism for sleep–awake scheduling. The performance of T-LEACH_SAS is compared against that of both LEACH and T-LEACH via simulation tests that confirm that T-LEACH_SAS indeed provides a promising choice for energy-efficient routing in WSNs. Full article

► Show Figures

Figure 1

13 pages, 72870 KiB

Open AccessArticle

Compact High-Scanning Rate Frequency Scanning Antenna Based on Composite Right/Left-Handed Transmission Line

by Zongrui He, Kaijun Song, Jia Yao and Yedi Zhou

J. Low Power Electron. Appl. 2025, 15(2), 18; https://doi.org/10.3390/jlpea15020018 - 28 Mar 2025

Abstract

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches [...] Read more.

This paper proposes a miniaturized frequency-scanning antenna with high scanning rate. To overcome the OSB (open stopband) of traditional leaky wave antenna, CRLH-TL (Composite Right/Left-Handed-Transmission Line) is adopted. Furthermore, an antenna unit consisting of two symmetrically curved microstrip lines with two short branches is employed, whose second mode exhibits excellent transmission characteristics. The measurements demonstrate that the antenna can achieve scanning from −67.5° to 35.5° in the frequency band range of 5.65–6.5 GHz, with a scanning rate of 7.3. During scanning, the highest gain in the band is 12.3 dBi, the lowest is 10 dBi, and the gain fluctuation is within 2.3 dB, showing good scanning characteristics. Additionally, the length of the proposed antenna is approximately 3.84λ₀ for a central frequency of 5.95 GHz. Full article

► Show Figures

Figure 1

14 pages, 6516 KiB

Open AccessArticle

Junction Temperature Estimation Model of Power MOSFET Device Based on Photovoltaic Power Enhancer

by Ning Li, Shubin Zhang and Yanfeng Jiang

J. Low Power Electron. Appl. 2025, 15(2), 17; https://doi.org/10.3390/jlpea15020017 - 24 Mar 2025

Abstract

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the [...] Read more.

In a photovoltaic power enhancer system, when it is operated in current-control mode, significant nonuniform temperature distribution occurs in the converter due to thermal coupling effects, dissipative boundary conditions, and differences in device losses within the in-phase bridge. Accurate on-site estimation of the power device’s junction temperature is critical in the system design. To address this problem, a novel thermal behavior estimation model based on electro-thermal analysis is proposed in this paper, which can be used for asymmetric power MOSFETs in a photovoltaic power enhancer system. Thermal coupling effects and dissipative boundary conditions are, firstly, analyzed in a three-dimensional finite element model. A coupling impedance matrix is constructed through step power response extraction to describe the significant thermal coupling effects among devices. The complete heat sink is decoupled into several sub-parts representing different dissipative boundary conditions. A compact RC network model for estimating junction temperature is established based on the combination of the coupling impedance and the sub-heat-sink impedance. The proposed model is verified by finite element simulation and experimental measurement. Full article

► Show Figures

Figure 1

16 pages, 3892 KiB

Open AccessReview

2D Spintronics for Neuromorphic Computing with Scalability and Energy Efficiency

by Douglas Z. Plummer, Emily D’Alessandro, Aidan Burrowes, Joshua Fleischer, Alexander M. Heard and Yingying Wu

J. Low Power Electron. Appl. 2025, 15(2), 16; https://doi.org/10.3390/jlpea15020016 - 24 Mar 2025

Cited by 1

Abstract

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic [...] Read more.

The demand for computing power has been growing exponentially with the rise of artificial intelligence (AI), machine learning, and the Internet of Things (IoT). This growth requires unconventional computing primitives that prioritize energy efficiency, while also addressing the critical need for scalability. Neuromorphic computing, inspired by the biological brain, offers a transformative paradigm for addressing these challenges. This review paper provides an overview of advancements in 2D spintronics and device architectures designed for neuromorphic applications, with a focus on techniques such as spin-orbit torque, magnetic tunnel junctions, and skyrmions. Emerging van der Waals materials like CrI₃, Fe₃GaTe₂, and graphene-based heterostructures have demonstrated unparalleled potential for integrating memory and logic at the atomic scale. This work highlights technologies with ultra-low energy consumption (0.14 fJ/operation), high switching speeds (sub-nanosecond), and scalability to sub-20 nm footprints. It covers key material innovations and the role of spintronic effects in enabling compact, energy-efficient neuromorphic systems, providing a foundation for advancing scalable, next-generation computing architectures. Full article

► Show Figures

Figure 1

26 pages, 2271 KiB

Open AccessArticle

Hardware/Software Co-Design Optimization for Training Recurrent Neural Networks at the Edge

by Yicheng Zhang, Bojian Yin, Manil Dev Gomony, Henk Corporaal, Carsten Trinitis and Federico Corradi

J. Low Power Electron. Appl. 2025, 15(1), 15; https://doi.org/10.3390/jlpea15010015 - 11 Mar 2025

Abstract

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture [...] Read more.

Edge devices execute pre-trained Artificial Intelligence (AI) models optimized on large Graphical Processing Units (GPUs); however, they frequently require fine-tuning when deployed in the real world. This fine-tuning, referred to as edge learning, is essential for personalized tasks such as speech and gesture recognition, which often necessitate the use of recurrent neural networks (RNNs). However, training RNNs on edge devices presents major challenges due to limited memory and computing resources. In this study, we propose a system for RNN training through sequence partitioning using the Forward Propagation Through Time (FPTT) training method, thereby enabling edge learning. Our optimized hardware/software co-design for FPTT represents a novel contribution in this domain. This research demonstrates the viability of FPTT for fine-tuning real-world applications by implementing a complete computational framework for training Long Short-Term Memory (LSTM) networks utilizing FPTT. Moreover, this work incorporates the optimization and exploration of a scalable digital hardware architecture using an open-source hardware-design framework, named Chipyard and its implementation on a Field-Programmable Gate Array (FPGA) for cycle-accurate verification. The empirical results demonstrate that partitioned training on the proposed architecture enables an 8.2-fold reduction in memory usage with only a 0.2× increase in latency for small-batch sequential MNIST (S-MNIST) compared to traditional non-partitioned training. Full article

► Show Figures

Figure 1

20 pages, 1710 KiB

Open AccessArticle

Design of Ultra-Low-Power Rail-to-Rail Input Common Mode Range Standard-Cell-Based Comparators

by Antonio Manno, Giuseppe Scotti and Gaetano Palumbo

J. Low Power Electron. Appl. 2025, 15(1), 14; https://doi.org/10.3390/jlpea15010014 - 8 Mar 2025

Abstract

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with [...] Read more.

In this paper, a NOR2 standard-cell-based dynamic comparator providing rail-to-rail input common mode range (ICMR) is presented, together with a novel standard-cell oriented design methodology. The proposed topology provides better speed performance and lower power-delay-product than the previously presented standard-cell-based dynamic comparators with rail-to-rail ICMR features. The NOR2 topology, which is also better than the complementary NAND2-based topology previously presented by the authors, is even able to guarantee improvements in the order of 8× –16× higher speed and 7× lower PDP, with respect to the other rail-to-rail ICMR standard-cell-based topologies in the literature. Concerning the standard-cell oriented design methodology, it is focused on the impact of the cell’s strength, which is the only free parameter, on delay, power consumption, ICMR and offset. The circuit performances are demonstrated for supply voltages equal to 600 mV, 300 mV and 150 mV, considering a 45 nm CMOS technology. Full article

► Show Figures

Figure 1

Journal Description

Journal of Low Power Electronics and Applications

Latest Articles

Journal Menu

Journal Browser

Highly Accessed Articles

Latest Books

E-Mail Alert

News

Topics

Conferences

Special Issues

Further Information

Guidelines

MDPI Initiatives

Follow MDPI