Journal of Low Power Electronics and Applications — Open Access Journal

Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve the mobile user experience. However, satisfying all power and performance requirements of such low power devices is a significant challenge. Recent work has shown that binarizing a neural network can significantly improve the memory requirements of mobile devices at the cost of minor loss in accuracy. This paper proposes MB-CNN, a memristive accelerator for binary convolutional neural networks that perform XNOR convolution in-situ novel 2R memristive data blocks to improve power, performance, and memory requirements of embedded mobile devices. The proposed accelerator achieves at least $13.26\times$, $5.91\times$, and $3.18\times$ improvements in the system energy efficiency (computed by energy × delay) over the state-of-the-art software, GPU, and PIM architectures, respectively. The solution architecture which integrates CPU, GPU and MB-CNN outperforms every other configuration in terms of system energy and execution time. Full article

Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level. Full article

The high-pressure (HP) injector is a highly dynamic component requiring careful voltage and pressure input modulation to achieve the required fuel injection quantities of gasoline direct injection (GDI) engines. Accurate fuel injection curves are a key influence for this technology, and therefore, will require an accurate estimation of fuel flow rate to be realized. In order to be driven to rapid response with respect to solenoid valve coils, HP injectors typically require to be designed to be capable of rapid response in GDI engines. In this paper, the design and analysis of the proposed injector drive circuit are presented. Next, the effects of total pulse width, injector supply voltage, fuel system pressure, and pulse width modulation (PWM) operation on fuel injection quantities of an HP injector are measured for achieving robust performance and stability in the presence of bounded errors of the GDI injectors due to total pulse width, injector’s supply voltage, fuel pressure and PWM operation. Additionally, the fuel injection quantities of the HP injector are measured by tuning the parameters of the injector drive circuit with the PWM operation. These are defined as the fuel injection curves. Finally, experimental results are provided for verification of the proposed injector drive circuit. Full article

The sector of autonomous driving gains more and more importance for the car makers. A key enabler of such systems is the planning of the path the vehicle should take, but it can be very computationally burdensome finding a good one. Here, new architectures in Electronic Control Units (ECUs) are required, such as Graphics Processing Units (GPUs), because standard processors struggle to provide enough computing power. In this work, we present a novel parallelization of a path planning algorithm. We show how many paths can be reasonably planned under real-time requirements and how they can be rated. As an evaluation platform, an Nvidia Jetson board equipped with a Tegra K1 System-on-Chip (SoC) was used, whose GPU is also employed in the zFAS ECU of the AUDI AG. Full article

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency. Full article

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error. Full article

Porous materials have superior electrochemical performance owing to its their structure, which could increase the specific and contact area with the electrode. The spinel Li₄Mn₅O₁₂ has a three-dimensional tunnel structure for a better diffusion path, which has the advantage of lithium ion insertion and extraction in the framework. However, multi-space spherical materials with single morphologies are rarely studied. In this work, waxberry-like and raspberry-like nanospheres for Li₄Mn₅O₁₂ have been fabricated by the wet chemistry and solid-state methods for the first time. The diameter of a single waxberry- and raspberry-like nanosphere is about 1 μm and 600 nm, respectively. The specific capacitance of Li₄Mn₅O₁₂ was 535 mF cm⁻² and 147.25 F g⁻¹ at the scan rate of 2 mV s⁻¹, and the energy density was 110.7 Wh kg⁻¹, remaining at 70% after 5000th charge-discharge cycles. Compared with raspberry-like nanosphere Li₄Mn₅O₁₂, the waxberry-like nanoporous spinel Li₄Mn₅O₁₂ shows the better electrochemical performance and stability; furthermore, these electrochemical performances have been improved greatly compared to the previous studies. All these results indicate that the waxberry-like nanoporous spinel Li₄Mn₅O₁₂ could provide a potential application in high performance supercapacitors. Full article

Quantum-dot cellular automata (QCA) is a low-power, non-von-Neumann, general-purpose paradigm for classical computing using transistor-free logic. Here, classical bits are encoded on the charge configuration of individual computing primitives known as “cells.” A cell is a system of quantum dots with a few mobile charges. Device switching occurs through quantum mechanical inter-dot charge tunneling, and devices are interconnected via the electrostatic field. QCA devices are implemented using arrays of QCA cells. A molecular implementation of QCA may support THz-scale clocking or better at room temperature. Molecular QCA may be clocked using an applied electric field, known as a clocking field. A time-varying clocking field may be established using an array of conductors. The clocking field determines the flow of data and calculations. Various arrangements of clocking conductors are laid out, and the resulting electric field is simulated. It is shown that that control of molecular QCA can enable feedback loops, memories, planar circuit crossings, and versatile circuit grids that support feedback and memory, as well as data flow in any of the ordinal grid directions. Logic, interconnect and memory now become indistinguishable, and the von Neumann bottleneck is avoided. Full article

We calculate the excess energy transferred into two-dot and three-dot quantum dot cellular automata systems during switching events. This is the energy that must eventually be dissipated as heat. The adiabaticity of a switching event is quantified using the adiabaticity parameter of Landau and Zener. For the logically reversible operations of WRITE or ERASE WITH COPY, the excess energy transferred to the system decreases exponentially with increasing adiabaticity. For the logically irreversible operation of ERASE WITHOUT COPY, considerable energy is transferred and so must be dissipated, in accordance with the Landauer Principle. The exponential decrease in energy dissipation with adiabaticity (e.g., switching time) distinguishes adiabatic quantum switching from the usual linear improvement in classical systems. Full article

Single-phase transformerless inverters are broadly studied in literature for residential-scale PV applications due to their great advantages in reducing system weight, cost and elevating system efficiency. The design of transformerless inverters is based on the galvanic isolation method to eliminate the generation of leakage current. Unfortunately, the use of the galvanic isolation method alone cannot achieve constant common mode voltage (CMV). Therefore, a complete elimination of leakage current cannot be achieved. In addition, modulation techniques of single-phase transformerless inverters are designed for the application of the unity power factor. Indeed, next-generation PV systems are required to support reactive power to enable connectivity to the utility grid. In this paper, a proposed single-phase transformerless inverter is modified with the clamping method to achieve constant CMV during all inverter operating modes. Furthermore, the modulation technique is modified by creating a new current path in the negative power region. As a result, a bidirectional current path is created in the negative power region to achieve reactive power generation. The simulation results show that the CMV is completely clamped at half the DC link voltage and the leakage current is almost completely eliminated. Furthermore, a reactive power generation is achieved with the modified modulation techniques. Additionally, the total harmonic distortion (THD) of the grid current with the conventional and a modified modulation technique is analyzed. The efficiency of the system is enhanced by using wide-bandgap (WBG) switching devices such as SiC MOSFET. It is observed that the efficiency of the system decreased with reactive power generation due to the bidirectional current path, which leads to increasing conduction losses. Full article

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property i n near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up. Full article

This paper presents a power efficient analog front-end (AFE) for electrocardiogram (ECG) signal monitoring and arrhythmia diagnosis. The AFE uses low-noise and low-power circuit design methodologies and aggressive voltage scaling to satisfy both the low power consumption and low input-referred noise requirements of ECG signal acquisition systems. The AFE was realized with a three-stage fully differential AC-coupled amplifier, and it provides bio-signal acquisition with programmable gain and bandwidth. The AFE was implemented in a 130 nm CMOS process, and it has a measured tunable mid-band gain from 31 to 52 dB with tunable low-pass and high-pass corner frequencies. Under only 0.5 V supply voltage, it consumes 68 nW of power with an input-referred noise of 2.8 µVrms and a power efficiency factor (PEF) of 3.9, which makes it very suitable for energy-harvesting applications. The low-noise 68nW AFE was also integrated on a self-powered physiological monitoring System on Chip (SoC) that is used to capture ECG bio-signals. Heart rate extraction (R-R) detection algorithms were implemented and utilized to analyze the ECG data received by the AFE, showing the feasibility of <100 nW AFE for continuous ECG monitoring applications. Full article

Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the car, not only for embedding consumer electronics, but also as a fast and reliable backbone for control applications. Still, low-cost but highly reliable sensors connected over the traditional Controller Area Network (CAN) deliver data needed for autonomous driving. To fusion the data efficiently among all, a common timebase is required. The alternative would be oversampling, which uses more time and energy, e.g., at least double the perception rates of sensors. Ethernet and CAN do require the latter by default. Hence, a global synchronization mechanism eases tremendously the design of a low power automotive network and is the foundation of a transparent global clock. In this article, we present the first step: Synchronizing legacy FlexRay networks to the upcoming Ethernet backbone, which will contain a precise clock over the generalized Precision Time Protocol (gPTP) defined in IEEE 802.1AS. FlexRay then could still drive its strengths with deterministic transmission behavior and possibly also serve as a redundant technology for fail-operational system design. Full article

In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-V_dd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-V_dd CAM chip along with an exploration of the multi-V_dd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-V_dd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-V_dd design operating over the same voltage range with equivalent noise margin. Our multi-V_dd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis. Full article

Notwithstanding the increasing interest in Molecular Quantum-Dot Cellular Automata (MQCA) as emerging devices for computation, a characterization of their behavior from an electronic standpoint is not well-stated. Devices are typically analyzed with quantum physics-based approaches which are far from the electronic engineering world and make it difficult to design, simulate and fabricate molecular devices. In this work, we define new figures of merits to characterize the molecules, which are based on the post-processing of results obtained from ab initio simulations. We define the Aggregated Charge (AC), the electric-field generated at the receiver molecule (EFGR), the Vin–Vout and Vin–AC transcharacteristics (VVT and VACT), the Vout maps (VOM) and the MQCA cell working zones (CWZ). These quantities are compatible with an electronic engineering point of view and can be used to analyze the capability of molecules to propagate information. We apply and verify the methodology to three molecules already proposed in the literature for MQCA and we state to which extent these molecules can be effective for computation. The adopted methodology provides the quantitative characterization of the molecules necessary for digital designers, to design digital circuits, and for technologists, to the future fabrication of MQCA devices. Full article

A three-dimensional thermal simulation investigation for the thermal management of GaN-on-SiC monolithic microwave integrated circuits (MMICs) of consisting multi-fingers (HEMTs) is presented. The purpose of this work is to demonstrate the utility and efficiency of the three-dimensional Transmission Line Matrix method (3D-TLM) in a thermal analysis of high power AlGaN/GaN heterostructures single gate and multi-fingers HEMT SSPA (solid state power amplifiers). The self-heating effects induce thermal cross-talk between individual fingers in multi-finger AlGaN/GaN that affect device performance and reliability. Gate-finger temperature differences only arise after a transient state, due to the beginning of thermal crosstalk which is attributed to the finite rate of heat diffusion between gate fingers. The TLM method accounts for the real geometrical structure and the non-linear thermal conductivities of GaN and SiC in order to improve the realistic calculations accuracy heat dissipation and thermal behavior of the device. In addition, two types of heat sources located on the top of GaN layer are considered in thermal simulations: Nano-scale hotspot as a pulsed wave heat source under gate and micro-scale hotspot as a continuous wave heat source, between gate and drain. Heat diffusion however, occurs not only between individual gate fingers (inter-finger) in a multi-finger HEMT, but also within each gate finger (intra-finger). To compare results, a Micro-Raman Spectroscopy experience is conducted to obtain a detailed and accurate temperature distribution. Good agreement between the microscopic spectral measurement and TLM simulation results is observed by accepting an error less than 2.2% relative to a maximum temperature. Results show that the 3D-TLM method is suitable for understanding heat management in particular for microwave devices AlGaN/GaN HEMTs SSPA amplifier. TLM method helps to select and locates the expected hot spots and to highlight the need of thermal study pre-design in order to minimize the system-level thermal dissipation and lead therefore to higher reliability. Full article

Reducing voltage supply is one of the most effective way to reduce the power consumption, but, on the other hand it is a challenging choice for the analog designers. In this paper, different topologies, well-suited for low voltage and ultra-low voltage supply, are depicted, investigated, designed in the same standard 180 nm technology and compared, highlighting the benefits and the possible applications. Full article

This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design choices that optimize the system and improve its reliability. We look into how to use these features to build the digital sub-system by determining the blocks to implement, the digital architecture, the clock rate of the system, the memory capacity, and the low power states. We also review how these features impact the choice of energy harvesting power management units. Full article

The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 μm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations. Full article