You seem to have javascript disabled. Please note that many of the page functionalities won't work as expected without javascript enabled.

Search for Articles:

Title / Keyword

Author / Affiliation / Email

Journal

Article Type

Advanced Search

Section

Special Issue

Volume

Issue

Number

Page

Logical OperatorOperator

Search Text

Search Type

Journal Description

Journal of Low Power Electronics and Applications

Journal of Low Power Electronics and Applications is an international, peer-reviewed, open access journal on low power electronics published quarterly online by MDPI.

Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and other databases.
Rapid Publication: manuscripts are peer-reviewed and a first decision is provided to authors approximately 24.2 days after submission; acceptance to publication is undertaken in 3.8 days (median values for papers published in this journal in the second half of 2025).
Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Journal Cluster of Electronic Engineering and Hardware Systems: Chips, Electronics, Hardware, Journal of Low Power Electronics and Applications, Microelectronics and Microwave.

Impact Factor: 1.8 (2024); 5-Year Impact Factor: 1.6 (2024)

Imprint Information Journal Flyer Open Access ISSN: 2079-9268

Latest Articles

23 pages, 2239 KB

Open AccessArticle

SparseDroop: Hardware–Software Co-Design for Mitigating Voltage Droop in DNN Accelerators

by Arnab Raha, Shamik Kundu, Arghadip Das, Soumendu Kumar Ghosh and Deepak A. Mathaikutty

J. Low Power Electron. Appl. 2026, 16(1), 2; https://doi.org/10.3390/jlpea16010002 - 23 Dec 2025

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) [...] Read more.

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (

I C C_{m a x}

) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths

I C C

trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining

I C C_{m a x}

and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning. Full article

► Show Figures

Figure 1

14 pages, 1157 KB

Open AccessArticle

Hardware-Friendly and Efficient Vision Transformer for Deployment on Low-Power Embedded Device

by Ziyang Chen, Ming Hao, Xinye Cao, Jingwei Zhang, Chaoyao Shen, Guoqing Li and Meng Zhang

J. Low Power Electron. Appl. 2026, 16(1), 1; https://doi.org/10.3390/jlpea16010001 - 22 Dec 2025

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained [...] Read more.

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained platforms. To address these challenges, this paper proposes a hardware-friendly CNN-Transformer hybrid pyramid architecture that effectively balances accuracy, efficiency, and deployability. The proposed model integrates convolutional bottlenecks with Transformer encoders to capture both local and global contextual information while maintaining low computational cost. A pyramid feature extraction structure is further introduced to enhance multi-scale semantic representation. To improve hardware efficiency, we redesign key nonlinear components by introducing hardware-friendly activation, normalization, and Softmax approximations. Specifically, GELU and LN are replaced by ReLU and Batch Normalization (BN), and a simplified logarithmic-exponential formulation termed Softmax2 is proposed, which eliminates complex exponential and division operations, significantly reducing hardware implementation cost. Extensive experiments demonstrate the effectiveness of the proposed framework. The experimental results validate that the proposed architecture offers a promising and practical solution for real-time and embedded vision applications. Full article

► Show Figures

Figure 1

13 pages, 3375 KB

Open AccessArticle

A Self-Contained Startup Charging Circuit for Energy-Harvesting Batteryless IoT Devices

by Michelle Libang, Kriz Kevin Adrivan, Jefferson A. Hora, Charade G. Avondo, Robert M. Comaling, Xi Zhu and Yichuang Sun

J. Low Power Electron. Appl. 2025, 15(4), 71; https://doi.org/10.3390/jlpea15040071 - 18 Dec 2025

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the [...] Read more.

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C. Full article

► Show Figures

Figure 1

14 pages, 1586 KB

Open AccessArticle

Efficient Error Correction Coding for Physically Unclonable Functions

by Sreehari K. Narayanan, Ramesh Bhakthavatchalu and Remya Ajai Ajayan Sarala

J. Low Power Electron. Appl. 2025, 15(4), 70; https://doi.org/10.3390/jlpea15040070 - 12 Dec 2025

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an [...] Read more.

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an efficient scheme that integrates a delay-base d PUF with a Low-Density Parity-Check (LDPC) code. Specifically, a feed-forward PUF is combined with LDPC coding to reliably regenerate the cryptographic key. Our design reproduces the key with minimal error using channel coding. The scheme achieves 96% key-generation reliability, representing a notable improvement over PUF-based key generation without error-correction coding. LDPC decoding with the min-sum algorithm provides better error correction than the bit-flipping algorithm, but it is more computationally intensive. We could design the proposed scheme with minimum hardware resource utilization using Xilinx Vivado 2018.2 and Cadence Genus tools. Full article

► Show Figures

Figure 1

25 pages, 1878 KB

Open AccessArticle

Slope Compensation and Bifurcation in a DC-DC, Single-Input, Multiple-Output, CMOS Integrated Converter Under Current-Mode and Comparator-Based Hybrid Control

by Mathieu Ginet, Eric Feltrin, Nicolas Jeanniot, Bruno Allard and Xuefang Lin-Shi

J. Low Power Electron. Appl. 2025, 15(4), 69; https://doi.org/10.3390/jlpea15040069 - 12 Dec 2025

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a [...] Read more.

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

► Show Figures

Figure 1

18 pages, 3817 KB

Open AccessArticle

Analysis of Core Temperature Dynamics in Multi-Core Processors

by Leena Ladge and Y. Srinivasa Rao

J. Low Power Electron. Appl. 2025, 15(4), 68; https://doi.org/10.3390/jlpea15040068 - 2 Dec 2025

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by [...] Read more.

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency. Full article

► Show Figures

Figure 1

15 pages, 3792 KB

Open AccessArticle

A Dynamic Current Pulsing Technique to Improve the Noise Efficiency Factor of Neural Recording Amplifiers

by Yujia Huo and Roy H. Olsson III

J. Low Power Electron. Appl. 2025, 15(4), 67; https://doi.org/10.3390/jlpea15040067 - 1 Dec 2025

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor [...] Read more.

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor (NEF) beyond that achievable using traditional design. A low NEF of 1.55 is achieved at an average power consumption of 587.8 nW and 5.18 µVrms noise, integrated from 0.1 to 9.8 kHz, inclusive of the impacts of sampling and aliasing. The NEF is improved from 1.76 in the static low current state (LCS) and 1.67 in the static high current state (HCS), measured on the same amplifier chip. Full article

► Show Figures

Figure 1

29 pages, 3796 KB

Open AccessReview

Research on the Security of SRAM-Based FPGAs in the Era of Artificial Intelligence

by Jing Zhou, Xiangyu Zhao, Shengbing Zhang, Lei Chen, Ke Xiao and Shuo Wang

J. Low Power Electron. Appl. 2025, 15(4), 66; https://doi.org/10.3390/jlpea15040066 - 28 Nov 2025

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics [...] Read more.

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

► Show Figures

Figure 1

17 pages, 6041 KB

Open AccessArticle

An Ultra-Low-Quiescent-Current On-Chip Energy Management Circuit in 65 nm CMOS for Energy Harvesting Applications

by Mehdi Shahabi, Noemi Perez, Hector Solar and Andoni Beriain

J. Low Power Electron. Appl. 2025, 15(4), 65; https://doi.org/10.3390/jlpea15040065 - 13 Nov 2025

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems [...] Read more.

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems operating under strict energy limitations. The design relies on a compact latch-based core and avoids the need for extra circuits such as voltage references, comparators, or logic blocks, which helps reduce both area and power. To implement the required high resistance, a series of diode-connected zero-threshold NMOS transistors is used. This approach enables very high resistance in a compact area without additional power consumption or biasing issues at low voltages. A PMOS transistor is also integrated at the EM output to directly control different types of loads. The circuit was designed and fabricated using a 65 nm CMOS standard process. Experimental measurements from the fabricated chips show a quiescent current of 170 nA at 3 V and a voltage hysteresis of over 0.9 V. In addition, temperature and process variation were simulated to verify robust operation. These results confirm that the circuit operates reliably under ultra-low-power conditions and is well-suited for EH systems. Full article

► Show Figures

Figure 1

34 pages, 3920 KB

Open AccessArticle

Towards Memory-Efficient and High-Performance Branch Prediction: The LXOR Architecture for Control Flow Optimization in Embedded and General-Purpose RISC-V Processors

by Devendra G. Sutar and Nitesh B. Guinde

J. Low Power Electron. Appl. 2025, 15(4), 64; https://doi.org/10.3390/jlpea15040064 - 24 Oct 2025

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, [...] Read more.

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, PAg, PAp, Gshare, Gselect) that rely on large Pattern History Tables (PHTs) or intricate global/local history combinations, the LXOR predictor employs complemented local history and XOR-based indexing, optimizing table access and reducing aliasing. Implemented and evaluated using the MARSS-RISCV simulator on a 64-bit in-order RISC-V core, the LXOR’s performance was compared against traditional predictors using Coremark and SPEC CPU2017 benchmarks. The LXOR consistently achieved competitive results, with a prediction accuracy of up to 83.92%, lower misprediction rates, and instruction flushes as low as 5.83%. It also attained an IPC rate of up to 0.83, all while maintaining a compact memory footprint of approximately 2 KB, significantly smaller than current alternatives. These findings demonstrate that the LXOR predictor not only matches the performance of more complex predictors but does so with less memory and logic overhead, making it ideal for embedded systems, low-power RISC-V processors, and resource-constrained IoT and edge devices. By balancing prediction accuracy with simplicity, the LXOR offers a scalable and cost-effective solution for next-generation microprocessors. Full article

► Show Figures

Figure 1

16 pages, 955 KB

Open AccessArticle

A Multiplierless Architecture for Image Convolution in Memory

by John Reuben, Felix Zeller, Benjamin Seiler and Dietmar Fey

J. Low Power Electron. Appl. 2025, 15(4), 63; https://doi.org/10.3390/jlpea15040063 - 23 Oct 2025

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring [...] Read more.

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring

{(n - (k - 1))}^{2}

Inner Product (IP) computations for convolution of a

n \times n

image with a

k \times k

kernel. For example, for a convolution of a 224 × 224 image with a 3 × 3 kernel, 49,284 IPs need to be computed, where each IP requires nine multiplications and eight additions. This is a major hurdle for in-memory implementation because in-memory adders and multipliers are extremely slow compared to CMOS multipliers. In this work, we revive an old technique called ‘Distributed Arithmetic’ and judiciously apply it to perform image convolution in memory without area-intensive hard-wired multipliers. Distributed arithmetic performs multiplication using shift-and-add operations, and they are implemented using CMOS circuits in the periphery of ReRAM memory. Compared to Google’s TPU, our in-memory architecture requires 56× less energy while incurring 24× more latency for convolution of a 224 × 224 image with a 3 × 3 filter. Full article

(This article belongs to the Special Issue Energy Consumption Management in Electronic Systems)

► Show Figures

Figure 1

19 pages, 9685 KB

Open AccessArticle

Dynamics of a Neuromorphic Circuit Incorporating a Second-Order Locally Active Memristor and Its Parameter Estimation

by Shivakumar Rajagopal, Viet-Thanh Pham, Fatemeh Parastesh, Karthikeyan Rajagopal and Sajad Jafari

J. Low Power Electron. Appl. 2025, 15(4), 62; https://doi.org/10.3390/jlpea15040062 - 13 Oct 2025

Cited by 1

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors [...] Read more.

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors (LAMs), with their ability to amplify small perturbations within a locally active domain to generate action potential-like responses, provide powerful building blocks for neuromorphic circuits and offer new perspectives on the mechanisms underlying neuronal firing dynamics. This paper introduces a novel second-order locally active memristor (LAM) governed by two coupled state variables, enabling richer nonlinear dynamics compared to conventional first-order devices. Even when the capacitances controlling the states are equal, the device retains two independent memory states, which broaden the design space for hysteresis tuning and allow flexible modulation of the current–voltage response. The second-order LAM is then integrated into a FitzHugh–Nagumo neuron circuit. The proposed circuit exhibits oscillatory firing behavior under specific parameter regimes and is further investigated under both DC and AC external stimulation. A comprehensive analysis of its equilibrium points is provided, followed by bifurcation diagrams and Lyapunov exponent spectra for key system parameters, revealing distinct regions of periodic, chaotic, and quasi-periodic dynamics. Representative time-domain patterns corresponding to these regimes are also presented, highlighting the circuit’s ability to reproduce a rich variety of neuronal firing behaviors. Finally, two unknown system parameters are estimated using the Aquila Optimization algorithm, with a cost function based on the system’s return map. Simulation results confirm the algorithm’s efficiency in parameter estimation. Full article

► Show Figures

Figure 1

15 pages, 1662 KB

Open AccessArticle

Adaptive Hybrid Switched-Capacitor Cell Balancing for 4-Cell Li-Ion Battery Pack with a Study of Pulse-Frequency Modulation Control

by Wu Cong Lim, Liter Siek and Eng Leong Tan

J. Low Power Electron. Appl. 2025, 15(4), 61; https://doi.org/10.3390/jlpea15040061 - 1 Oct 2025

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor [...] Read more.

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers. Full article

► Show Figures

Figure 1

26 pages, 2759 KB

Open AccessReview

MCU Intelligent Upgrades: An Overview of AI-Enabled Low-Power Technologies

by Tong Zhang, Bosen Huang, Xiewen Liu, Jiaqi Fan, Junbo Li, Zhao Yue and Yanfang Wang

J. Low Power Electron. Appl. 2025, 15(4), 60; https://doi.org/10.3390/jlpea15040060 - 1 Oct 2025

Cited by 2

Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly [...] Read more.

Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly critical. This paper systematically reviews the development history and current technical challenges of MCU low-power technology. It then focuses on analyzing system-level low-power optimization pathways for integrating MCUs with artificial intelligence (AI) technology, including lightweight AI algorithm design, model pruning, AI acceleration hardware (NPU, GPU), and heterogeneous computing architectures. It further elaborates on how AI technology empowers MCUs to achieve comprehensive low power consumption from four dimensions: task scheduling, power management, inference engine optimization, and communication and data processing. Through practical application cases in multiple fields such as smart home, healthcare, industrial automation, and smart agriculture, it verifies the significant advantages of MCUs combined with AI in performance improvement and power consumption optimization. Finally, this paper focuses on the key challenges that still need to be addressed in the intelligent upgrade of future MCU low power consumption and proposes in-depth research directions in areas such as the balance between lightweight model accuracy and robustness, the consistency and stability of edge-side collaborative computing, and the reliability and power consumption control of the sensor-storage-computing integrated architecture, providing clear guidance and prospects for future research. Full article

► Show Figures

Figure 1

3 pages, 161 KB

Open AccessEditorial

Ultra-Low-Power ICs for the Internet of Things (2nd Edition)

by Orazio Aiello

J. Low Power Electron. Appl. 2025, 15(4), 59; https://doi.org/10.3390/jlpea15040059 - 1 Oct 2025

After the success of the first edition [...] Full article

(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things (2nd Edition))

14 pages, 3756 KB

Open AccessArticle

Active Quasi-Circulator Based on Wilkinson Power Divider for Low-Power Wireless Communication Systems

by Kaijun Song, Xinsheng Chen and Zongrui He

J. Low Power Electron. Appl. 2025, 15(4), 58; https://doi.org/10.3390/jlpea15040058 - 1 Oct 2025

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and [...] Read more.

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%. Full article

► Show Figures

Figure 1

28 pages, 7493 KB

Open AccessArticle

Research on Frequency Characteristic Fitting of LLC Switching-Mode Power Supply Under All Operating Conditions Based on FT-WOA-MLP

by Jiale Guo, Rongsheng Han, Zibo Yang, Guoqing An, Rui Li and Long Zhang

J. Low Power Electron. Appl. 2025, 15(4), 57; https://doi.org/10.3390/jlpea15040057 - 28 Sep 2025

The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method [...] Read more.

The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method for all operating conditions based on FT-WOA-MLP. A discrete-point dataset covering all conditions of an LLC SMPS was obtained using the small-signal perturbation method, including input voltage, output current, injection frequency, and corresponding amplitude- and phase-frequency characteristics. The multilayer perceptron (MLP) model was trained on the training set covering all operating conditions, with the whale optimization algorithm (WOA) used to optimize the learning rate, and fine tuning (FT) applied to further enhance accuracy. Independent test set validation showed that, for amplitude-frequency characteristics, the mean absolute error (MAE) was 2.0995, the mean absolute percentage error (MAPE) was 0.0974, the root mean square error (RMSE) was 4.0474, and the coefficient of determination (R²) reached 0.92; for phase-frequency characteristics, the MAE was 3.502, the MAPE was 0.0956, the RMSE was 10.5192, and the R² reached 0.94. The method accurately fits frequency characteristics under all conditions, supporting defect identification and performance optimization. Full article

► Show Figures

Figure 1

18 pages, 2888 KB

Open AccessArticle

Data Analysis of Electrical Impedance Spectroscopy-Based Biosensors Using Artificial Neural Networks for Resource Constrained Devices

by Marco Grossi and Martin Omaña

J. Low Power Electron. Appl. 2025, 15(4), 56; https://doi.org/10.3390/jlpea15040056 - 26 Sep 2025

Cited by 1

Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors [...] Read more.

Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors are devices that use electrochemical techniques to measure a target analyte. In the case of electrochemical biosensors based on EIS, the measured impedance spectrum is fitted to that of an equivalent electrical circuit, whose component values are then used to estimate the concentration of the target analyte. Fitting EIS data is usually carried out by sophisticated algorithms running on a PC. In this paper, we have evaluated the feasibility to perform EIS data fitting using simple Artificial Neural Networks (ANNs) that can be run on resource constrained microcontrollers, which are typically used for portable and wearable sensors. We considered a typical case of an impedance spectrum in the range 0.1 Hz–10 kHz, modeled by using the simplified Randles equivalent circuit. Our analyses have shown that simple ANNs can be a low power alternative to perform EIS data fitting on low-cost microcontrollers with a memory occupation in the order of kilo bytes and a measurement accuracy between 1% and 3%. Full article

► Show Figures

Figure 1

37 pages, 14177 KB

Open AccessReview

Wake-Up Receivers: A Review of Architectures Analysis, Design Techniques, Theories and Frontiers

by Suhao Chen, Xiaopeng Yu and Xiongchun Huang

J. Low Power Electron. Appl. 2025, 15(4), 55; https://doi.org/10.3390/jlpea15040055 - 23 Sep 2025

The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art [...] Read more.

The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art in WuRXs design, focusing on low-power architectures, key trade-offs, and recent advancements. We discuss the challenges in achieving low power consumption while maintaining sensitivity, power consumption, and interference resilience. The review highlights the evolution from radio frequency (RF) envelope detection architectures to more complex heterodyne and subthreshold designs and concludes with future directions for WuRXs research. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

► Show Figures

Figure 1

20 pages, 5246 KB

Open AccessArticle

Class E ZVS Resonant Inverter with CLC Filter and PLL-Based Resonant Frequency Tracking for Ultrasonic Piezoelectric Transducer

by Apinan Aurasopon, Boontan Sriboonrueng, Jirapong Jittakort and Saichol Chudjuarjeen

J. Low Power Electron. Appl. 2025, 15(3), 54; https://doi.org/10.3390/jlpea15030054 - 22 Sep 2025

This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically [...] Read more.

This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically monitor and adjust the operating frequency in response to slight variations in the cleaning load, employing a phase-locked loop (PLL) control scheme. The proposed method ensures that the inverter maintains ZVS operation across a frequency range from 30.0 kHz to 34.0 kHz, thereby improving energy efficiency and reducing switching losses. The system is capable of delivering a stable power output of 100 W. Both the simulation and experimental results validate the effectiveness of the proposed technique, demonstrating improved performance under varying load conditions. The combination of CLC filtering and frequency tracking offers a compact and robust solution suitable for ultrasonic cleaner systems and similar resonant-load applications. Full article

► Show Figures

Figure 1

More Articles...

Submit to JLPEA Review for JLPEA

Journal Menu

Journal Browser

► Journal Browser

Highly Accessed Articles

View More...

Latest Books

More Books and Reprints...

E-Mail Alert

News

6 November 2025
MDPI Launches the Michele Parrinello Award for Pioneering Contributions in Computational Physical Science

9 October 2025
Meet Us at the 3^rd International Conference on AI Sensors and Transducers, 2–7 August 2026, Jeju, South Korea

1 October 2025
2024 MDPI Top 1000 Reviewers

More News & Announcements...

Topics

Propose a Topic

Topic in Electronics, Eng, JLPEA, Micromachines, Nanomaterials

Advanced Integrated Circuit Design and Application Topic Editors: Shoue Chen, Xiaolong Wang, Ke Xie
Deadline: 30 April 2026

Topic in Applied Mechanics, JLPEA, JSAN, ASI

Application of IOT on Manufacturing, Communication and Engineering, 2nd Volume Topic Editors: Teen-Hang Meen, Chun-Yen Chang, Charles Tijus, Cheng-Fu Yang, Shu-Han Liao
Deadline: 31 May 2026

Topic in Electronics, Sensors, Micromachines, JLPEA, Semiconductors and Heterogeneous Integration, Chips, Hardware, Encyclopedia

Edge AI: From Intelligent Sensing to AI-Dedicated Hardware Topic Editors: Laura Falaschetti, Giorgio Biagetti
Deadline: 31 December 2026

Conferences

Propose a Conference Collaboration

2–7 August 2026 The 3rd International Conference on AI Sensors and Transducers

More Conferences...

Special Issues

Propose a Special Issue

Special Issue in JLPEA

Electron Devices and Solid-State Circuits (EDSSC 2025) Guest Editors: Lei Xu, Yuan Xiao Ma, Yitu Wang, Zhihua Zhu
Deadline: 31 January 2026

Special Issue in JLPEA

Low Power Sensing and Energy Harvesting for Self-Sustained Electronics Guest Editors: Bingang Xu, Yujue Yang
Deadline: 31 May 2026

Special Issue in JLPEA

Sustainable Wireless Sensor Networks: Recent Trends and Advances Guest Editors: Dionisis Kandris, Eleftherios Anastasiadis
Deadline: 30 September 2026

Special Issue in JLPEA

15th Anniversary of Journal of Low Power Electronics and ApplicationsGuest Editor: Davide Bertozzi
Deadline: 30 September 2026

More Special Issues

Back to TopTop