Journal Description
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications
is an international, interdisciplinary, peer-reviewed, open access journal on low power electronics and is published quarterly online by MDPI.
- Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
- High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and many other databases.
- Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
- Rapid Publication: manuscripts are peer-reviewed and a first decision provided to authors approximately 16.3 days after submission; acceptance to publication is undertaken in 2.9 days (median values for papers published in this journal in the first half of 2021).
- Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Latest Articles
A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs
J. Low Power Electron. Appl. 2021, 11(3), 32; https://doi.org/10.3390/jlpea11030032 - 17 Aug 2021
Abstract
This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the
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This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.
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(This article belongs to the Special Issue Hardware for Machine Learning)
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Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback
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, , , , , and
J. Low Power Electron. Appl. 2021, 11(3), 31; https://doi.org/10.3390/jlpea11030031 - 26 Jul 2021
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An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents
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An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 10.6 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.
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A New VCII Application: Sinusoidal Oscillators
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, , , , , , and
J. Low Power Electron. Appl. 2021, 11(3), 30; https://doi.org/10.3390/jlpea11030030 - 08 Jul 2021
Abstract
The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative
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The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII−). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII−. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
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Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks
J. Low Power Electron. Appl. 2021, 11(3), 29; https://doi.org/10.3390/jlpea11030029 - 06 Jul 2021
Abstract
Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized
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Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.
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(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Open AccessArticle
Dynamic Compilation for Transprecision Applications on Heterogeneous Platform
J. Low Power Electron. Appl. 2021, 11(3), 28; https://doi.org/10.3390/jlpea11030028 - 29 Jun 2021
Abstract
This article describes a software environment called HybroGen, which helps to experiment binary code generation at run time. As computing architectures are getting more complex, the application performance is becoming data-dependent. The proposed experimental platform is helpful in programming applications that can
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This article describes a software environment called HybroGen, which helps to experiment binary code generation at run time. As computing architectures are getting more complex, the application performance is becoming data-dependent. The proposed experimental platform is helpful in programming applications that can be reconfigured at run time in order to be adapted for a new data environment. The HybroGen platform is adapted to heterogeneous architectures and can generate instructions for different targets. This platform allows to go farther than classical JIT compilation in many directions: the code generator is smaller by three orders of magnitude and faster by three orders of magnitude, compared to JIT (Just-In-Time) platforms, and allows making code transformation that is impossible in traditional compilation schemes, such as code generation for non von Neumann accelerators or dynamic code transformations for transprecision. The latter is illustrated in a code example: the square root with Newton’s algorithm. We also illustrate the proposed HybroGen platform with two other examples: a multiplication with a specialization on a value determined at run time, and a conversion of degrees Celsius to degrees Fahrenheit. This article presents a proof of concept of the proposed HybroGen platform in terms of its functionalities, and demonstrates the working status.
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(This article belongs to the Special Issue Advances in Programming Parallel and Heterogeneous Computing for Cyber-Physical Systems)
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Open AccessArticle
A 1.02 μW Autarkic Threshold-Based Sensing and Energy Harvesting Interface Using a Single Piezoelectric Element
J. Low Power Electron. Appl. 2021, 11(2), 27; https://doi.org/10.3390/jlpea11020027 - 04 Jun 2021
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A self-powered piezoelectric sensor interface employing part of the signal that is not intended for measurement to sustain its autonomous operation was designed using XH018 (180 nm) technology. The aim of the proposed circuit, besides the energy self-sufficiency of the sensor, is to
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A self-powered piezoelectric sensor interface employing part of the signal that is not intended for measurement to sustain its autonomous operation was designed using XH018 (180 nm) technology. The aim of the proposed circuit, besides the energy self-sufficiency of the sensor, is to provide an interface that eliminates the effect of the harvesting process on the piezoelectric output signal which contains context data. This is achieved by isolating part of the signal that is desirable for sensing from the harvesting process so that the former is not affected or distorted by the latter. Moreover, the circuit manages to self-start its operation, so no additional battery or pre-charged capacitor is needed. The circuit achieves a very low power consumption of 1.02 μW. As a proof of concept, the proposed interfacing circuit is implemented in order to be potentially used for weigh-in-motion applications.
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Open AccessArticle
Design of Low-Voltage FO-[PD] Controller for Motion Systems
J. Low Power Electron. Appl. 2021, 11(2), 26; https://doi.org/10.3390/jlpea11020026 - 31 May 2021
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Fractional-order controllers have gained significant research interest in various practical applications due to the additional degrees of freedom offered in their tuning process. The main contribution of this work is the analog implementation, for the first time in the literature, of a fractional-order
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Fractional-order controllers have gained significant research interest in various practical applications due to the additional degrees of freedom offered in their tuning process. The main contribution of this work is the analog implementation, for the first time in the literature, of a fractional-order controller with a transfer function that is not directly constructed from terms of the fractional-order Laplacian operator. This is achieved using Padé approximation, and the resulting integer-order transfer function is implemented using operational transconductance amplifiers as active elements. Post-layout simulation results verify the validity of the introduced procedure.
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Open AccessArticle
PageRank Implemented with the MPI Paradigm Running on a Many-Core Neuromorphic Platform
J. Low Power Electron. Appl. 2021, 11(2), 25; https://doi.org/10.3390/jlpea11020025 - 28 May 2021
Abstract
SpiNNaker is a neuromorphic hardware platform, especially designed for the simulation of Spiking Neural Networks (SNNs). To this end, the platform features massively parallel computation and an efficient communication infrastructure based on the transmission of small packets. The effectiveness of SpiNNaker in the
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SpiNNaker is a neuromorphic hardware platform, especially designed for the simulation of Spiking Neural Networks (SNNs). To this end, the platform features massively parallel computation and an efficient communication infrastructure based on the transmission of small packets. The effectiveness of SpiNNaker in the parallel execution of the PageRank (PR) algorithm has been tested by the realization of a custom SNN implementation. In this work, we propose a PageRank implementation fully realized with the MPI programming paradigm ported to the SpiNNaker platform. We compare the scalability of the proposed program with the equivalent SNN implementation, and we leverage the characteristics of the PageRank algorithm to benchmark our implementation of MPI on SpiNNaker when faced with massive communication requirements. Experimental results show that the algorithm exhibits favorable scaling for a mid-sized execution context, while highlighting that the performance of MPI-PageRank on SpiNNaker is bounded by memory size and speed limitations on the current version of the hardware.
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(This article belongs to the Special Issue Advances in Programming Parallel and Heterogeneous Computing for Cyber-Physical Systems)
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Efficient ROS-Compliant CPU-iGPU Communication on Embedded Platforms
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, , , , and
J. Low Power Electron. Appl. 2021, 11(2), 24; https://doi.org/10.3390/jlpea11020024 - 26 May 2021
Abstract
Many modern programmable embedded devices contain CPUs and a GPU that share the same system memory on a single die. Such a unified memory architecture (UMA) allows programmers to implement different communication models between CPU and the integrated GPU (iGPU). Although the simpler
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Many modern programmable embedded devices contain CPUs and a GPU that share the same system memory on a single die. Such a unified memory architecture (UMA) allows programmers to implement different communication models between CPU and the integrated GPU (iGPU). Although the simpler model guarantees implicit synchronization at the cost of performance, the more advanced model allows, through the zero-copy paradigm, the explicit data copying between CPU and iGPU to be eliminated with the benefit of significantly improving performance and energy savings. On the other hand, the robot operating system (ROS) has become a de-facto reference standard for developing robotic applications. It allows for application re-use and the easy integration of software blocks in complex cyber-physical systems. Although ROS compliance is strongly required for SW portability and reuse, it can lead to performance loss and elude the benefits of the zero-copy communication. In this article we present efficient techniques to implement CPU–iGPU communication by guaranteeing compliance to the ROS standard. We show how key features of each communication model are maintained and the corresponding overhead involved by the ROS compliancy.
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(This article belongs to the Special Issue Advances in Programming Parallel and Heterogeneous Computing for Cyber-Physical Systems)
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A Review of Algorithms and Hardware Implementations for Spiking Neural Networks
J. Low Power Electron. Appl. 2021, 11(2), 23; https://doi.org/10.3390/jlpea11020023 - 24 May 2021
Abstract
Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of
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Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.
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(This article belongs to the Special Issue Artificial Intelligence of Things (AIoT))
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An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement
J. Low Power Electron. Appl. 2021, 11(2), 22; https://doi.org/10.3390/jlpea11020022 - 20 May 2021
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Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel
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Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.
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Open AccessArticle
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads
J. Low Power Electron. Appl. 2021, 11(2), 21; https://doi.org/10.3390/jlpea11020021 - 12 May 2021
Cited by 1
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In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling
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In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.
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Open AccessArticle
Accelerating Population Count with a Hardware Co-Processor for MicroBlaze
J. Low Power Electron. Appl. 2021, 11(2), 20; https://doi.org/10.3390/jlpea11020020 - 24 Apr 2021
Abstract
This paper proposes a Field-Programmable Gate Array (FPGA)-based hardware accelerator for assisting the embedded MicroBlaze soft-core processor in calculating population count. The population count is frequently required to be executed in cyber-physical systems and can be applied to large data sets, such as
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This paper proposes a Field-Programmable Gate Array (FPGA)-based hardware accelerator for assisting the embedded MicroBlaze soft-core processor in calculating population count. The population count is frequently required to be executed in cyber-physical systems and can be applied to large data sets, such as in the case of molecular similarity search in cheminformatics, or assisting with computations performed by binarized neural networks. The MicroBlaze instruction set architecture (ISA) does not support this operation natively, so the count has to be realized as either a sequence of native instructions (in software) or in parallel in a dedicated hardware accelerator. Different hardware accelerator architectures are analyzed and compared to one another and to implementing the population count operation in MicroBlaze. The achieved experimental results with large vector lengths (up to 217) demonstrate that the best hardware accelerator with DMA (Direct Memory Access) is ~31 times faster than the best software version running on MicroBlaze. The proposed architectures are scalable and can easily be adjusted to both smaller and bigger input vector lengths. The entire system was implemented and tested on a Nexys-4 prototyping board containing a low-cost/low-power Artix-7 FPGA.
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(This article belongs to the Special Issue Advances in Programming Parallel and Heterogeneous Computing for Cyber-Physical Systems)
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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate
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, , , and
J. Low Power Electron. Appl. 2021, 11(2), 19; https://doi.org/10.3390/jlpea11020019 - 21 Apr 2021
Cited by 2
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In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA
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In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.
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Open AccessArticle
Low-Power Audio Keyword Spotting Using Tsetlin Machines
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, , , , , , and
J. Low Power Electron. Appl. 2021, 11(2), 18; https://doi.org/10.3390/jlpea11020018 - 09 Apr 2021
Abstract
The emergence of artificial intelligence (AI) driven keyword spotting (KWS) technologies has revolutionized human to machine interaction. Yet, the challenge of end-to-end energy efficiency, memory footprint and system complexity of current neural network (NN) powered AI-KWS pipelines has remained ever present. This paper
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The emergence of artificial intelligence (AI) driven keyword spotting (KWS) technologies has revolutionized human to machine interaction. Yet, the challenge of end-to-end energy efficiency, memory footprint and system complexity of current neural network (NN) powered AI-KWS pipelines has remained ever present. This paper evaluates KWS utilizing a learning automata powered machine learning algorithm called the Tsetlin Machine (TM). Through significant reduction in parameter requirements and choosing logic over arithmetic-based processing, the TM offers new opportunities for low-power KWS while maintaining high learning efficacy. In this paper, we explore a TM-based keyword spotting (KWS) pipeline to demonstrate low complexity with faster rate of convergence compared to NNs. Further, we investigate the scalability with increasing keywords and explore the potential for enabling low-power on-chip KWS.
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(This article belongs to the Special Issue Artificial Intelligence of Things (AIoT))
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Highly Adaptive Linear Actor-Critic for Lightweight Energy-Harvesting IoT Applications
J. Low Power Electron. Appl. 2021, 11(2), 17; https://doi.org/10.3390/jlpea11020017 - 08 Apr 2021
Abstract
Reinforcement learning (RL) has received much attention in recent years due to its adaptability to unpredictable events such as harvested energy and workload, especially in the context of edge computing for Internet-of-Things (IoT) nodes. Due to limited resources in IoT nodes, it is
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Reinforcement learning (RL) has received much attention in recent years due to its adaptability to unpredictable events such as harvested energy and workload, especially in the context of edge computing for Internet-of-Things (IoT) nodes. Due to limited resources in IoT nodes, it is difficult to achieve self-adaptability. This paper studies online reactivity issues of fixed learning rate in the linear actor-critic (LAC) algorithm for transmission duty-cycle control. We propose the LAC-AB algorithm that introduces into the LAC algorithm an adaptive learning rate called Adam for actor update to achieve better adaptability. We introduce a definition of “convergence” when quantitative analysis of convergence is performed. Simulation results using real-life one-year solar irradiance data indicate that, unlike the conventional setups of two decay rate of Adam, smaller such as 0.2–0.4 are suitable for power-failure-sensitive applications and 0.5–0.7 for latency-sensitive applications with . LAC-AB improves the time of reactivity by 68.5–88.1% in our application; it also fine-tunes the initial learning rate for the initial state and improves the time of fine-tuning by 78.2–84.3%, compared to the LAC. Besides, the number of power failures is drastically reduced to zero or a few occurrences over 300 simulations.
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(This article belongs to the Special Issue Artificial Intelligence of Things (AIoT))
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Open AccessReview
Internet of Things: A Review on Theory Based Impedance Matching Techniques for Energy Efficient RF Systems
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, , , , , and
J. Low Power Electron. Appl. 2021, 11(2), 16; https://doi.org/10.3390/jlpea11020016 - 31 Mar 2021
Abstract
Within an increasingly connected world, the exponential growth in the deployment of Internet of Things (IoT) applications presents a significant challenge in power and data transfer optimisation. Currently, the maximization of Radio Frequency (RF) system power gain depends on the design of efficient,
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Within an increasingly connected world, the exponential growth in the deployment of Internet of Things (IoT) applications presents a significant challenge in power and data transfer optimisation. Currently, the maximization of Radio Frequency (RF) system power gain depends on the design of efficient, commercial chips, and on the integration of these chips by using complex RF simulations to verify bespoke configurations. However, even if a standard 50 transmitter’s chip has an efficiency of 90%, the overall power efficiency of the RF system can be reduced by 10% if coupled with a standard antenna of 72 . Hence, it is necessary for scalable IoT networks to have optimal RF system design for every transceiver: for example, impedance mismatching between a transmitter’s antenna and chip leads to a significant reduction of the corresponding RF system’s overall power efficiency. This work presents a versatile design framework, based on well-known theoretical methods (i.e., transducer gain, power wave approach, transmission line theory), for the optimal design in terms of power delivered to a load of a typical RF system, which consists of an antenna, a matching network, a load (e.g., integrated circuit) and transmission lines which connect all these parts. The aim of this design framework is not only to reduce the computational effort needed for the design and prototyping of power efficient RF systems, but also to increase the accuracy of the analysis, based on the explanatory analysis within our design framework. Simulated and measured results verify the accuracy of this proposed design framework over a 0–4 GHz spectrum. Finally, a case study based on the design of an RF system for Bluetooth applications demonstrates the benefits of this RF design framework.
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(This article belongs to the Special Issue Artificial Intelligence of Things (AIoT))
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A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter
J. Low Power Electron. Appl. 2021, 11(2), 15; https://doi.org/10.3390/jlpea11020015 - 30 Mar 2021
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This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower
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This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.
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Open AccessArticle
Physical Computing: Unifying Real Number Computation to Enable Energy Efficient Computing
by
and
J. Low Power Electron. Appl. 2021, 11(2), 14; https://doi.org/10.3390/jlpea11020014 - 26 Mar 2021
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Physical computing unifies real value computing including analog, neuromorphic, optical, and quantum computing. Many real-valued techniques show improvements in energy efficiency, enable smaller area per computation, and potentially improve algorithm scaling. These physical computing techniques suffer from not having a strong computational theory
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Physical computing unifies real value computing including analog, neuromorphic, optical, and quantum computing. Many real-valued techniques show improvements in energy efficiency, enable smaller area per computation, and potentially improve algorithm scaling. These physical computing techniques suffer from not having a strong computational theory to guide application development in contrast to digital computation’s deep theoretical grounding in application development. We consider the possibility of a real-valued Turing machine model, the potential computational and algorithmic opportunities of these techniques, the implications for implementation applications, and the computational complexity space arising from this model. These techniques have shown promise in increasing energy efficiency, enabling smaller area per computation, and potentially improving algorithm scaling.
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Statically Analyzing the Energy Efficiency of Software Product Lines
J. Low Power Electron. Appl. 2021, 11(1), 13; https://doi.org/10.3390/jlpea11010013 - 23 Mar 2021
Abstract
Optimizing software to become (more) energy efficient is an important concern for the software industry. Although several techniques have been proposed to measure energy consumption within software engineering, little work has specifically addressed Software Product Lines (SPLs). SPLs are a widely used software
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Optimizing software to become (more) energy efficient is an important concern for the software industry. Although several techniques have been proposed to measure energy consumption within software engineering, little work has specifically addressed Software Product Lines (SPLs). SPLs are a widely used software development approach, where the core concept is to study the systematic development of products that can be deployed in a variable way, e.g., to include different features for different clients. The traditional approach for measuring energy consumption in SPLs is to generate and individually measure all products, which, given their large number, is impractical. We present a technique, implemented in a tool, to statically estimate the worst-case energy consumption for SPLs. The goal is to reason about energy consumption in all products of a SPL, without having to individually analyze each product. Our technique combines static analysis and worst-case prediction with energy consumption analysis, in order to analyze products in a feature-sensitive manner: a feature that is used in several products is analyzed only once, while the energy consumption is estimated once per product. This paper describes not only our previous work on worst-case prediction, for comprehensibility, but also a significant extension of such work. This extension has been realized in two different axis: firstly, we incorporated in our methodology a simulated annealing algorithm to improve our worst-case energy consumption estimation. Secondly, we evaluated our new approach in four real-world SPLs, containing a total of 99 software products. Our new results show that our technique is able to estimate the worst-case energy consumption with a mean error percentage of 17.3% and standard deviation of 11.2%.
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(This article belongs to the Special Issue Energy-Efficient Embedded Computing)
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Editors-in-Chief: Ching-Ming Lai, Yitao LiuDeadline: 20 June 2022
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Advanced Researches in Embedded Systems
Guest Editors: Nicu Bizon, Mihai OproescuDeadline: 15 October 2021
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Nano-Bio-Electronics
Guest Editors: Cristian Ravariu, Fei YuanDeadline: 31 October 2021
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Low-Power Hardware Security
Guest Editor: Luis Parrilla RoureDeadline: 15 November 2021
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Low Power Memory/Memristor Devices and Systems
Guest Editors: Alex Serb, Adnan MehonicDeadline: 30 November 2021




