A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

: A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop ﬁlter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with − 11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is − 84.43 dBc/Hz. The chip area of the PLL is 0.84 mm 2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.


Introduction
Phase-locked signal sources are a critical building block for millimeter-wave radio systems, since they provide a stable frequency and phase reference as a local oscillator (LO) [1][2][3][4][5]. A recent advance in CMOS technologies has enabled the implementation of low-power, low phase-noise integrated phase-locked loops (PLL) operating at millimeter-wave frequencies [6,7]. In [8], a V-band PLL was developed in 65 nm CMOS. In [9], a 40, 60, and 80 GHz bands PLL, using multi-mode LC-based injection-locked frequency divider (ILFD), is designed in 90-nm CMOS. A 64 GHz PLL for 16-QAM modulation is presented in [10]. An 81-86 GHz frequency synthesizer is demonstrated in [11]. In [12], a 60 GHz low power PLL is demonstrated in 65 nm CMOS.
The phase and frequency detection play a key role in the locking of the PLL. The two different circuits for phase and frequency detection consume more power as compared to a single phase-frequency detector (PFD), which operates for both phase and frequency detection.
A high-frequency synthesizer having a pure output signal with less output phase noise is required in wireless communication applications, specifically transceivers. The proposed V-Band PLL can be utilized for IEEE 802.11ad standard high data rate transceivers for carrier signal generation with low power consumption and less phase noise.
In this paper, we present a 65-67 GHz PLL based on a V-band voltage-controlled oscillator (VCO), a V-band injection-locked frequency divider (ILFD), and a novel phase-frequency detector (PFD), which is simpler and consumes less power than conventional ones. Section 2 describes the PLL architecture. The design details of the proposed PLL are explained in Section 3. The measured results are shown in Section 4. Figure 1 shows the block diagram of the proposed PLL. The VCO is in cross-coupled configuration and provides dual outputs: a V-band fundamental output at f 0 and an optional output at 2nd-order harmonic, 2f 0 . The divider chain consists of a V-band divide-by-two ILFD and six-stage current-mode logic (CML) dividers. The overall division ratio of the PLL is, thus, 1/128. Details of the PLL building blocks are described in the following section.  Figure 2a shows the schematic of the dual-output V-band VCO that was used in this work. M 1,2 are biased at V gs = V ds = 1.2 V, forming a cross-coupled pair with g m = 4.8 mS. The oscillation frequency is determined by the symmetrical inductor L 2 = 80 pH, the total capacitance at the drain of M 1,2 (25 fF) and the varactors C 1 and C 2 . The quality factor of L 2 is 18 at 70 GHz according to electromagnetic (EM) simulation. One of the differential outputs of the cross-coupled core drives the divide-by-two ILFD, and the other output is connected to probe pads for off-chip testing. The differential outputs at f 0 drive M 3,4 in push-push configuration, generating an optional VCO output at 2f 0 . L 1 and C 3 are optimized for the highest output power at 2f 0 . All of the transistors in Figure 2a have 1 µm of unit finger width. In the simulation, the VCO can be tuned from 69.5 GHz to 76 GHz, as seen in Figure 2b, while providing −5 dBm and −18 dBm of output power at f 0 and 2f 0 , respectively, while dissipating 28 mW.  Figure 3a shows the schematic of the divide-by-two ILFD. M 6,7 , together with the symmetric inductor L 3 and varactors C 5 and C 6 , form a cross-coupled pair where its oscillation frequency is centered at 1/2 f 0 . The VCO output at f 0 is injected to the cross-coupled pair through M 5 . According to the simulation, the ILFD achieves locking across the entire VCO tuning range from 69.5 GHz to 76 GHz, by properly biasing the varactor tuning voltage V tune , as shown in Figure 3b. Specifically, the locking range of the ILFD is 3.6 GHz and 7 GHz, when the injected power at f 0 is −12 dBm and 0 dBm, respectively. The designed ILFD consumes 24 mW.

CML Frequency Divider Chain
The frequency of the ILFD output is approximately 35 GHz, which is sufficiently low to drive static frequency dividers. The ILFD output is followed by a six-stage CML frequency divider chain, where the frequency of the final output is 500 MHz for phase comparison. Figure 4 shows the schematic of a single-stage CML frequency divider. To minimize the power consumption, the bias current and drain resistors are properly scaled for each stage. The designed CML frequency divider chain consumes 36 mW.  Figure 5 shows the different architectures of PFDs. The block diagram of conventional PFD is shown in Figure 5a, which is commonly used for phase and frequency error detection. The conventional PFD is comparing a low-frequency reference signal with divided VCO's output and controls the tuning voltage while sub-sampling PD, as shown in Figure 5b, samples the VCO's output directly with a high-frequency reference signal and detects only the phase error. If the reference V re f is on rising edges, it yields a rising edge on V up . Similarly, if the VCO output V vco is on rising edges, it yields a rising edge on V dn . If both outputs are high, both D-FFs are reset. Circuit schematic of D flip-flop (D-FF) in conventional PFD is shown in Figure 6, where high-speed CML D-FF is used for fast switching, low noise, and low power consumption [13,14]. In one such D-FF, 14 transistors are used. In an AND-gate as shown in Figure 7, five transistors are employed [15].    Figure 8b works similarly. The switches M 6 and M 14 are controlled by the input signals to pass or block the pulses, thus achieving dead-zone free condition. Figure 9 shows the difference between dead-zone free and dead-zone exist state. In Figure 9a, the ideal PFD works for all phase errors and controls the output voltages accordingly. The dead-zone exists state, as shown in Figure 9b, is clearly depicted that PFD is non-operative for a wide range of phase errors. The behavior of proposed PFD is shown in Figure 9c which shows the PFD is dead-zone free except for a phase error of 2π/15. To minimize glitches when both input signals are in the same state, feedback from V up to drain of M 3 and V dn to drain of M 11 are utilized, because, when both inputs are in-phase, then it directly grounds the output.   The proposed PFD uses 16 transistors, thus more area-efficient than the conventional one, where 33 transistors are necessary. The proposed PFD is potentially low-power, too, due to the lack of CML gates. In the simulation, the proposed PFD consumes 2.3 µW at a 500 MHz reference clock. Simulation confirms the functionality of the proposed PFD as a phase and frequency detector. In Figure 10, both input signals V re f and V vco are in-phase. It is seen that the proposed PFD exhibits smaller glitches than the conventional one due to feedback from V up to drain of M 3 and, similarly, for V dn to drain of M 11 . The active chip area, including PFD, CP, and LPF is 0.171 mm 2 .

Charge Pump (CP) and Loop Filter (LF)
The schematics of the charge pump (CP) and loop filter (LF) used for the presented PLL are shown in Figure 11. M 3 and M 2 switch the current formed by M 1 and M 4 . The LF is 2nd-order low-pass filter with 25.5 MHz of the loop bandwidth.

Layout Designing
The layout is designed using 65nm LP CMOS PDK. All of the transistors are used with a configuration of M2, M3, and M4 metals for the gate, source and drain respectively. The capacitors used for DC block and bypass are metal-insulator-metal (MIM) capacitor designed with OA metal layer for high-quality factor as compared to other PDK VNCAP, and NCAP capacitors. The inductors are designed for VCO and ILFD using the OA metal layer with 3 µm thickness and highest conductivity of 5.3 × 10 7 Siemens/m as compared to all other metal layers used in substrate configuration. The probing pads are designed while using the LB layer for signal line and metal M1 for the ground path not only for pads, but also for the whole layout ground. Figure 12 shows the stack information of substrate configuration.

Measured Results
The designed PLL is fabricated in 65 nm LP CMOS process. Figure 13 shows the chip photograph of the PLL. Its active die area is 0.37 mm 2 excluding pads. The fabricated PLL chip is tested using an on-wafer test setup. The PLL reference clock is provided by Keysight J-BERT N4903B. The PLL output is down-converted by a V-band sub-harmonic mixer, VDI WR15SHM, with a 30 GHz LO input. Figure 14 shows a close-in spectrum of the PLL output at f 0 = 66.05 GHz with 515 MHz of the reference clock. The measured phase noise of the PLL is −84.43 dBc/Hz and −100 dBc/Hz, at 1 MHz and 10 MHz offset frequencies, respectively, as shown in Figure 15.
The output power of the PLL is measured using a V-band power sensor, Keysight N8488A, and a power meter, Keysight N1914A. The PLL achieves locking from 65.15 GHz to 67.4 GHz with the output power greater than −11.6 dBm, as shown in Figure 16. The measured PLL output frequency is lower than the simulation by 6-7 GHz, and the discrepancy is attributed to inaccuracies in EM modeling of layout parasitics and process variations. The PLL chip consumes 88 mW from a single 1.4 V supply. The optional PLL output at 2f 0 was not tested due to the lack of spectrum and power testing capability at around 130 GHz. Table 1 compares the presented PLL with prior work. The PLL achieves an FoM 132.58 dBc/Hz. The locking range of the PLL can be improved with a capacitor bank based tuning network for a wider tuning range VCO and ILFD for better FoM. Table 2 compares the proposed PFD with prior work, where it is seen that the proposed PFD consumes relatively low power.

Conclusions
This paper presents a V-band PLL with a novel PFD circuit. A cross-coupled VCO has been used as an RF signal generator with dual-frequency outputs. The fundamental frequency output has been injected to ILFD for 2nd order division and to the RF output probing PAD. The ILFD has been implemented using cross-coupled topology in order to yield similar parasitic effects as VCO. A novel PFD was employed for its simplicity and low-power consumption. The PFD has been implemented with only four logic NOT gates in a combination of two controlled switches. This controlled switched technique reduces the glitches which improve the tuning voltage efficiency. The PLL is fabricated in a 65-nm LP CMOS process, and it achieves an FoM 132.58 dBc/Hz. The PLL measured output power is −11.6 dBm with a locking range of 65.15 GHz to 67.4 GHz and phase noise of −84.43 dBc/Hz at 1 MHz offset while consuming 88 mW DC power. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in high frequency transceiver circuits.