- Article
First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA
- Nicola Lusardi,
- Fabio Garzetti,
- Gabriele Fiumicelli,
- Mattia Morabito,
- Gabriele Bonanno,
- Enrico Ronconi,
- Andrea Costa and
- Angelo Geraci
Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped...