Managing Multi-Processor Systems-on-Chip (MPSoCs) is becoming increasingly complex as demands for advanced capabilities rise. This complexity is due to the involvement of more processing elements and resources, leading to a higher degree of heterogen...
Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance requirements and reduce power consumption when executing an applica...
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is...
Side-channel attacks remain a challenge to information flow control and security in mobile edge devices till this date. One such important security flaw could be exploited through temperature side-channel attacks, where heat dissipation and propagati...
Neural networks are the state-of-the-art solution to image-processing tasks. Some of these neural networks are relatively simple, but the popular convolutional neural networks (CNNs) can consist of hundreds of layers. Unfortunately, the excellent rec...
Real-time image processing and computer vision systems are now in the mainstream of technologies enabling applications for cyber-physical systems, Internet of Things, augmented reality, and Industry 4.0. These applications bring the need for Smart Ca...
As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target archite...
State-of-the-art mobile platforms, such as smartphones and tablets, are powered by heterogeneous system-on-chips (SoCs). These SoCs are composed of many processing elements, including multiple CPU core clusters (e.g., big.LITTLE cores), graphics proc...
To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this pap...
Cache attacks are widespread on microprocessors and multi-processor system-on-chips but have not yet spread to heterogeneous systems-on-chip such as SoC-FPGA that are found in increasing numbers of applications on servers or in the cloud. This type o...
The acquisition of digital images is susceptible to haze, and images captured under such adverse conditions may impact high-level applications designed for clean input data. Image dehazing emerges as a practical solution to this problem, as it can be...
In a multiprocessor System-on-Chip (SoC), efficient communication between the associated processors has to be addressed at all levels of the system design to guarantee global interconnection [...]
Modern power systems, particularly those integrating smart grid and microgrid functionalities, demand efficient high-speed data processing to manage increasingly complex operational requirements. In response to these challenges, this paper proposes a...
This paper presents a novel metascheduling algorithm to enhance communication efficiency in off-chip time-triggered multi-processor system-on-chip (MPSoC) platforms, particularly for safety-critical applications in aerospace and automotive domains. T...
Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of ve...
Despite the tremendous socioeconomic importance of supply chains (SCs), security officers and operators are faced with no easy and integrated way for protecting their critical, and interconnected, infrastructures from cyber-attacks. As a result, solu...
Iris recognition is currently considered the most promising biometric method and has been applied in many fields. Current commercial and research systems typically use software solutions running on a dedicated computer, whose power consumption, size...
Advanced, superscalar microprocessors (
Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) des...
6 September 2023
In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware...
A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complem...
Static schedules for systems can lead to an inefficient usage of the resources, because the system’s behavior cannot be adapted at runtime. To improve the runtime system performance in current time-triggered Multi-Processor System on Chip (MPSoC), a...
This paper addresses the problem of automatic quality inspection in assembly processes by discussing the design of a computer vision system realized by means of a heterogeneous multiprocessor system-on-chip. Such an approach was applied to a real cat...
With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially,...
A heterogeneous system-on-chip (SoC) integrates multiple types of processors on the same chip. It has great advantages in many aspects, such as processing capacity, size, weight, cost, power, and energy consumption, which result in it being widely ad...
The end of Dennard scaling led to the use of heterogeneous multi-processor systems-on-chip (MPSoCs). Heterogeneous MPSoCs provide a high efficiency in terms of energy and performance due to the fact that each processing element can be optimized for a...
Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design prob...
In recent years, as semiconductor manufacturing processes have been steadily scaled down, the transistor count fabricated on a single silicon die can reach up to a billion units. Therefore, current multiprocessor system-on-chips (MPSoCs) can include...
Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, w...
Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–softw...
In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cach...
This paper suggests an optimisation approach in heterogeneous computing systems to balance energy power consumption and efficiency. The work proposes a power measurement utility for a reinforcement learning (PMU-RL) algorithm to dynamically adjust th...
Double-precision general matrix multiplication (DGEMM) is an essential kernel for measuring the potential performance of an HPC platform. ARMv8-based system-on-chips (SoCs) have become the candidates for the next-generation HPC systems with their hig...
Field Programmable Gate Array (FPGA) accelerators have been widely adopted for artificial intelligence (AI) applications on edge devices (Edge-AI) utilizing Deep Neural Networks (DNN) architectures. FPGAs have gained their reputation due to the great...
Field-Programmable Gate Array System-on-Chip (FPGA-SoC) platforms are increasingly adopted in modern industrial Cyber-Physical Systems (CPSs), enabling real-time control, monitoring, and automation of critical industrial processes. The increasing int...
A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE SoCs currently commonly u...
One of the main challenges faced by iris recognition systems is to be able to work with people in motion, where the sensor is at an increasing distance (more than 1 m) from the person. The ultimate goal is to make the system less and less intrusive a...
With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing,...
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, su...
Benes/Clos networks constitute a particularly important part of interconnection networks and have been used in numerous areas, such as multi-processor systems, data centers and on-chip networks. They have also attracted great interest in the field of...
Autonomous plankton monitoring needs classifiers that run on low-power edge hardware and reject out-of-distribution (OOD) inputs. Our prior in situ plankton image biomass estimation (IsPlanktonBIO) framework identifies organisms by nearest-neighbour...
In the field of sparse signal reconstruction, sparse Bayesian learning (SBL) has excellent performance, which is accompanied by extremely high computational complexity. This paper presents an efficient SBL hardware and software (HW&SW) co-impleme...
Existing PLC security solutions face a fundamental conflict between stringent real-time requirements and robust protection: traditional IT security mechanisms (e.g., encryption, authentication) introduce unacceptable latency, while software-based red...
Electromyography (EMG) signals are fundamental in neurorehabilitation as they provide a non-invasive means of capturing the electrical activity of muscles, enabling precise detection of motor intentions. This capability is essential for controlling a...
This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture...
Correlation has a variety of applications that require signal processing. However, it is computationally intensive, and software correlators require high-performance processors for real-time data analysis. This is a challenge for embedded devices bec...
1 February 2012
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors...
The Network-on-Chip (NoC) paradigm emerged as a viable solution to provide an efficient and scalable communication backbone for next-generation Multiprocessor Systems-on-Chip. As the number of integrated cores keeps growing, alternatives to the tradi...
The power density of modern high-power integrated processors keeps rising rapidly. Among them, chiplet-based high-power AI accelerators exhibit local peak heat flux exceeding 1 kW/cm2, which leads to concentrated hotspots, severe internal temperature...
Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the core...
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