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J. Low Power Electron. Appl. 2017, 7(2), 8;

Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity

Department of Computing and Immersive Technologies, University of Northampton, Northampton NN2 7AL, UK
Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, China
School of Electrical & Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU, UK
Department of Electrical and Electronic Engineering, UCL, London WC1E 6BT, UK
Electronics and Computer Science, Faculty of Physical Sciences and Engineering, University of Southampton, Southampton SO17 1BJ, UK
Author to whom correspondence should be addressed.
Academic Editor: Davide Patti
Received: 30 January 2017 / Revised: 20 April 2017 / Accepted: 20 April 2017 / Published: 26 April 2017
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
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To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45 % (or 50 % ) in 3D NoCs (or WiNoCs). View Full-Text
Keywords: router architecture; 3D NoC; hybrid wired-wireless network-on-chip; surface wave; mm-wave; WiNoC; waveguide router architecture; 3D NoC; hybrid wired-wireless network-on-chip; surface wave; mm-wave; WiNoC; waveguide

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Opoku Agyeman, M.; Zong, W.; Yakovlev, A.; Tong, K.-F.; Mak, T. Extending the Performance of Hybrid NoCs beyond the Limitations of Network Heterogeneity. J. Low Power Electron. Appl. 2017, 7, 8.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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