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Open AccessArticle

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

1
Institut für Informations- und Kommunikationstechnik, Otto-von-Guericke-Universität Magdeburg, 39106 Magdeburg, Germany
2
Institute of Electrodynamics and Microelectronics, University of Bremen, 28359 Bremen, Germany
*
Author to whom correspondence should be addressed.
Technologies 2020, 8(1), 10; https://doi.org/10.3390/technologies8010010
Received: 26 November 2019 / Revised: 10 January 2020 / Accepted: 21 January 2020 / Published: 23 January 2020
(This article belongs to the Special Issue MOCAST 2019: Modern Circuits and Systems Technologies on Electronics)
Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well. View Full-Text
Keywords: Network-on-Chip; core mapping Network-on-Chip; core mapping
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Joseph, J.M.; Ermel, D.; Bamberg, L.; García-Oritz, A.; Pionteck, T. Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing. Technologies 2020, 8, 10.

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