A Novel FEC Implementation for VSAT Terminals Using High-Level Synthesis

Abstract

This paper presents a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture terminal (VSAT) satellite communication systems. The decoder is described in C++ and synthesized using the Xilinx Vitis high-level synthesis (HLS) 2025 (AMD Xilinx, San Jose, CA, USA) tool, and then packaged and integrated as an intellectual property (IP) core within the Vivado Design Suite 2024 (AMD Xilinx, San Jose, CA, USA), enabling rapid prototyping and portability across FPGA platforms. Unlike conventional normalized min-sum (NMS) and two-dimensional normalized min-sum (2D-NMS) architectures, the proposed 2D-CNMS scheme employs dyadic, multiplier-free normalization combined with two-level magnitude correction, achieving near sum-product performance with reduced complexity and latency. The design is implemented on a Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) (AMD Xilinx, San Jose, CA, USA) and supports real-time operation with a throughput of 29–41 Mbps at 100 MHz, while using only 9.6–22.4 k look-up tables (LUTs), 2.1–5.9 k flip-flops (FFs), and no digital signal processing (DSP) slices or block random-access memories (BRAMs). Bit-error-rate (BER) simulations over an additive white Gaussian noise (AWGN) channel show no error floor down to ${10}^{-8}$. These results demonstrate that the proposed HLS-based 2D-CNMS IP core provides a resource-efficient, high-performance LDPC decoding solution as compared with existing LDPC implementation approaches. This LDPC solution targets performance enhancement in wireless communication systems and has been deployed on a multi-frequency time-division multiple-access (MF-TDMA) satellite link to assess its overall behavior, demonstrating improved performance with reduced resource usage.

1. Introduction

Hubless full-mesh very small aperture terminal (VSAT) communication systems are increasingly adopted in satellite networks for their resilience against single points of failure, support for direct VSAT-to-VSAT connectivity, and enhanced security through private network isolation [1]. Unlike traditional star-configured VSAT architectures that rely on a central hub, hubless full-mesh systems eliminate hub dependency and enable direct remote-to-remote communication, which is critical for modern satellite applications, such as broadband connectivity, Internet of Things (IoT) backhaul, and emergency communications. Reliable satellite communication requires robust forward error correction (FEC) to mitigate noisy channel conditions and maintain data integrity. Conventional FEC schemes such as turbo product codes (TPCs) [2], convolutional codes [3,4,5,6], and Reed–Solomon (RS) codes [3,4,7] have been widely deployed. However, low-density parity-check (LDPC) codes, and particularly quasi-cyclic LDPC (QC-LDPC) codes, have gained prominence due to their superior error-correction capability and hardware efficiency. QC-LDPC codes exploit structural regularity in the parity-check matrix, reducing memory and interconnect complexity while achieving near-optimal performance [8]. These advantages have led to their adoption in modern standards such as digital video broadcasting-satellite, second-generation (DVB-S2) [3], IEEE 802.11n (WiFi) [9], and fifth-generation (5G) new radio (NR) [10]. The sum-product (SP) algorithm, also known as belief propagation (BP) [11], remains the performance benchmark for LDPC decoding [12], but its probability-domain arithmetic is computationally expensive for resource-constrained field-programmable gate arrays (FPGAs). Simplified variants such as min-sum (MS) [13,14] and normalized min-sum (NMS) reduce complexity by replacing multiplications with add-compare-select operations, albeit at the cost of some coding gain. Further refinements, including second-minimum approximation min-sum (SAMS) [15], two-dimensional min-sum (2D-MS) [16], and two-dimensional normalized min-sum (2D-NMS) [11], improve accuracy with modest overhead. Traditional register-transfer-level (RTL)-based implementations of LDPC decoders are time-consuming, error-prone, and difficult to scale across evolving FPGA platforms. High-level synthesis (HLS) offers a modern design methodology that accelerates development, improves portability, and enables rapid design-space exploration without sacrificing hardware efficiency. For FPGA targets such as VSATPlus^®, decoder micro-architecture strongly impacts throughput, latency, and power. Fully parallel layered designs achieve high per-iteration throughput but incur dense interconnect and tight timing closure [17]. Partially parallel designs reduce wiring and power at the cost of lower throughput [18], while pipelined block-serial decoders minimize area but increase latency [19]. Scheduling also influences convergence and memory organization: flooding requires more iterations and higher energy, whereas layered scheduling reduces iterations but demands careful memory banking [20,21]. Despite these advances, existing FPGA implementations struggle to balance error-correction performance, resource utilization, and power efficiency under stringent constraints typical of satellite systems. This gap motivates the need for an approach that combines algorithmic improvements with a scalable, hardware-aware design methodology leveraging HLS. To address this challenge, this work proposes a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder integrated into an HLS-based design flow for generating reusable LDPC intellectual property (IP) cores. The proposed architecture incorporates dyadic, multiplier-free normalization and dual scaling of the first and second minima, achieving near-SP performance while minimizing resource usage and power consumption.

The main contributions of this paper are as follows: (1) a hardware-aware LDPC decoder architecture based on the 2D-CNMS algorithm optimized for FPGA implementation; (2) an HLS-based design flow for generating reusable LDPC IP cores, reducing development complexity compared with traditional RTL approaches; and (3) comprehensive evaluation of post-implementation error-correction performance, resource utilization, and throughput under realistic satellite channel conditions. The remainder of this paper is organized as follows: Section 2 describes the VSATPlus system and its architectural constraints. Section 3 and Section 4 present the proposed LDPC decoder and algorithmic enhancements. Section 5 details the FPGA-oriented architecture. Section 7 reports simulation results and analyzes complexity-performance trade-offs. Finally, Section 8 concludes the paper and outlines future research directions.

2. VSATPlus^® System Overview

The VSATPlus [22] system provides full-mesh, single-hop connectivity within a satellite network, leveraging multi-frequency time division multiple access (MF-TDMA) technology. Each terminal buffers user data and transmits it in short, high-speed bursts scheduled to avoid overlap, ensuring efficient satellite resource utilization without requiring a central hub for scheduling [23]. This hubless architecture supports diverse satellite applications, including broadband connectivity, IoT backhaul, emergency communications, and enterprise networking, where reliability and scalability are critical [23].

Figure 1 illustrates one example of VSATPlus deployment in air traffic control (ATC), showing direct Internet protocol (IP) connectivity between area control centers (ACCs) and airports across regions. The system supports radar, very high frequency (VHF) radio, automatic dependent surveillance-broadcast (ADS-B), and essential ATC services such as messaging, weather updates, and air traffic coordination. Similar principles apply to other mission-critical satellite services requiring secure, low-latency communication.

The VSATPlus modem is highly agile, capable of varying multiple parameters burst-by-burst. This flexibility enables carrier-to-carrier hopping for both transmit and receive over 32 carriers, along with adaptive modulation and FEC changes. This capability, referred to as Mesh-adaptive coding and modulation (ACM)^TM, dynamically adjusts modulation and coding to accommodate different terminal antenna sizes and varying channel conditions across the network, optimizing throughput and reliability [23].

Figure 2 shows the architecture of a VSATPlus full-mesh, hubless network employing Ku-band and C-band satellite links for high-throughput communication. The satellite facilitates signal transmission from ground stations operating on both frequency bands, enabling simultaneous multi-band connectivity. The network consists of six nodes ($A_1$ to $A_6$), interconnected in a full-mesh topology to ensure direct, bidirectional communication between all nodes. The labels (e.g., primary, secondary) indicate the logical roles or hierarchy of the nodes, while the consistent inter-node links. This architecture demonstrates the robustness and scalability of VSATPlus for distributed satellite applications beyond ATC, including broadband and enterprise networking.

3. Decoding Algorithmic Principles

QC-LDPC codes apply parity-check matrices tiled by $Z\times Z$ sub-matrices that are either circulant permutations of the identity or zeros [24]. This regular structure yields compact representations and lower memory requirements while enabling highly parallel, hardware-efficient decoders, an attractive performance/complexity trade-off for high-throughput satellite links. In satellite communication systems, where long propagation delays and limited link budgets make re-transmissions costly, efficient LDPC decoding is essential to maintain reliability and throughput. Although QC-LDPC codes may be degree-irregular (row and column weights $(d_c,d_v)$ can vary), the locations of ones in H are deterministically specified by the permutation matrix and its circulant shifts, producing predictable, conflict-free access patterns rather than random placement [25]. Furthermore, the QC form organizes H as a regular array of blocks, with Z distinct memory banks for variable node data, enabling block-wise schedules that achieve scalable parallelism. A compressed permutation matrix, illustrated in Table 1, stores only shift offsets, where dash marks a zero block and non-negative entries specify the cyclic shift of the identity, minimizing footprint and simplifying decoder configuration. Owing to these advantages, QC-LDPC codes are widely adopted in modern communication standards.

The decoding of QC-LDPC codes typically employs SP algorithms, broadly classified by the type of message information exchanged during iterations. Hard-decision decoders, such as the bit-flipping (BF) algorithm, operate on binary decisions extracted directly from the channel [26], whereas soft-decision techniques, including the SP algorithm and its simplified MS variant, exploit soft information in the form of log-likelihood ratios (LLRs) [13,27]. These iterative message-passing algorithms exchange extrinsic information between variable nodes (VNs) and check nodes (CNs) over a bipartite graph representation of the parity-check matrix H, known as a Tanner graph [28], which underpins the inference mechanism that progressively refines the reliability of decoded bits across iterations.

The structure of the LDPC parity-check matrix H used in this work is derived from the IEEE 802.16e (WiMAX) standard [29]. The matrix is constructed from a permutation matrix, shown in Table 1, composed of integer shift values and null entries, expanded by a lifting factor Z. The resulting H matrix is sparse and quasi-cyclic, as illustrated in Figure 3. Each diagonal or off-diagonal band in the figure corresponds to a circulant permutation matrix. Their distribution reflects the structured connectivity of VNs (columns) and CNs (rows).

Table 1. Permutation matrix of QC-LDPC code with $\mathrm{R}=2/3$ [30].

37	-	-	32	19	27	30	-	4	-	-	-	-	-	21	33	0	0	-	-	-	-	-	-
36	-	35	-	20	22	-	1	-	13	-	39	-	-	39	-	-	0	0	-	-	-	-	-
-	-	-	-	-	-	-	20	17	18	18	29	7	1	22	-	-	-	0	0	-	-	-	-
-	17	32	-	-	16	28	-	26	-	-	10	-	20	-	7	-	-	-	0	0	-	-	-
5	12	-	7	29	11	-	-	-	-	12	11	30	-	-	-	0	-	-	-	0	0	-	-
-	-	6	23	-	-	4	14	37	-	-	-	-	35	2	26	-	-	-	-	-	0	0	-
27	2	27	-	6	-	19	-	-	36	33	-	22	-	-	-	-	-	-	-	-	-	0	0
-	38	-	7	-	-	-	33	-	21	14	-	33	15	-	25	0	-	-	-	-	-	-	0

Table 1. Permutation matrix of QC-LDPC code with $\mathrm{R}=2/3$ [30].

37	-	-	32	19	27	30	-	4	-	-	-	-	-	21	33	0	0	-	-	-	-	-	-
36	-	35	-	20	22	-	1	-	13	-	39	-	-	39	-	-	0	0	-	-	-	-	-
-	-	-	-	-	-	-	20	17	18	18	29	7	1	22	-	-	-	0	0	-	-	-	-
-	17	32	-	-	16	28	-	26	-	-	10	-	20	-	7	-	-	-	0	0	-	-	-
5	12	-	7	29	11	-	-	-	-	12	11	30	-	-	-	0	-	-	-	0	0	-	-
-	-	6	23	-	-	4	14	37	-	-	-	-	35	2	26	-	-	-	-	-	0	0	-
27	2	27	-	6	-	19	-	-	36	33	-	22	-	-	-	-	-	-	-	-	-	0	0
-	38	-	7	-	-	-	33	-	21	14	-	33	15	-	25	0	-	-	-	-	-	-	0

3.1. Sum-Product (SP)/Belief Propagation (BP)

The SP/BP decoding algorithm initiates by calculating the LLRs for each received channel symbol $r_i$ at time i under an additive white Gaussian noise (AWGN) channel model, as follows:

$$LL{R}_i=log{\displaystyle \frac{Pr\left(r_i\right|t_i=1)}{Pr\left(r_i\right|t_i=-1)}}={\displaystyle \frac{2r_i}{{\sigma }^2/2}}$$

(1)

where ${\sigma }^2$ is the channel noise power following the Gaussian distribution. Initially, messages passed from the variable node v to the connected check node c are set to the LLR value derived from the received symbol, as given by

$$L_{v\to c}=\sum _{c^{\prime }\in \mathcal{M}\left(v\right)\setminus c}{L}_{c^{\prime }\to v}$$

(2)

where $c^{\prime }\in \mathcal{M}\left(v\right)\setminus c$ represents the set of check nodes connected to the variable node v, excluding c. Next, the check node information is updated as follows:

$$L_{c\to v}^{(\ell )}=2{tanh}^{-1}(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}tanh{\displaystyle \frac{L_{v^{\prime }\to c}^{(\ell -1)}}{2}})$$

(3)

Once the convergence condition is satisfied or the maximum number of iterations is reached, the operation terminates. Subsequently, the hard decision for each variable node, v, is computed based on its LLR, as follows:

$$L_v=LLR+\sum _{c^{\prime }\in \mathcal{M}\left(v\right)}{L}_{c^{\prime }\to v}$$

(4)

If $L_v\ge 0$, then the estimated transmitted bit value is 0; otherwise, it is considered as 1.

3.2. Min-Sum (MS)

While SP achieves excellent error-correction performance, its reliance on nonlinear functions and probability-domain operations results in high computational complexity, motivating the development of simplified algorithms such as MS. The MS decoding algorithm simplifies the computational complexity of the SP algorithm by replacing nonlinear hyperbolic tangent functions with a minimum operation. Thus, the check node update equation simplifies to

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(5)

The variable nodes update, and hard decision processes remain consistent with the SP algorithm.

3.3. Normalized Min-Sum (NMS)

Although the MS significantly reduces hardware resource requirements and processing latency compared with the SP algorithm, it experiences degradation in bit-error-rate (BER) performance, typically around 0.5–1 dB [26]. This degradation primarily results from overestimation in extrinsic information exchange between nodes. To mitigate this effect, NMS applies a scaling factor, $\beta \in (0,1)$, to correct extrinsic information estimates, thereby enhancing practical decoding performance [31], as follows:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\beta \underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(6)

Whereas NMS attenuates the check-node minima by multiplying the raw minimum magnitude by a constant $0<\beta <1$, offset min-sum (OMS) instead applies a fixed subtraction to correct for the systematic overestimation introduced by the plain min-sum rule [32]. In OMS, each check-to-variable message is computed as

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)max\left[\left(\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|L_{v^{\prime }\to c}^{(\ell -1)}\right|\right)-\eta ,0\right]$$

(7)

where $\eta >0$ is the offset parameter chosen to minimize the performance loss relative to the full belief-propagation algorithm [32]. Because the offset operation requires only a single subtraction per edge rather than a multiplication, OMS offers reduced critical-path latency and lower hardware resource usage compared with NMS.

3.4. Two-Dimensional Normalized Min-Sum (2D-NMS)

In the standard NMS algorithm, a single constant scaling factor compensates the overestimated magnitudes of all incoming check-to-variable messages. However, the extrinsic magnitude sent to a VN equals the smallest incoming magnitude, ${min}_1$, for all edges except the edge, which uses the second-smallest incoming magnitude, ${min}_2$, due to edge exclusion. Consequently, applying one scale for both cases can miscalibrate some messages and degrade performance. The 2D-NMS addresses this by applying distinct scaling (${\beta }_1,{\beta }_2$), conditioned on whether ${min}_1$ or ${min}_2$ is used, yielding more accurate LLRs with only modest added complexity [33], as follows:

$$L_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\times \left\{\begin{array}{c}{\beta }_2\times \underset{2}{min}\hfill \\ {\beta }_1\times \underset{1}{min}\hfill \end{array}\right.$$

(8)

For LDPC decoders employing the 2D-NMS algorithm, the optimal normalization factors (${\beta }_1,{\beta }_2$) are predominantly determined by the check node degree ($d_c$), which is determined by the parity check matrix.

3.5. Two-Dimensional Min-Sum (2D-MS)

While 2D-NMS compensates the check-node magnitude bias via the scaling pair (${\beta }_1,{\beta }_2$), it applies the same gain to both message flows. Density-evolution analysis in [16] shows that the residual bias on the variable-to-check stream differs statistically from that on the check-to-variable stream. Therefore, introducing a second, direction-specific scaling pair eliminates this asymmetry and closes the remaining gap to SP decoding with only two extra multiplications per edge. To address this residual asymmetry more effectively, ref. [16] proposes applying iteration-dependent scale factors (${\alpha }^{(\ell )},{\beta }^{(\ell )}$) directly to the extrinsic LLRs on each edge, resulting in

$${\tilde{L}}_{v\to c}^{(\ell )}={\alpha }^{(\ell )}{L}_{v\to c}^{(\ell )}$$

(9)

while the corresponding check-to-variable updates is as follows:

$${\tilde{L}}_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left({\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right)\right){\beta }^{(\ell )}\underset{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}{min}\left|{\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right|$$

(10)

Although (${\alpha }^{(\ell )},{\beta }^{(\ell )}$) can be optimized adaptively based on the code structure and channel SNR, [16] demonstrates that exhaustive AWGN profiling across the operational $E_b/N_0$ range yields two fixed scale factors that preserve virtually all of the SP decoder’s extrinsic-information fidelity.

4. Two-Dimensional Corrected Normalized Min-Sum (2D-CNMS)

For VSATPlus terminals, even modest coding-gain improvements translate into reduced power-amplifier back-off and increased fade margins. However, the SP decoding algorithm remains computationally impractical for the throughput and power envelopes of the target FPGA platforms. Building on [16,33], we propose a 2D-CNMS decoder that preserves the add-compare-select arithmetic of MS while recovering a substantial fraction of the residual gap to an SP algorithm. The update introduces two shift-based per-edge scaling per iteration and incurs no additional on-chip memory, thereby maintaining low architectural complexity. Therefore, the scaled variable-to-check update is defined as

$${\tilde{L}}_{v\to c}^{(\ell )}=\overline{\alpha }{L}_{v\to c}^{(\ell )}$$

(11)

while the scaled check-to-variable update is given by

$${\tilde{L}}_{c\to v}^{(\ell )}=\left(\prod _{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left({\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}\right)\right)\times \left\{\begin{array}{c}\overline{{\beta }_2}\times \underset{2}{min}\hfill \\ \overline{{\beta }_1}\times \underset{1}{min}\hfill \end{array}\right.$$

(12)

Similar to a 2D-NMS algorithm, ${min}_1$ and ${min}_2$ denote the smallest and second-smallest absolute values of the incoming messages $|{\tilde{L}}_{v^{\prime }\to c}^{(\ell -1)}|$, where $v^{\prime }\in \mathcal{N}\left(c\right)\setminus v$.

5. 2D-CNMS Hardware Implementation

Hand-optimized RTL design has traditionally been the standard approach for FPGA-based LDPC decoders. However, HLS methodologies [34] and commercial toolchains such as Vitis high-level synthesis (HLS) 2025 (AMD Xilinx, San Jose, CA, USA) [35] now offer a more productive alternative by enabling designers to specify the decoder in C/C++ or SystemC and automatically generate synthesizable RTL. In practice, HLS significantly reduces design and verification effort [36], while achieving area, timing, and power results comparable to expert-tuned hardware description language (HDL) implementations [36]. Furthermore, a single high-level source is portable across FPGA families and integrates seamlessly with the VSATPlus C-based simulation environment, facilitating rapid design-space exploration and system-level validation. Algorithm 1 summarizes the layered scheduling strategy employed in the proposed 2D-CNMS decoder. Compared with conventional layered MS, the proposed approach introduces a uniform variable-to-check scaling factor, $\overline{\alpha }$, and a two-level check-to-variable scaling pair (${\overline{\beta }}_1,{\overline{\beta }}_2$), conditioned on whether the outgoing message is derived from ${min}_1$ or ${min}_2$. These refinements improve extrinsic information accuracy while preserving the low-complexity arithmetic of MS.

Algorithm 1 Layered 2D-CNMS QC-LDPC Decoder

1: Kernel 1: Initialization   2: # Pipeline directive   3: Load ${\mathrm{LLR}}_v^{\mathrm{ch}}$ into VN accumulator memory   4: Initialize message memory   5: Kernel 2: Process Decoding Iterations   6: while $i=1:{\mathrm{Itr}}_{max}$ do   7:          Kernel 2.1: Compute VN Incoming Messages   8:          for $h=1$ : $M/Z$ do   9:                   # Pipeline directive 10:                   for all check-nodes c in layer h do 11:                            Load $L_{v\to c}^{\left(i\right)}:v\in \mathcal{N}\left(c\right)$ from VN–message RAM 12:                            for all $v\in \mathcal{N}\left(c\right)$ do 13:                                     # Unroll directive 14:                                     $\mathrm{sign}\left(L_{c\to v}^{\left(i\right)}\right)={\prod }_{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v}\mathrm{sign}\left(L_{v^{\prime }\to c}^{(i-1)}\right)$  15:                                     $$\begin{gathered} |L_{c\to v}^{\left(i\right)}|=\left\{\begin{array}{c}{\overline{\beta }}_1\times {min}_{1\{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v\}}|L_{v^{\prime }\to c}^{(i-1)}| \\ {\overline{\beta }}_2\times {min}_{2\{v^{\prime }\in \mathcal{N}\left(c\right)\setminus v\}}\left|L_{v^{\prime }\to c}^{(i-1)}\right|\hfill \end{array}\right. \end{gathered}$$ 16:                                     Write $L_{c\to v}^{\left(i\right)}$ to CN–message RAM 17:                            end for 18:                   end for 19:          end for 20:          Kernel 2.2: Generate VN Output Messages 21:          for $u=1$ : $N/Z$ do 22:                   # Pipeline directive 23:                   for all variable-node v in layer u do 24:                            Load $L_{c\to v}^{\left(i\right)}:c\in \mathcal{M}\left(v\right)$ from CN–message RAM 25:                            for all $c\in \mathcal{M}\left(v\right)$ do 26:                                     # Unroll directive 27:                                     $L_{v\to c}^{\left(i\right)}=L_v^{(i-1)}+\overline{\alpha }{\sum }_{c^{\prime }\in \mathcal{M}\left(v\right)\setminus c}{L}_{c^{\prime }\to v}^{(i-1)}$ 28:                                     Write $L_{v\to c}^{\left(i\right)}$ to VN–message RAM 29:                            end for 30:                   end for 31:          end for 32: end while 33: Kernel 3: Compute VNs Hard Decision 34: for all $v=1:N$ do 35:          # Pipeline directive 36:           ${\widehat{c}}_v\leftarrow 0\mathrm{if}{L}_v^{\left(i\right)}<0\mathrm{else}1$ 37: end for 38: return Decoded Word, ${\widehat{c}}_v$

The proposed decoder is implemented using Vitis HLS 2025, leveraging loop-level parallelism and pipelining to maximize throughput. Inner loops responsible for CN and VN updates are partially or fully unrolled to generate multiple CN→VN and VN→CN messages per cycle, while outer loops are pipelined to minimize the initiation interval (II), enabling iteration overlap and reducing latency. The inherent layered structure of QC-LDPC codes facilitates deterministic memory banking and partitioning across Z independent memory banks implemented using distributed RAM and registers, supporting concurrent read-modify-write operations aligned with layer boundaries. Address generation is performed using two read-only memory (ROM)-based look-up tables (LUTs) precomputed from the base matrix: $\mathcal{N}\left(c\right)$ for CN updates and $\mathcal{M}\left(v\right)$ for VN updates. These index tables enable constant-time routing without additional buffering or pointer chasing, ensuring efficient memory access.

The HLS-based 2D-CNMS decoder architecture, illustrated in Figure 4, comprises two fully parallel processing engines: one dedicated to CN message computation and the other to VN message computation. Each engine interfaces directly with distributed random access memory (RAM) and registers under the control of a compact ROM storing non-negative cyclic-shift offsets and connection degrees derived from the base matrix.

In the CN engine, which comprises $M/Z$ parallel pipelines, each pipeline retrieves a Z-wide vector of extrinsic LLRs from the VN RAM, applies a fixed-depth tree of four-input comparators to identify the smallest and second-smallest magnitudes, determines the overall output sign through a single XOR reduction stage, and adjusts these minima using normalization factors (${\overline{\beta }}_1,{\overline{\beta }}_2$). The normalized extrinsic messages are then written back to the CN-RAM via the dual-port interface. Similarly, the VN engine, consisting of $N/Z$ parallel pipelines, reads the updated CN messages along with the original channel LLRs, accumulates them using an adder tree, subtracts each corresponding extrinsic to form new messages, scales the result by $\overline{\alpha }$, applies eight-bit saturation, and generates provisional hard decisions based on the sign. Both the updated soft-value vectors and hard-decision bits are subsequently written to the VN RAM and output RAM, respectively.

6. End-to-End Vivado Design Suite 2024 Block Design

Figure 5 illustrates the integrated encoder-channel-decoder chain instantiated in Vivado 2024 (AMD Xilinx, San Jose, CA, USA), the Xilinx FPGA design and implementation platform, by introducing external IP cores generated using the Xilinx Vitis HLS 2025, high-level synthesis toolchain. Although the LDPC IP core was validated at a clock frequency of 350 MHz, the design employs a 100 MHz system clock generated by the clocking wizard IP and distributed via the processor system reset module. Each frame begins with a single-cycle start pulse, and all AXI4-Stream interfaces operate without backpressure, with the ready signal held asserted.

A pseudo-random source generates independent and identically distributed (i.i.d.) Bernoulli bits using a linear feedback shift register (LFSR) method. After AXI4-Stream handshakes, the QC-LDPC encoder accepts the payload and emits a serialized codeword. An RTL binary phase-shift keying (BPSK) modulator maps bits to signed 8-bit symbols with values $\{+127,-128\}$. Additive noise is produced by an external AWGN IP implementing the Box–Muller transform (see Appendix C). Variance and seed registers are programmed via AXI4-Lite memory-mapped writes issued by the Zynq UltraScale+ multiprocessor system-on-chip (MPSoC) (AMD Xilinx, San Jose, CA, USA) processing system (PS), enabling deterministic initialization and run-time reconfiguration of the programmable logic (PL) core. The noise stream is buffered in a first-in first-out (FIFO) to decouple producer and consumer timing. On readout, the noise is added to the BPSK waveform, saturated to $[-128,127]$, and treated as the input LLR stream for the decoder. Similar to AWGN parameters, the iteration limit, ${\mathrm{Itr}}_{max}$, is also configured by a control register for each frame.

During transmission, the reference bit for each payload position is stored in a reference FIFO. In parallel, a channel hard decision is derived from the sign of the saturated received sample and stored in a second FIFO to measure uncoded performance. When decoded bits become available, they are compared against the reference FIFO to accumulate the post-decoder error count, while the channel-hard stream is compared against the same reference to count bit flips caused by noise.

7. Emulation Results

We evaluate decoding algorithms under a layered schedule on the QC-LDPC code $(1056,704)$ with ${\mathrm{Itr}}_{max}=50$ using 8-bit fixed-point LLRs (clip/saturate) and syndrome-based early termination. The channel is AWGN, and $E_b/N_0$ is swept on a uniform grid with sufficient frames per point to probe down to $\mathrm{BER}\le {10}^{-8}$. All baselines use identical quantization, stopping criteria, and layered scheduling for a fair comparison. Unlike conventional NMS, the proposed 2D-CNMS introduces dual-direction scaling and normalization refinements that significantly improve convergence speed and error-floor performance while maintaining FPGA-friendly complexity.

According to [33], the optimal two-level CN normalization factors $({\beta }_1,{\beta }_2)$ decrease with increasing check-node degree ($d_c$) and approach constants at high SNR. Specifically, for the regular codes with $d_c=6$ and $\mathrm{SNR}\in [0,4]$ dB, ${\beta }_1\in [0.50,0.90]$ and ${\beta }_2\in [0.27,0.50]$, trending toward the upper end as SNR rises. Consistently, [16] reports nearly iteration-invariant scalings for IEEE 802.11n $(1944,1296)$, $R=2/3$ as $\overline{\alpha }\approx 0.9007$ and $\overline{\beta }\approx 0.8973$, achieving BER within $0.02$ dB of an SP algorithm over $E_b/N_0\in [1.4,2.6]$ dB. In line with [37], the strongest single-scalar NMS baseline uses a fixed normalization schedule, as follows:

$${\beta }^{(\ell )}=3/4+2^{-(\ell +1)}\mathrm{if}2\le \ell \le 5,\mathrm{else}3/4$$

(13)

where ℓ represents the number of iterations.

These observations support fixed, iteration-invariant gains. Guided by coarse-to-fine emulation sweeps on the target IEEE 802.16e QC-LDPC codes (rates $1/2,2/3,3/4$), we therefore map $({\beta }_1,{\beta }_2)$ to $\overline{{\beta }_1}=0.8125$ and $\overline{{\beta }_2}=0.875$, and set the VN gain to $\overline{\alpha }=0.75$. All scalings are implemented via shift-and-subtract to eliminate multipliers and extra memory.

7.1. Performance and Complexity Comparison

Figure 6 compares full-SP, layered-SP, NMS ($\beta =0.75$) [31,37], 2D-MS ($\overline{\alpha }=\overline{\beta }\approx 0.899$) [26], 2D-NMS (${\beta }_1,{\beta }_2$) = ($0.75,0.875$) [33], and the proposed 2D-CNMS ($\overline{\alpha },\overline{{\beta }_1},\overline{{\beta }_2}$)$=$($0.75,0.8125,0.875$) on a QC-LDPC code ($1056,704$) with ${\mathrm{Itr}}_{max}=50$. Across the operational $E_b/N_0$ range, a few algorithms, notably layered-SP and, at certain SNR points, 2D-NMS, exhibit slightly better BER performance than the proposed 2D-CNMS. This behavior is expected and is consistent with the algorithmic discussion in Section 3: layered-SP employs full message-passing scheduling with nonlinear message updates, whereas 2D-CNMS deliberately adopts MS style add-compare-select operations with dual shift-based normalization to remain multiplier-free and FPGA-efficient. The modest loss in BER therefore reflects a deliberate trade-off between decoding optimality and hardware realizability. At the same time, 2D-CNMS outperforms the other MS-based variants (NMS, 2D-MS, 2D-NMS) because the dual normalization $(\overline{\alpha },{\overline{\beta }}_1,{\overline{\beta }}_2)$ compensates for the residual gap to SP more effectively while avoiding multipliers and additional memory, yielding better BER in both the waterfall and high-SNR regions at substantially lower complexity and thus the most favorable performance-complexity trade-off.

Figure 7 reports BER versus decoder iterations for the $(1056,704)$ code under BPSK/AWGN. At SNR$=2.0$ dB, the proposed 2D-CNMS achieves BER$\le {10}^{-7}$ by approximately 12 iterations, whereas the conventional NMS (with $\beta =0.75$) requires roughly 15 iterations. For SNR$\le 1.5$ dB, neither method reaches ${10}^{-7}$ within 50 iterations. Nevertheless, 2D-CNMS maintains a uniformly lower BER for the same iteration budget and, at SNR$=1.5$ dB, attains BER$\approx {10}^{-6}$ in the mid-30s iterations, while NMS does not achieve ${10}^{-6}$ within 50 iterations. These iteration savings translate directly to reduced latency and higher throughput (see Section 7.3).

Figure 8 presents the $\mathrm{BER}$ performance of the proposed 2D-CNMS decoder for the $\mathrm{IEEE}802.16\mathrm{e}$ QC-LDPC code profiles. For each code rate $(R=1/2,2/3,3/4)$, three block lengths $(N=528,1056,2064)$ are shown. As expected, lower-rate codes achieve better BER at a given SNR, while higher-rate codes are shifted to the right. For a fixed rate, increasing the block length improves the coding gain, with longer codes exhibiting a steeper waterfall region over the simulated SNR range.

Table 2. Computational complexity of a check node within a single iteration.

Ref.	Algorithm	Mult.	Div.	Comparison	Add.	Sub.	Bit-Shift	FPGA Impl.	Remarks
[12]	SP	$d_c$	$d_c-1$	0	1	0	0	✗	tanh, ${tanh}^{-1}$
[38]	MS	0	0	$d_c+{log}_2{d}_c-2$	0	0	0	✗	–
[31]	NMS	1	0	$d_c+{log}_2{d}_c-2$	0	0	0	✗	–
[32]	OMS	0	0	$d_c+{log}_2{d}_c-2$	0	1	0	✗	–
[39]	$NMS$	0	0	$d_c+{log}_2{d}_c-2$	4	0	12	✓	$\beta =0.75$
[16]	2D-MS	2	0	$d_c+{log}_2{d}_c+2$	0	0	0	✗	adaptive
[26]	2D-MS	2	0	$d_c+{log}_2{d}_c-2$	0	0	0	✓	$\overline{\alpha }=\overline{\beta }=0.899$
[33]	2D-NMS	2	0	$d_c+{log}_2{d}_c-2$	0	0	0	✗	–
[32]	2D-NMS	2	0	$d_c+{log}_2{d}_c-2$	0	0	0	✗	${\beta }_1=0.75,{\beta }_2=0.875$
									$\overline{\alpha }=0.75$
Ourwork	2D-CNMS	0	0	$d_c+{log}_2{d}_c-2$	0	3	12	✓	$\overline{{\beta }_1}=0.8125$
									$\overline{{\beta }_2}=0.875$

contrasts the arithmetic requirements of SP, MS, NMS, OMS, 2D-MS, 2D-NMS, and the proposed 2D-CNMS on a per-check-node basis. SP demands $d_c$ multiplications and $d_c-1$ divisions. 2D-MS retains two multipliers. In the proposed 2D-CNMS approach, we remove the multipliers and dividers and keep the comparator count $d_c+{log}_2{d}_c-2$.

Normalization is implemented using three subtractions, followed by a fixed power-of-two scaling corresponding to 12 right bit shifts. This 12-bit shift acts as a fixed-point approximation of the SP normalization factors, which require multiplications, in the 2D-CNMS algorithm for the considered IEEE 802.16e QC-LDPC codes. As confirmed by the decoding performance curves in Figure 6, this simple 12-bit shift achieves near-SP error-rate performance while completely avoiding multipliers and dividers. Consequently, the resulting data path is digital signal processing (DSP)-free and FPGA-native: 2D-CNMS, similar in spirit to OMS, NMS, 2D-MS, and 2D-NMS, trades multiplications/divisions for lightweight comparisons and shifts, delivering SP-like decoding behavior with significantly simpler hardware or, equivalently, better performance for a comparable hardware cost.

7.2. Resource Utilization

Table 3. Previous LDPC decoder implementations on various FPGA platforms.

Method	Type	Decoder	Schedule	Standard	N	Rate	Itr.	${\mathit{f}}_{\mathit{clk}}$ (MHz)	$\mathbf{\Gamma }$ (Mbps)	Logic 1	RAM 2
[40]	$\mathrm{HLS}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.16e$	768	$1/2$	10	$211.1$	99	$\mathrm{147,000}$	1641
[40]	$\mathrm{HLS}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.16e$	1152	$1/2$	10	$222.6$	104	$\mathrm{161,000}$	1703
[40]	$\mathrm{HLS}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.16e$	1536	$1/2$	10	$203.5$	82	$\mathrm{134,000}$	1461
[40]	$\mathrm{HLS}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.16e$	1920	$1/2$	10	$202.4$	81	$\mathrm{144,000}$	1516
[41]	$\mathrm{HLS}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.11n$	648	$1/2$	3	122	27	9072	28
[42]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	$802.11n$	1944	$1/2$	10	157	21	$\mathrm{187,000}$	1349
[43]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	$802.11n$	648	$1/2$	6	100	281	$\mathrm{35,668}$	81
[44]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	custom	1024	$1/2$	30	175	-	$\mathrm{25,035}$	72
[45]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$802.16e$	576	$1/2$	20	100	33	8685	106
[45]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$802.16e$	2304	$1/2$	10	100	307	$\mathrm{34,104}$	281
[46]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	$802.11n$	972	$1/2$	4	200	2476	$\mathrm{159,000}$	831
[46]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$802.11n$	1944	$1/2$	4	200	608	$\mathrm{33,351}$	120
[47]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$802.11n$	1944	$1/2$	8	260	608	$\mathrm{33,351}$	102
[48]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Flooding}$	$802.16e$	2304	$1/2$	20	260	290	<15,520	76
[39]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$802.11n$	648	$1/2$	5	194	77	$\mathrm{19,332}$	3
[49]	$\mathrm{FPGA}$	$\mathrm{OMS}$	$\mathrm{Layered}$	$\mathrm{DVB}\text{-}\mathrm{S}2$	$16,384$	$1/2$	10	250	2130	$\mathrm{49,121}$	50
[50]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	$802.16e$	1536	$1/2$	5	-	209	$\mathrm{14,000}$	-
[51]	$\mathrm{FPGA}$	$\mathrm{MS}$	$\mathrm{Layered}$	$802.16e$	1152	$1/2$	10	330	188	$\mathrm{25,621}$	76
	$\mathrm{FPGA}$	2D-CNMS	$\mathrm{Layered}$	$802.16e$	528	$1/2$	15	100	29	9696	0
Our-work	$\mathrm{FPGA}$	2D-CNMS	$\mathrm{Layered}$	$802.16e$	1056	$1/2$	15	100	34	$\mathrm{10,343}$	0
	$\mathrm{FPGA}$	2D-CNMS	$\mathrm{Layered}$	$802.16e$	2064	$1/2$	15	100	34	$\mathrm{11,748}$	0

¹ Logic: LUTs (Xilinx) or ALMs (Intel Altera). ² RAM: 18 K-bit BRAM (Xilinx) or 20 K-bit M20K (Altera).

summarizes representative LDPC decoder implementations on FPGA platforms for WiMAX [29], WiFi [9], and DVB-S2 [3] standards. Most of these designs target throughputs in the hundred-Mbps range, but at the cost of very large logic and memory footprints, typically on the order of 8.7–187 k LUTs and 3–1703 block random-access memories (BRAMs). These figures provide a reference envelope for conventional MS/OMS decoders implemented either via HLS or hand-tuned RTL.

The dominant resource bottleneck in LDPC decoding is often memory, because each iteration repeatedly reads and writes extrinsic messages while applying QC cyclic-shift permutations dictated by the rate-dependent permutation matrix. In a straightforward hardware mapping, these messages are typically stored in BRAM since multiple concurrent accesses are required per cycle. For highly parallel and irregular access patterns, BRAM replication may be inferred to emulate multi-port behavior, which can significantly increase BRAM usage, especially at higher code rates. In this work, each code rate uses a different permutation matrix [30], which changes the arrangement of non-empty circulant sub-matrices and shift distribution, thereby affecting connectivity and the “bank-friendliness” of the access schedule.

As highlighted in the gray-shaded rows at the bottom of Table 3, the proposed 2D-CNMS QC-LDPC decoder achieves comparable tens-of-Mbps throughput (29–34 Mbps at 100 MHz for WiMAX rate-1/2 codes) while using only $9.7$–$11.7$ k LUTs and zero BRAM blocks. In contrast, many prior FPGA-based decoders require tens to hundreds of thousands of LUTs and from a few up to more than 1700 BRAM blocks to reach similar or higher throughput regimes. Thus, within the reference envelope established by Table 3, the proposed architecture provides a more favorable logic/memory–throughput trade-off, especially in terms of eliminating dedicated block memories.

To avoid BRAM growth, we adopt a BRAM-free architecture based on banked, connection-indexed message storage with minimal redundant buffering so that parallel accesses are served by independent banks rather than BRAM-based multi-port memories. Practical BRAM-mitigation strategies for QC-LDPC decoders include (i) memory banking and access scheduling to avoid multi-port conflicts and replication, (ii) redundancy reduction by removing duplicate buffers via in-place updates, and (iii) optional data packing when BRAM-based storage is preferred. Consequently, post-optimization synthesis reports $\mathrm{BRAM}=0$ for all configurations in

Table 4. Post-synthesis optimized resource utilization of 2D-CNMS QC-LDPC decoder.

Resource 1	$\mathbf{R}=1/2$			$\mathbf{R}=2/3$			$\mathbf{R}=3/4$
	$(\mathbf{528},\mathbf{264})$	$(\mathbf{1056},\mathbf{528})$	$(\mathbf{2064},\mathbf{1032})$	$(\mathbf{528},\mathbf{352})$	$(\mathbf{1056},\mathbf{704})$	$(\mathbf{2064},\mathbf{1376})$	$(\mathbf{528},\mathbf{396})$	$(\mathbf{1056},\mathbf{792})$	$(\mathbf{2064},\mathbf{1548})$
$\mathrm{LUT}$	9696	$10,343$	$11,748$	$10,396$	$10,780$	$12,651$	$20,145$	$21,212$	$22,416$
$\mathrm{FF}$	2362	2146	2328	2518	2320	2502	5899	5837	5732
$\mathrm{DSP}$	0	0	0	0	0	0	0	0	0
$\mathrm{BRAM}$	0	0	0	0	0	0	0	0	0
$\mathrm{URAM}$	0	0	0	0	0	0	0	0	0
$\mathrm{SRL}$	68	0	0	65	0	0	228	221	228
$\mathrm{LATCH}$	0	0	0	0	0	0	0	0	0
$\mathrm{CLB}$	0	0	0	0	0	0	0	0	0
$\mathrm{SLICE}$	0	0	0	0	0	0	0	0	0
${\mathrm{Latency}}^2$	1834	3239	6179	1834	3239	6179	1563	2817	5076
${\mathrm{C}}_{\mathrm{iter}}$3	63	98	182	63	98	182	42	64	97
$\Gamma \left(\mathrm{Mbps}\right)$	29	34	34	29	33	34	34	38	41

¹ Target clock period: 10.000 ns, optimized iteration: 15. ² Decoding latency is based on clock-cycle$@100\mathrm{MHz}$. ³ Equation (14).

, while some storage and alignment are realized using distributed resources, reflected in the reported LUT/shift-register LUT (SRL) utilization. In addition, $\mathrm{SRL}=0$ in some configurations indicates that the selected permutation and schedule can be implemented without explicit shift-register delay chains, whereas higher-pressure cases require additional distributed delay/buffering implemented as SRLs.

For compactness, Table 3 reports only the WiMAX rate-1/2 configurations of the proposed decoder so that they can be directly compared with representative prior work under a common standard and code rate. A detailed breakdown of resource utilization and timing for all supported block lengths and code rates ($1/2$, $2/3$, and $3/4$) is provided in Table 4.

Table 4 therefore reports the post-synthesis utilization and timing of the proposed 2D-CNMS QC-LDPC decoder for multiple $(N,K)$ settings and code rates. All instances remain DSP-free and BRAM-free: all check-node and variable-node memories are mapped to LUT-based storage and registers, which keeps the BRAM usage at 0 for all configuration. The LUT, flip-flop (FF), and SRL counts stay modest, in the ranges $9.6$–$22.4$ k, $2.1$–$5.9$ k, and 68–228, respectively.

Compared with the prior-art decoders of Table 3, which typically require $8.7$–187 k LUTs and tens to thousands of BRAMs, the proposed 2D-CNMS architecture achieves comparable tens-of-Mbps throughput with a 3–$8\times$ reduction in logic utilization and eliminates dedicated block memories altogether. This demonstrates that the HLS-based 2D-CNMS formulation compiles to compact RTL with predictable scaling while preserving the algorithmic benefits of two-dimensional dyadic normalization.

7.3. Decoding Latency Analysis

Decoding latency is measured in clock cycles required to process one full codeword. Under non-overlapped AXI4-Stream I/O, the total latency consists of the sequential input of all channel LLRs, the sequential output of the final hard decisions, a fixed I/O and pipeline overhead, and an iteration-dependent compute term. For code rate $2/3$ defined by an $8\times 24$ permutation matrix (see Table 1), the lifting size is $Z=N/24$ and the information length is $K=2/3\times N$. Calibrated to the HLS schedule, the per-iteration compute cost scales approximately linearly with Z. For a run with ${\mathrm{Itr}}_{max}$ decoding iterations, the latency in cycles is

$${\Lambda }_N=N+K+{\delta }_{\mathrm{pipe}}+It{r}_{max}\times C_{\mathrm{iter}}\left(Z\right)$$

(14)

with ${\delta }_{\mathrm{pipe}}$ the fixed pipeline and I/O overhead and $C_{\mathrm{iter}}$, the scheduled check-node and variable-node kernel cost per iteration. From the post-synthesis report, as addressed in Table 4, at rate $2/3$, we conservatively upper-bound ${\delta }_{\mathrm{pipe}}=9$ cycles, $C_{\mathrm{iter}}\left(22\right)=63$ cycles for QC-LDPC ($528,352$), and $C_{\mathrm{iter}}\left(44\right)=98$ cycles for ($1056,704$). Given a clock frequency $F_{clk}$ in $\mathrm{MHz}$, the coded-bit throughput in $\mathrm{Mbps}$ is

$$\mathcal{T}={\displaystyle \frac{N\times F_{clk}}{\Lambda }}Mbps$$

(15)

while the information-bit throughput equals $R\times \mathcal{T}$.

As summarized in Figure 9, the decoding latency as a function of the iteration limit for $N\in \{528,1056,2064\}$ is illustrated in Figure 9a, whereas Figure 9b reports the corresponding throughput trend at $F_{\mathrm{clk}}=100\mathrm{MHz}$. The latency curves grow almost linearly with the number of iterations, which indicates that each additional iteration contributes an approximately constant extra delay. For larger block lengths, the slope is steeper, reflecting the increased amount of message-processing work per iteration.

In contrast, the throughput curves decrease monotonically with the iteration budget because longer processing time per codeword directly reduces the number of codewords that can be decoded per second. For any fixed iteration limit, the larger block sizes achieve slightly higher throughput since the fixed I/O and control overheads are amortized over more decoded bits. The same qualitative behavior is observed at $F_{\mathrm{clk}}=350\mathrm{MHz}$ reported in Appendix D.

To experimentally validate the 2D-CNMS decoder latency model in (14) and corroborate the post-synthesis estimates in Table 4, Figure 10 presents representative RTL simulation traces obtained in Xilinx Vivado 2024 for the $(528,352)$ and $(1056,704)$ QC-LDPC codes. For each configuration, the left cursor is aligned with the first valid AXI4-Stream LLR sample at the decoder input, and the right cursor marks the last valid hard-decision bit at the decoder output. Between these two cursors, the cyan input counters ramp over N samples, after which the decoder enters its iterative processing phase, clearly visible as the dark-red activity region in the decoder waveforms. For the $(528,352)$ code (Figure 10a), the decoder is configured with ${\mathrm{Itr}}_{max}=15$, producing 15 almost identical dark-red segments and a total measured latency of approximately $18.6\mathsf{\mu }\mathrm{s}$. For the $(1056,704)$ code (Figure 10b), ${\mathrm{Itr}}_{max}=32$ iterations are enabled, resulting in a longer dark-red region and a latency of about $48.4\mathsf{\mu }\mathrm{s}$. We deliberately choose different iteration limits for the two block lengths to make the impact of the iteration budget on the overall latency visually evident: each additional iteration extends the dark-red decoder activity by approximately a constant amount, which is consistent with the iteration-dependent term in the latency model of (14) and with the nearly linear latency-iteration relationship observed in Figure 9a.

8. Conclusions

This work presented an end-to-end FPGA implementation of a QC-LDPC decoder for VSATPlus systems using Vitis HLS 2025 and Vivado 2024. The primary contribution lies in demonstrating a practical design methodology for mapping advanced LDPC decoding techniques onto FPGA hardware through HLS-driven flows, enabling rapid prototyping and deployment without manual RTL development. The proposed architecture employs shift-and-subtract operations to eliminate multipliers and dividers, resulting in a DSP-free design optimized for resource-constrained satellite terminals. The complete system integration was achieved using HLS-generated IP cores for the encoder, AWGN channel, and decoder. Under a 100 MHz clock, the decoder attains a coded-bit throughput of 29–41 Mbps with optimized resource utilization, while maintaining low implementation complexity. Fixed scaling factors were selected through empirical optimization to balance BER performance and hardware simplicity, avoiding the complexity overhead of adaptive scaling with negligible performance penalty. Performance evaluation under AWGN, which is appropriate for geostationary Earth orbit (GEO) VSATPlus links with negligible Doppler and stable fading, shows near-SP decoding performance and no observable error floor down to $\mathrm{BER}<{10}^{-8}$. Compared with MS-family baselines, the implemented design achieves faster convergence and lower iteration counts, translating into reduced latency and higher throughput.

Future work will extend this HLS-based methodology beyond AWGN baselines by assessing robustness under non-Gaussian and interference-rich satellite communications (SATCOM) conditions (e.g., narrowband and partial-band interference, pulsed and swept jamming, adjacent-channel interference, and time-varying intelligent jamming). In this context, we will also consider lightweight cross-layer hooks between FEC and higher-layer counter-jamming mechanisms, where deep reinforcement learning (DRL)-based strategies are one possible option, for example, by exploiting decoder reliability indicators to enable adaptive operation, as motivated by dual-intelligence satellite/terminal counter-jamming frameworks [52]. In parallel, we will further connect this work with CNN-based LDPC decoding by targeting “colored’’ noise (e.g., 1/f-type correlation) to adapt decoding and scheduling for improved end-to-end throughput and resilience [23].