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Open AccessArticle

Router-Integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems

1
Graduate School of Information, Production and Systems, WASEDA University, Wakamatsu-ku, Fukuoka 808-0135, Japan
2
Electrical Academy, Jiangxi University of Science and Technology, Ganzhou 3410000, China
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(11), 1363; https://doi.org/10.3390/electronics8111363
Received: 20 August 2019 / Revised: 28 October 2019 / Accepted: 15 November 2019 / Published: 17 November 2019
In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads to maintain sharing data efficiently. In this work, an enhanced router network is integrated within the private cache level for fast interconnecting sharing data accesses existing in different threads. All sharing data in private cache level can be classified into seven access types by experimental pattern analysis. Then, both shared accesses and thread-crossed accesses can be rapidly detected and dealt with in the proposed router network. As a result, the access latency of private cache is decreased, and a conventional coherence traffic problem is alleviated. The process in the proposed path is composed of three steps. Firstly, the target accesses can be detected by exploring in the router network. Then, the proposed replacement logic can handle those accesses for maintaining data coherence. Finally, those accesses are delivered in the proposed data deliverer. Thus, the harmful data sharing accesses are solved within the first chip layer in 3D-IC structure. The proposed system is also implemented into a cycle-precise simulation platform, and experimental results illustrate that our model can improve the Instructions Per Cycle (IPC) of on-chip execution by maximum 31.85 percent, while energy consumption can be saved by about 17.61 percent compared to the base system. View Full-Text
Keywords: network on cache; CMP systems; stacked integration; router architecture; TSVs network on cache; CMP systems; stacked integration; router architecture; TSVs
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Zhao, H.; Jia, X.; Watanabe, T. Router-Integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems. Electronics 2019, 8, 1363.

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