VLSI-Based Sequential Devices in Cyber-Physical Systems

Topic Information

Dear Colleagues,

Cyber–physical systems (CPSs) are widely used in many fields of human activity. These systems significantly impact the quality of our lives. As a rule, CPSs can be viewed as a composition of microcontrollers (microprocessors) and various specific blocks. Various sequential devices (SDs) are crucial CPSs. They can be used as control units of a system, controllers of protocols, and can be responsible for the cooperation of a central processing unit with various accelerators. The quality of such SDs determines the quality of a particular CPS. Often, to represent the behavior of SDs, the models of Petri nets and FSM are used. Currently, microelectronics become nanoelectronics. For this reason, modern CPSs include application-specified integrated circuits (ASICs), application-specified standard products (ASSPs), and field-programmable gate arrays (FPGAs). A single chip is enough to implement a very complex cyber–physical system. This phenomenon has led to the need to develop new design methods taking into account the specifics of ASIC, ASSP, and FPGAs. As a result, designers of SDs face the following challenge: a sequential device circuit with the smallest possible hardware, propagation time, and energy consumed must be implemented. All these characteristics must be balanced. The ever-increasing complexity of modern and future CPSs requires the development of efficient computer-aided design tools to implement complex sequential devices. The aim of this Topic is to expand research on the practical and theoretical aspects associated with the design of sequential devices and the application of SD-based blocks in modern cyber–physical systems. The key focus is to present theoretical advances, as well as new design and verification methods to improve the quality of SD-based circuits as elements of modern cyber–physical systems. Topics may include, but are not limited, the following:

• Development of theory of sequential devices;
• Development of methods of state assignment targeting improving basic characteristics of sequential devices (chip area, performance, and consumed energy); 
• Improving the specification of SDs targeting real-scale projects; 
• Design of energy-efficient SDs; 
• Development of hardware-dependent design methods targeting SDs implemented with ASICs, ASSP and FPGAs; 
• Development of design methods for asynchronous SDs;
• Development of hardware-dependent and hardware-independent computer-aided design tools targeting SDs; 
• Development of design methods for hierarchical SDs; 
• Improving testability of complex SDs;
• Development of advanced methods of verification of SD-based circuits.

Prof. Dr. Alexander Barkalov
Prof. Dr. Larysa Titarenko
Dr. Kazimierz Krzywicki
Topic Editors

Keywords

Participating Journals

Journal Name	Impact Factor	CiteScore	Launched Year	First Decision (median)	APC
Applied Sciences applsci	2.9	6.1	2011	16 Days	CHF 2400	Submit
Chips chips	-	2.8	2022	22.4 Days	CHF 1000	Submit
Electronics electronics	2.9	7.0	2012	16.4 Days	CHF 2400	Submit
Energies energies	3.9	8.3	2008	16.8 Days	CHF 2600	Submit
Journal of Low Power Electronics and Applications jlpea	1.7	4.6	2011	24.2 Days	CHF 1800	Submit
Sensors sensors	4.0	9.4	2001	17.8 Days	CHF 2600	Submit

Preprints.org is a multidisciplinary platform offering a preprint service designed to facilitate the early sharing of your research. It supports and empowers your research journey from the very beginning.

MDPI Topics is collaborating with Preprints.org and has established a direct connection between MDPI journals and the platform. Authors are encouraged to take advantage of this opportunity by posting their preprints at Preprints.org prior to publication:

1. Share your research immediately: disseminate your ideas prior to publication and establish priority for your work.
2. Safeguard your intellectual contribution: Protect your ideas with a time-stamped preprint that serves as proof of your research timeline.
3. Boost visibility and impact: Increase the reach and influence of your research by making it accessible to a global audience.
4. Gain early feedback: Receive valuable input and insights from peers before submitting to a journal.
5. Ensure broad indexing: Web of Science (Preprint Citation Index), Google Scholar, Crossref, SHARE, PrePubMed, Scilit and Europe PMC.

Published Papers (2 papers)

Order results

Content type Publication Date

Result details

Normal Extended Compact

Journals

All Applied Sciences Electronics Energies Sensors Chips JLPEA

Show export options expand_more Show export options expand_less

Select all

Export citation of selected articles as:

Plain Text BibTeX BibTeX (without abstracts) Endnote Endnote (without abstracts) Tab-delimited RIS

Error

Oops... you haven't selected anything for export.

Ok

clear

27 pages, 5602 KB  

Open AccessArticle

Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages

by Adam Milik, Wojciech Kierat and Tomasz Rudnicki

Energies 2026, 19(8), 2001; https://doi.org/10.3390/en19082001 - 21 Apr 2026

Viewed by 414

Abstract

The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential [...] Read more.

The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential sentences of a language to parallel computations and then map them to a dedicated hardware structure. The flexible graph-based method of language mapping is shown. It enables extracting control and data flow from language sentences. The direct hardware mapping technique enables building not only a high-performance structures but also a low-power implementations. All implementations retain a very short response time consisting of several clock cycles (from 3 to 7). The proposed low-power mapping strategies enable power saving up to 10 times while retaining processing performance. The obtained results are compared with a standard implementation using a benchmark program set. The paper is concluded with a comparison of the performance and energy consumption for the proposed implementation strategies. Full article

(This article belongs to the Topic VLSI-Based Sequential Devices in Cyber-Physical Systems)

►▼ Show Figures

Figure 1

31 pages, 6311 KB  

Open AccessArticle

Synthesis of FPGA-Based Moore FSMs with Two Cores of Partial Functions

by Alexander Barkalov, Larysa Titarenko and Kazimierz Krzywicki

Electronics 2026, 15(6), 1279; https://doi.org/10.3390/electronics15061279 - 18 Mar 2026

Viewed by 595

Abstract

A new architecture of FPGA-based Moore finite state machine (FSM) is proposed, as well as the corresponding method of synthesis. The proposed architecture of FSM circuit includes two cores of partial Boolean functions. The first core is based on functional decomposition, the second [...] Read more.

A new architecture of FPGA-based Moore finite state machine (FSM) is proposed, as well as the corresponding method of synthesis. The proposed architecture of FSM circuit includes two cores of partial Boolean functions. The first core is based on functional decomposition, the second core is based on structural decomposition. Under certain conditions, the proposed method improves both spatial and temporal characteristics of FSM circuits. The FSM states have two codes. The first of them is a maximum binary code (MBC) having minimum possible number of bits. The second code is a partial state code representing a state as the element of some class of compatibility. The method can be applied if Moore FSM circuits are implemented using look-up table (LUT) elements of field-programmable gate arrays. To improve characteristics of resulting FSM circuits, the classes of pseudoequivalent states are used. This allows diminishing the numbers of literals in sum-of-products representing partial input memory functions. The first core is multi-level. For the second core, all partial functions are generated by single-LUT circuits. These cores form the first level of FSM circuit. The LUTs of the second level generate bits of MBCs. These codes are used by the third circuit level for generating both FSM outputs and partial state codes. An example of synthesis is shown. The experiments are conducted using a known library of benchmark Moore FSMs. The experiments show that the proposed approach can be used for complex FSMs where the total number of FSM inputs and state variables is at least twice the number of inputs of the base LUT. The results of experiments show that the proposed method allows improving both the spatial and temporal characteristics for complex FSMs compared with their counterparts based on other known design methods. Full article

(This article belongs to the Topic VLSI-Based Sequential Devices in Cyber-Physical Systems)

►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less

Select all

Export citation of selected articles as:

Plain Text BibTeX BibTeX (without abstracts) Endnote Endnote (without abstracts) Tab-delimited RIS

 

Error

Oops... you haven't selected anything for export.

Ok

clear

Displaying articles 1-2