Special Issue "Low-Power Techniques for Embedded Systems and Network-on-Chip Architectures"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Networks".

Deadline for manuscript submissions: 30 November 2019.

Special Issue Editor

Dr. Davide Patti
E-Mail Website
Guest Editor
Department of Computer Science and Telecommunications Engineering, University of Catania, 95124 Catania, Italy
Interests: cyber-physical systems; networks on chip; design space exploration; approximate computing; neural networks
Special Issues and Collections in MDPI journals

Special Issue Information

Dear Colleagues,

Last generation embedded systems have evolved from traditional standalone systems to become a complex environment where computational elements tightly interact with physical entities such as sensors networks and I/O devices.

The mobility and pervasive requirements of such environments impose power and energy consumption constraints that must be met in the context of increasing computational needs, due to the processing of large amounts of data from sensing and input devices.

This Special Issue will explore emerging approaches, ideas, and contributions to address the challenges in the design of energy efficient computational-centric embedded systems and on-chip networks.

Potential topics include, but are not limited to:

  • Approximate computing for energy-efficient applications
  • Novel architectures for embedded low power computing
  • Communication infrastructures for energy efficient IoT environments
  • Energy efficient neural networks
  • Energy-aware parallel architectures for high-performance computing
  • Design Platforms and Tools for optimizing energy/performance trade-offs

Dr. Davide Patti
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • embedded systems
  • network-on-chip
  • approximate computing
  • power and energy
  • cyber-physical systems
  • neural networks
  • Internet of Things

Published Papers (2 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

Open AccessArticle
Router-Integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems
Electronics 2019, 8(11), 1363; https://doi.org/10.3390/electronics8111363 - 17 Nov 2019
Abstract
In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads [...] Read more.
In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads to maintain sharing data efficiently. In this work, an enhanced router network is integrated within the private cache level for fast interconnecting sharing data accesses existing in different threads. All sharing data in private cache level can be classified into seven access types by experimental pattern analysis. Then, both shared accesses and thread-crossed accesses can be rapidly detected and dealt with in the proposed router network. As a result, the access latency of private cache is decreased, and a conventional coherence traffic problem is alleviated. The process in the proposed path is composed of three steps. Firstly, the target accesses can be detected by exploring in the router network. Then, the proposed replacement logic can handle those accesses for maintaining data coherence. Finally, those accesses are delivered in the proposed data deliverer. Thus, the harmful data sharing accesses are solved within the first chip layer in 3D-IC structure. The proposed system is also implemented into a cycle-precise simulation platform, and experimental results illustrate that our model can improve the Instructions Per Cycle (IPC) of on-chip execution by maximum 31.85 percent, while energy consumption can be saved by about 17.61 percent compared to the base system. Full article
Show Figures

Figure 1

Open AccessArticle
Intelligent Mapping Method for Power Consumption and Delay Optimization Based on Heterogeneous NoC Platform
Electronics 2019, 8(8), 912; https://doi.org/10.3390/electronics8080912 - 19 Aug 2019
Abstract
As integrated circuit processes become more advanced, feature sizes become smaller and smaller, and more and more processing cores and memory components are integrated on a single chip. However, the traditional bus-based System-on-Chip (SoC) communication is inefficient, has poor scalability, and cannot handle [...] Read more.
As integrated circuit processes become more advanced, feature sizes become smaller and smaller, and more and more processing cores and memory components are integrated on a single chip. However, the traditional bus-based System-on-Chip (SoC) communication is inefficient, has poor scalability, and cannot handle the communication tasks between the processing cores well. Network-on-chip (NoC) has become an important development direction in this field by virtue of its efficient transmission and scalability of data between multiple cores. The mapping problem is a hot spot in NoC's research field, and its mapping results will directly affect the power consumption, latency, and other properties of the chip. The mapping problem is a NP-hard problem, so how to effectively obtain low-power and low-latency mapping schemes becomes a research difficulty. Aiming at this problem, this paper proposes a two-populations-with-enhanced-initial-population based on genetic algorithm (TI_GA) task mapping algorithm based on an improved genetic algorithm from the two indexes of power consumption and delay. The quality of the initial individual is optimized in the process of constructing the population, so the quality of initial population is improved. In addition, a two-population genetic mechanism is added during the iterative process of the algorithm. The experimental results show that TI_GA is very effective for optimizing network power consumption and delay of heterogeneous multi-core. Full article
Show Figures

Graphical abstract

Back to TopTop