Flash memory, as the core unit of a compute-in-memory (CIM) array, requires multiple positive and negative (PN) high voltages (HVs) for word lines (WLs) to operate during storage and computation. A traditional WL driver generates these voltages using...
Computing in memory represented by resistive switching (memristive) devices is a promising way to implement hardware for artificial neural networks. We see it as the way to create energy-efficient and high-performance systems for solving a wide range...
Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in t...
The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges...
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, w...
Artificial intelligence (AI) has become ubiquitous in modern computing systems, from high-performance data centers to resource-constrained edge devices. As AI applications continue to expand into mobile and IoT domains, the need for energy-efficient...
Vision transformers (ViTs) have emerged as one of the most popular computer vision models, achieving remarkable performance in image recognition. However, ViTs require large-scale, high-dimensional matrix computations, and traditional digital acceler...
For parallelization of applications with high processing times and large amounts of storage in High Performance Computing (HPC) systems, shared memory programming and distributed memory programming have been used; a parallel application is represente...
On-chip memory is one of the core components of deep learning accelerators. In general, the area used by the on-chip memory accounts for around 30% of the total chip area. With the increasing complexity of deep learning algorithms, it will become a c...
In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additi...
In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines st...
With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physi...
The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial in...
The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digita...
The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Con...
For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann lim...
The increasing computational demands of deep neural network inference drive the need for energy-efficient hardware accelerators that minimize data movement between memory and processing units. Compute-in-memory (CIM) architectures address this bottle...
Memristors, as transformative electronic devices designed to transcend the von Neumann architecture, enable the physical unification of information storage and computation, thereby offering a foundational hardware pathway toward energy-efficient, bra...
In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRA...
In floating gate compute-in-memory (CIM) chips, due to the gate equivalent capacitance of the large-scale array and the parasitic capacitance of the long-distance transmission wire, it is difficult to balance the switching speed and area of the word...
In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various...
This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve in...
We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations,...
Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study...
24 November 2021
Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders ca...
4 September 2020
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary...
Filamentary metal–oxide RRAM conducts through a tunneling gap for which the current grows exponentially with bias, so its Read-range I–V characteristic follows a
In SRAM-based compute-in-memory (CIM), read-bitline (RBL) charging and discharging depend on the physical bit pattern stored in the memory array, so the energy-relevant code statistic should be defined with respect to the actual read-port polarity. T...
The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging re...
The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an a...
Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provid...
Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for bo...
Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive mater...
Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory...
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumu...
In recent years, convolution operations often consume a lot of time and energy in deep learning algorithms, and convolution is usually used to remove noise or extract the edges of an image. However, under data-intensive conditions, frequent operation...
Deep neural networks (DNNs) require efficient hardware accelerators due to the high cost of vector–matrix multiplication operations. Computing-in-memory (CIM) architectures address this challenge by performing computations directly within memor...
Memristors mimic synaptic functions in advanced electronics and image sensors, thereby enabling brain-inspired neuromorphic computing to overcome the limitations of the von Neumann architecture. As computing operations based on von Neumann hardware r...
In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing...
Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossb...
Computing-in-memory (CIM) with emerging non-volatile resistive memory devices has demonstrated remarkable performance in data-intensive applications, such as neural networks and machine learning. A crosspoint memory array enables naturally parallel c...
Next-generation photonic memory, leveraging broad spectral operability and electromagnetic immunity, enables ultrafast data storage with high density, overcoming the physical limitations of silicon-based electronic memory in the post-Moore era. Phase...
Vector–matrix multiplication (VMM), which dominates the computational workload in neural networks, accounts for over 99% of all operations, particularly in Convolutional Neural Networks (CNNs). These operations, consisting of multiply-and-accum...
This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more...
Image analysis-based artificial intelligence (AI) models leveraging convolutional neural networks (CNN) take a significant role in evaluating the ripeness of strawberry, contributing to the maximization of productivity. However, the convolution, whic...
AI is fueling explosive growth in compute demand that traditional digital chip architectures cannot keep up with. Analog crossbar arrays enable power efficient synaptic signal processing with linear scaling on neural network size. We present a photon...
Deep convolutional neural networks (CNNs) have shown strong abilities in the application of artificial intelligence. However, due to their extensive amount of computation, traditional processors have low energy efficiency when executing CNN algorithm...
Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devi...
Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizi...
The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by t...
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