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Electronics
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Analog Circuits and Analog Computing
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Analog Circuits and Analog Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 June 2025 | Viewed by 5712

Special Issue Editor

Prof. Dr. Zhong Sun

E-Mail Website
Guest Editor
1.Institute for Artificial Intelligence, Peking University, Beijing 100871, China
2. School of Integrated Circuits, Peking University, Beijing 100871, China
Interests: analogue matrix computing; neural networks; resistive memory

Special Issue Information

Dear Colleagues,

Recently, we have witnessed a resurgence of analog computing, which is motivated by the strong demand for developing high-throughput and energy-efficient computers for accelerating data-intensive applications in the post-Moore era. It is also the result of the continuous interest in exploring unconventional computing paradigms, which is fueled by today’s advanced CMOS technology and emerging resistive memory concepts. Analog circuits inherently demonstrate immense computing parallelism, which endows analog computing with fast speed and low computational complexity. There have been widespread investments into analog computing, by using conventional or novel hardware technologies that concern computational acceleration or fusing memory and computing, in order to seek for computer performance breakthroughs in applications such as scientific computing and artificial intelligence. It is highly promising that analog computing in modern times will be substantially different from its past versions, and its development should make a key contribution to the sustainable development of the computer industry.

In this framework, the aim of this Special Issue is to attract reviews and original research outcomes related to the design of analog circuits and their applications to analog computing.

The topics of interest for this Special Issue include but are not limited to:

  • CMOS analog circuits for solving differential equations or linear algebraic problems;
  • CMOS analog circuits for neuromorphic computing and engineering;
  • Analog computing with emerging resistive memory for implementing logic gates, performing matrix operations, or emulating synapse/neuron functions;
  • In-memory computing using analog physical laws, with SRAM, DRAM, or nonvolatile resistive memory devices;
  • Addressing noise and accuracy issues of analog computing;
  • Analog–digital hybrid architectures for high-precision analog computing.

Prof. Dr. Zhong Sun
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog computing
  • analog CMOS
  • resistive memory
  • neuromorphic
  • in-memory computing

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Published Papers (4 papers)

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Research

18 pages, 6224 KiB  
Article
Realization of Modified Electrical Equivalent of Memristor-Based Pavlov’s Associative Learning to Avoid Training Fallacies
by Ankit Mehta, Arash Ahmadi and Majid Ahmadi
Electronics 2025, 14(3), 606; https://doi.org/10.3390/electronics14030606 - 4 Feb 2025
Viewed by 681
Abstract
Biological systems learn from past experiences by establishing relationships between two simultaneously occurring events, a phenomenon known as associative learning. This concept has promising applications in modern AI (Artificial Intelligence) and ML (Machine Learning). To leverage it effectively, a precise electrical model that [...] Read more.
Biological systems learn from past experiences by establishing relationships between two simultaneously occurring events, a phenomenon known as associative learning. This concept has promising applications in modern AI (Artificial Intelligence) and ML (Machine Learning). To leverage it effectively, a precise electrical model that can simulate associative learning observed in biological systems is essential. The paper focuses on modeling Pavlov’s famous experiment related to the drooling of dogs at the sound of bell after associating the food with the bell during training. The study addresses limitations in existing circuit designs that fail to accurately replicate associative learning in dogs, particularly when the sequence of food and bell signals deviates from a specific pattern. We propose a novel design using a few CMOS (Complementary Metal Oxide Semiconductor) transistors and memristor models that produces an output corresponding to the dogs drooling only when food and bell signals are associated, mirroring real-life training conditions. The results section first discusses simulations using the standard TiO2 (Titanium Oxide) memristor model, followed by experimental results obtained from a classical memristor emulator. Both simulation and experimental findings confirm the effectiveness of the circuit designs. Full article
(This article belongs to the Special Issue Analog Circuits and Analog Computing)
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26 pages, 8203 KiB  
Article
Transistor Frequency-Response Analysis: Recursive Shunt-Circuit Transformations
by Pratyush Manocha and Gabriel A. Rincón-Mora
Electronics 2025, 14(2), 296; https://doi.org/10.3390/electronics14020296 - 13 Jan 2025
Viewed by 981
Abstract
Frequency-response analysis is critical in circuit design. Frequency response encodes crucial information, like gain, accuracy, bandwidth, response time, phase shift, stability, and more. Unfortunately, existing methods are either algebraic and obscure or approximations with inaccuracies. So applying them to more complex circuits is [...] Read more.
Frequency-response analysis is critical in circuit design. Frequency response encodes crucial information, like gain, accuracy, bandwidth, response time, phase shift, stability, and more. Unfortunately, existing methods are either algebraic and obscure or approximations with inaccuracies. So applying them to more complex circuits is often arduous or unreliable. This paper proposes recursive shunt-circuit transformations: a simple, rigorous, and insightful analytical method for conceptualizing and designing electronic circuits. The method asserts that (a) each equivalent capacitance shunts away its parallel resistance past its RC frequency. This (b) decreases the gain (induces a pole) and (c) changes the circuit. (d) The next dominant capacitance shunts its parallel resistance past the next pole and so on until all remaining capacitances shunt their parallel resistances past the poles they establish. The method also asserts that (e) bypass capacitances increase gain (induce zeros) and (f) cross-amp capacitances couple stages and poles. By applying this method and concepts, designers can (i) simplify an arbitrarily complex circuit into simpler coupled/decoupled stages and (ii) determine and manage poles and zeros with insight. This method was applied to design and analyze single- and multi- stage amplifier circuits and results were benchmarked against traditional methods and NGSPICE simulations, demonstrating its accuracy and broad applicability. Full article
(This article belongs to the Special Issue Analog Circuits and Analog Computing)
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14 pages, 1606 KiB  
Article
TA-Quatro: Soft Error-Resilient and Power-Efficient SRAM Cell for ADC-Less Binary Weight and Ternary Activation In-Memory Computing
by Thanh-Dat Nguyen, Minh-Son Le, Thi-Nhan Pham and Ik-Joon Chang
Electronics 2024, 13(15), 2904; https://doi.org/10.3390/electronics13152904 - 23 Jul 2024
Viewed by 992
Abstract
Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations [...] Read more.
Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works. Full article
(This article belongs to the Special Issue Analog Circuits and Analog Computing)
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16 pages, 5014 KiB  
Article
A First-Order Noise-Shaping SAR ADC with PVT-Insensitive Closed-Loop Dynamic Amplifier and Two CDACs
by Jaehyeon Nam, Youngha Hwang, Junhyung Kim, Jiwoo Kim and Sang-Gyu Park
Electronics 2024, 13(9), 1758; https://doi.org/10.3390/electronics13091758 - 2 May 2024
Cited by 1 | Viewed by 1919
Abstract
This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables [...] Read more.
This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. Full article
(This article belongs to the Special Issue Analog Circuits and Analog Computing)
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