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Article

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

by
Eduardo Pérez
1,*,
Antonio Javier Pérez-Ávila
2,
Rocío Romero-Zaliz
3,
Mamathamba Kalishettyhalli Mahadevaiah
1,
Emilio Pérez-Bosch Quesada
1,
Juan Bautista Roldán
2,
Francisco Jiménez-Molinos
2 and
Christian Wenger
1,4
1
IHP-Leibniz-Institut für Innovative Mikroelektronik, 15236 Frankfurt, Germany
2
Department of Electronics and Computer Technology, University of Granada, 18071 Granada, Spain
3
Andalusian Research Institute on Data Science and Computational Intelligence (DaSCI), University of Granada, 18071 Granada, Spain
4
Institute of Physics, Brandenburg University of Technology Cottbus-Senftenberg (BTU), 03046 Cottbus, Germany
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(9), 1084; https://doi.org/10.3390/electronics10091084
Submission received: 15 April 2021 / Revised: 26 April 2021 / Accepted: 28 April 2021 / Published: 3 May 2021
(This article belongs to the Special Issue Resistive Memory Characterization, Simulation, and Compact Modeling)
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Abstract

Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.
Keywords: RRAM arrays; programming algorithm; multi-level; inter-levels switching; in-memory computing; vector-matrix-multiplication RRAM arrays; programming algorithm; multi-level; inter-levels switching; in-memory computing; vector-matrix-multiplication

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MDPI and ACS Style

Pérez, E.; Pérez-Ávila, A.J.; Romero-Zaliz, R.; Mahadevaiah, M.K.; Pérez-Bosch Quesada, E.; Roldán, J.B.; Jiménez-Molinos, F.; Wenger, C. Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing. Electronics 2021, 10, 1084. https://doi.org/10.3390/electronics10091084

AMA Style

Pérez E, Pérez-Ávila AJ, Romero-Zaliz R, Mahadevaiah MK, Pérez-Bosch Quesada E, Roldán JB, Jiménez-Molinos F, Wenger C. Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing. Electronics. 2021; 10(9):1084. https://doi.org/10.3390/electronics10091084

Chicago/Turabian Style

Pérez, Eduardo, Antonio Javier Pérez-Ávila, Rocío Romero-Zaliz, Mamathamba Kalishettyhalli Mahadevaiah, Emilio Pérez-Bosch Quesada, Juan Bautista Roldán, Francisco Jiménez-Molinos, and Christian Wenger. 2021. "Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing" Electronics 10, no. 9: 1084. https://doi.org/10.3390/electronics10091084

APA Style

Pérez, E., Pérez-Ávila, A. J., Romero-Zaliz, R., Mahadevaiah, M. K., Pérez-Bosch Quesada, E., Roldán, J. B., Jiménez-Molinos, F., & Wenger, C. (2021). Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing. Electronics, 10(9), 1084. https://doi.org/10.3390/electronics10091084

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