Constraints on Bit Precision and Row Parallelism for Reliable Computing-in-Memory

Abstract

Computing-in-memory (CIM) with emerging non-volatile resistive memory devices has demonstrated remarkable performance in data-intensive applications, such as neural networks and machine learning. A crosspoint memory array enables naturally parallel computation of matrix–vector multiplication (MVM) in the analog domain, offering significant advantages in terms of speed, energy efficiency, and computational density. However, the intrinsic device non-ideality residing in analog conductance state distorts the MVM precision and limits the application to high-precision scenarios, e.g., scientific computing. Yet, a theoretical framework for guiding reliable computing-in-memory designs has been lacking. In this work, we develop an analytical model describing the constraints on bit precision and row parallelism for reliable MVM operations. By leveraging the concept of capacity from information theory, the impact of non-ideality on computational precision is quantitively analyzed. This work offers a theoretical guidance for optimizing the quantized margins, providing valuable insights for future research and practical implementation of reliable CIM.

1. Introduction

Over the past decade, extensive research has focused on emerging memory technologies [1,2,3], such as resistive random-access memory (RRAM) devices, which offer significant advantages in high area efficiency, fast switching speed, and low power consumption compared to conventional CMOS-based memories, etc. [4]. Notably, they are non-volatile (a feature rare in traditional memories) and allowed to be programmed in an analog manner, through continuous modulation of their internal state variables [5]. These capabilities are critical for emerging computing paradigms [6,7,8], as substantial research has demonstrated their significant advantages in accelerating matrix–vector multiplication (MVM) operations. This acceleration, in turn, enables faster processing of numerous data-intensive tasks, including neural network inference and training, as well as recommendation systems [9,10,11,12], and shows promise for extension to dynamic collaborative adversarial domain adaptation network, residual frequency attention regularized network, and other deep learning-based methods [13,14,15]. It has also contributed to high-precision scenarios, such as scientific computing (Figure 1a) [16,17] and signal processing [18,19].

A crosspoint RRAM array is illustrated in Figure 1b. By leveraging Ohm’s and Kirchhoff’s laws for multiplication and addition, respectively, it performs in situ MVM computations in the analog domain. Thus, it not only solves the problem of significant overhead for data movement in traditional digital approaches [20] but also reduces the computational complexity from O(N²) to O(1) [21]. In the MVM circuit, digital-to-analog converters (DACs) are used to provide input voltages (vector V) to the word lines of the RRAM array, the matrix G is encoded as the conductance values of the device cells, then the currents on the bit lines (vector I) represent the MVM product result in real time. To read out the MVM result, the currents are usually converted by transimpedance amplifiers (TIAs) and subsequently quantized by analog-to-digital converters (ADCs).

Despite the notable advantages in terms of computational parallelism, integration density, and low latency, the analog MVM operation is fundamentally more susceptible to non-ideality than digital counterparts [22,23]. In particular, the multi-level conductance programming capability is limited by the reduced readout margin due to inherent device variations and fluctuations, as illustrated in Figure 1c. The device non-ideality is reasonably abstracted as a normal distribution of conductance [24,25,26]. As a result, when participated in the analog MVM operation, the non-idealities would be accumulated and eventually limit the computing precision, otherwise lead to quantization errors during output digitization. While such errors may be tolerated in neural networks due to the robustness provided by nonlinear activation functions, their presence becomes problematic in high-precision tasks such as scientific computing and signal processing, posing a significant challenge for high-precision analog computing systems. Therefore, performing rigorous precision analysis of analog MVM is crucially important.

According to the basic statistical principles, the output current distribution should scale with $\sqrt{N_{ROW}}$ (where N_Row is the number of cells involved in MVM computation) [27], but the precise quantitative relationship remains unexplored. A recent study examined the deviation in output current caused by the device’s low-conductance state (which is not strictly zero), ultimately affecting computational accuracy [28]. However, this work primarily focused on 1-bit precision inputs and lacked a comprehensive analysis of multi-bit inputs, limiting its applicability and generalizability. Here, we develop an analytical model describing the input-output precision relationship of the analog MVM circuit. It captures the inherent limitations imposed by hardware constraints and non-ideality characteristics, shedding light on the fundamental trade-off between bit precision and row parallelism. The capacity concept in information theory is utilized as a quantitative tool to evaluate the impact of non-ideality distribution on output precision, and thus measuring the degradation behavior of analog MVM precision.

2. MVM Product Result Precision Model

2.1. Definition of Physical Quantities

To study the precision of the analog MVM result in Figure 1b, we define that precision of the input voltage V is C_V bits (with N_V levels), and precision of the device conductance matrix G is C_G bits (with N_G levels). C_OUT represents the precision of the MVM result per operation cycle, corresponding to the number of current states that needs to be quantized by the ADC. It is worth noting that, although the conductance range varies significantly across various RRAM devices (or broadly other nonvolatile resistive memory devices, e.g., phase change memory), the absolute value of these physical quantities should not affect the modeling result. It is well known that, in the ideal case, when N_ROW rows in the array are simultaneously turned on, the nominal output precision of MVM is

C_OUT = C_V + C_G + log₂N_ROW

(1)

Equation (1) has been frequently used to guide the selection of ADCs and the determination of quantization interval in existing studies [29,30,31], especially on the field of microarchitecture design, which is understandable, as objects at architecture level are abstracted. However, in practical, the individual discrete conductance levels are never ideal, rather they follow specific distributions, as illustrated in Figure 1c, which, in turn, should change the effectiveness of Equation (1).

2.2. MVM Output Precision Model

To perform MVM output precision analysis, we assume that all voltage and conductance levels are distributed uniformly in their ranges, respectively, and that all levels of each variable follow a normal distribution with the same standard deviations (σ_V and σ_G) [32]. The levels are normalized with respect to the lowest level, namely the means of all levels (μ_V and μ_G) are positive integers within the ranges 1 to N_V and 1 to N_G, respectively. As DAC is a much more mature technology, the voltage input V it provides is relatively stable with a small non-ideality distribution. For simplicity, we first assume the ideal voltage input (σ_V = 0) and analyze only the impact of non-ideal conductance levels on MVM precision. Figure 2a illustrates such a consideration for two specific cases, in each of which the non-ideal conductance vector G = [N(μ_G1, σ_G1²), N(μ_G2, σ_G2²), …, N(μ_GN, σ_GN²)], where N(μ, σ²) represents the normal distribution, is multiplied by an ideal voltage vector V = [μ_V1, μ_V2, …, μ_VN]. According to basic statistical principle, the resulting MVM product currents should also normal distribution, with each element dictated by

I = Σ_i N(μ_Viμ_Gi, μ_Vi²σ_Gi²),

(2)

where Σ represents the summation of currents through all RRAM devices, and the subscript i = 1, 2, …, N represents the index of the RRAM device through which the current is accumulated. When the non-ideal input voltage is taken into account, the product of these two distributions results in a more complex distribution for the current output. However, the maximum distribution still occurs only when all elements of the voltage and conductance vectors reach their respective maximum values. Specifically, this is represented as σ_I² = N_ROW(σ_V²σ_G² + N_V²σ_G² + N_G²σ_V²). Notably, when σ_V = 0, the analysis corresponds to the ideal voltage input case shown in Figure 2a.

It is revealed that the standard deviation of the MVM product current is controlled by the input voltages, in addition to the device conductance variation σ_G. In the worst-case scenario, all voltage inputs μ_V are assumed with the maximum value N_V, and the resulting current vector is I = Σ_i N(N_Vμ_Gi, N_V²σ_G²), the standard deviation of MVM current is σ_I = $\sqrt{N_{ROW}}$N_Vσ_G. To accurately quantize two adjacent current levels with ADC, there should be no overlap between the two distributions. Under the 3σ (4σ) criteria with 99.73% (99.99%) probability, the following inequality should be satisfied:

$$k\sqrt{N_{ROW}}NV\sigma G<1/2$$

(3)

where k is 3 or 4. Equation (3) reflects the constraint on bit precision σ_G and row parallelism N_ROW. The results for 99.73% (corresponding to using 3σ as the criterion) and 99.99% quantized accuracy (4σ criterion) are calculated, respectively.

Figure 2b illustrates these constraints according to Equation (3). The maximum number of row parallelism N_ROW is greatly restricted by the voltage input precision N_V and the non-ideality characteristics σ_G of the device. When the input voltage is limited to the simplest 1-bit case and the conductance distribution is confined to 1% (percent of the device’s maximum conductance), N_ROW can reach 64. However, as the conductance distribution deteriorates, for example, under parameter conditions where σ_G = 3~5%, which is a common range of metal-oxide RRAM devices [33,34], N_ROW will quickly drop below 10. For example, when the input voltage is 1-bit and σ_G = 4%, the maximum allowable row parallelism is merely 4. When the input voltage is 3 bits, multi-row MVM computations with N_ROW less than 4 achieve at least 3σ accuracy, only if the condition of σ_G = 1% is met. This result underscores again the importance of accounting for non-ideal factors when implementing high-precision MVM computations on current RRAM devices.

In addition to RRAM, a variety of emerging non-volatile memory (NVM) technologies—such as magnetoresistive random-access memory (MRAM), phase-change memory (PCM), and ferroelectric field-effect transistors (FeFETs)—have also been explored for MVM applications. MRAM offers exceptional endurance (up to 10¹⁵ cycles), but its narrow resistance window limits its suitability for multi-bit storage and analog computing [35]. PCM is among the most mature NVM technologies at advanced fabrication nodes, yet it suffers from relatively high read/write currents and power consumption [36,37]. FeFETs, in contrast, feature lower write currents and reduced power consumption, which significantly enhance energy efficiency in programming computational units [38,39]. However, like RRAM, FeFETs also face challenges in endurance, particularly in scenarios requiring frequent weight updates.

Our proposed model serves as a mathematical abstraction of the MVM process. Crucially, the output precision depends solely on the statistical characteristics of input noise and device variability, rather than on any specific memory type. As such, the model applies broadly to MVM implementations that rely on analog programming and operate under fundamental circuit laws—such as Ohm’s and Kirchhoff’s laws. It can be directly applied to resistive memory devices like PCM and MRAM, which follow similar analog computing paradigms. For non-resistive devices such as FeFETs, although the underlying switching mechanism is based on threshold voltage modulation, the core assumptions of the model remain valid. These devices can be treated as special cases—such as binary-state (1-bit) systems—within the same analytical framework. Therefore, our method retains its applicability and provides meaningful insights into precision degradation and design constraints across a wide range of NVM-based MVM architectures.

3. Information Loss in Non-Ideal MVM

Equation (3) discloses the constraints for producing distinguishable MVM output levels. The increase in memory precision and row parallelism would eventually cause overlaps between neighboring MVM result levels, for which the use of ADC according to Equation (1) becomes invalid. To obtain reliable, error-free ADC outputs, the bit precision of the ADC can be reduced to increase the margin between neighboring levels [40]. However, this approach is mostly empirical and lacks theoretical investigation. To measure the precision loss in non-ideal MVM caused by nonideality distribution, we adopt information capacity to quantify the degradation in computational precision by utilizing the concept of information entropy (a measure of the uncertainty or randomness in the information theory). It should also help gain a deeper understanding of how non-ideality and computational errors impact the overall performance of the system. Previous works [41] have modeled the storage problem in memory devices as a communication problem, in which storage capacity is represented by information capacity. Similarly, the MVM process can also be interpreted within the framework of information theory, where the precision of computation and the system’s ability to handle and transmit information are closely related to information capacity.

We performed a series of numerical simulations to comprehensively evaluate the effects of the input bits, bit precision and row parallelism under practical conditions. The parameters are presented in

Table 1. Model parameters, including input bits, bit precision, and row parallelism.

Parameters	CV	CG	σV	σG	NROW
Value Range	[1, 2, 3] Bit	[1, 2, 3] Bit	[0.1, 0.3, 0.5]%	[3, 5, 10]%	4, 8, 16, 32, 64

. The input voltage V and conductance G were all set to [1, 2, 3] bits, with their respective non-ideality distributions ranging from [0.1, 0.3, 0.5]% and [3, 5, 10]% based on data disclosed in the literature [32,42]. In addition, the number of rows (N_ROW) considered across the range [4, 8, 16, 32, 64]. The information capacity is defined as

C_OUT = −ΣP(i)log₂P(i),

(4)

where P(i) represents the probability of each possible level. Considering that ADCs design typically assumes a uniform quantization of the analog MVM results over the full dynamic range, we described the MVM result levels as being uniformly distributed (namely P(i) = 1/N_VN_GN_ROW). There is C_OUT = −ΣP(i)log₂P(i) = log₂N_VN_GN_ROW = C_V + C_G + log₂N_ROW, that is, Equation (4) is reduced to Equation (1). In the non-ideal case, the probability P(i) associated with different current levels will be different. Additionally, each current level transitions from a discrete level to a continuous distribution (corresponding to i changing from a positive integer to a continuous variable).

Figure 3a illustrates the case of C_V = C_G = 2 Bits, with its parameters specified in the graph. Specifically, by running 10⁶ times simulations, we obtained the occurrence probability of each individual level, corresponding to the ideal output case. Based on these ideal individual levels, non-idealities were introduced to each input to generate the normal distribution for each level. It is evident that the distribution of each state inevitably has some overlap. Moreover, since the occurrence of the minimum or maximum levels is relatively infrequent, the overall output distribution closely approximates a normal distribution. There are some works [31,40] that use lower-precision ADCs and discard quantization for these extreme cases, with results showing that the overall output is only minorly affected. However, for reliable high-precision MVM computation, all output levels should be covered in the consideration. Therefore, each level is normalized so that the area under each curve is the same (Figure 3b). Because the distribution is wider when the current output is larger, the corresponding peak value is lower.

Subsequently, the output capacity C_OUT is computed using Equation (4) to quantitatively assess the output precision loss. As shown in Figure 4a, the yellow plane represents the ideal precision, C_IDEAL, under ideal conditions as calculated by Equation (1), while the red polyline connects the actual capacity values obtained under various parameter settings, illustrating how precision changes as those parameters vary. It can be seen that as σ_G increases, C_OUT decreases rapidly. Although raising N_ROW can boost C_OUT, it eventually saturates and diverges from C_IDEAL. We also examined the impact of σ_V on output precision and found that, within a hypothetical range, it has a virtually negligible effect on C_OUT. Figure 4b shows the precision loss resulting from increased σ_G and N_ROW, which clearly demonstrates the limits on bit precision and row parallelism required to prevent precision degradation.

4. Discussion

We have systematically investigated output precision under different row parallelism settings and non-ideal input distributions (both voltage and conductance). As shown in Figure 5, when non-ideal factors are small, increasing input precision and row parallelism improves output precision almost described by Equation (1). However, as the variances of the voltage and conductance distributions increase, the output precision measured via information theory capacity rapidly decreases and eventually saturates, highlighting inherent constraints on bit precision and row parallelism for any input combination.

While the above results are obtained with the consideration of normalizing output levels, we have also considered the scenario with unnormalized levels (Figure 6), which show that the overall capacity is significantly reduced, mainly due to potential inconsistencies between states. In other words, the probability of an extreme value (either large or small) appearing in the output state is extremely low, leading to a reduction in information content and a corresponding decrease in capacity contribution. In addition, the overall normal distribution will also mask the capacity loss caused by other factors, making the impact of the bit numbers or fluctuations in conductance and voltage distribution less apparent.

Finally, considering that the assumption of normal distribution may not hold under closed-loop write–verify methods, where the resulting conductance distributions tend to deviate from normality, we have extended our analysis by introducing two additional models: (1) a simple uniform distribution model and (2) a mixed distribution model that combines a weighted superposition of uniform and normal distributions. Since repeated multiplication and addition operations on uniform distributions also broaden their effective width, the maximum output level remains a valid representation of the worst-case scenario. As a result, the analytical and simulation methodologies presented previously are still applicable. We performed numerical simulations to evaluate whether all output states could be reliably distinguished. The results are shown in Figure 7, formatted consistently with Figure 2b. Specifically, Figure 7a presents the uniform distribution case G~U(μ_G − σ_G, μ_G + σ_G), while Figure 7b shows a representative case of the mixed model (G~αU(μ_G − σ_G, μ_G + σ_G) + βN(μ_G, σ_G²), with α = 2β = 2/3). Compared with the baseline results under the normal distribution in Figure 2b, the impact of σ_G is more moderate in the uniform and mixed distribution models. These findings indicate that using a write–verify programming scheme can substantially enhance row parallelism and increase the bit precision achievable per RRAM cell.

5. Conclusions

In this work, we have investigated the sensitivity of analog-domain MVM computation to input voltage bit precision, device conductance precision, and row parallelism—all of which contribute to output precision loss. Building on this, we conducted a comprehensive analysis to examine how bit precision and row parallelism influence computational accuracy. Furthermore, we expanded the scope of our model by discussing its applicability to both resistive (e.g., PCM, MRAM) and non-resistive (e.g., FeFET) memory technologies. By introducing a mixed uniform–normal distribution model under write–verify programming conditions, we significantly enhanced the generalizability and robustness of our framework for diverse application scenarios. We also applied information-theoretic concepts to quantitatively evaluate output precision degradation. The results of our analysis establish rigorous fabrication requirements and highlight the need for high-precision write–verify schemes across various emerging memory technologies. Additionally, our findings emphasize the importance of high-resolution ADC design in analog computing systems and provide theoretical guidance for determining ADC quantization margins—ultimately contributing to the design and optimization of precise, efficient, and practically viable MVM systems.