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Electronics
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Computing-in-Memory Devices and Systems
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Computing-in-Memory Devices and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (1 August 2022) | Viewed by 22429

Special Issue Editors

Dr. Mariagrazia Graziano

E-Mail Website
Guest Editor
Department of Applied Science and Technology (DISAT), Politecnico di Torino, 10129 Torino, Italy
Interests: nanocomputing; nanoelectronics; microelectronics; VLSI
Dr. Fabrizio Riente

E-Mail Website
Guest Editor
Department of Electronics and Telecommunications, Politecnico di Torino, 10129 Torino, Italy
Interests: spintronics; in-memory computing; beyond-CMOS technologies; ferromagnetic spintronics; field-coupled technologies; EDA tools for beyond-CMOS; emerging computing devices
Dr. Giovanna Turvani

E-Mail Website
Guest Editor
Department of Electronics and Telecommunications, Politecnico di Torino, 10129 Torino, Italy
Interests: nanocomputing; digital electronics; EDA tools for beyond CMOS; magnetism; emerging computing devices; high-level device modeling; quantum computing; microwave imaging

Special Issue Information

Dear Colleagues,

Computation-in-memory refers to computing systems where the memory is placed as close as possible to the processing systems. The reduced amount of data transfer significantly improves the application performance, reducing the overhead involved in accessing the main memory.

The term “in-memory” refers to the capability of executing simple logic operations within the memory. An architecture based on computing-in-memory has several benefits, mainly related to the possibility of executing some operations locally without wasting energy and time for transferring data from the memory to the computational units.

To implement computing-in-memory systems, emerging non-volatile memory technologies are preferred to significantly reduce standby leakage power. Resistive random-access memory (RRAM), phase-change memory (PCM), ferroelectric FETs, and spin-based memories are just some examples.

The purpose of the proposed Special Issue on Computing-in-Memory Devices and Systems is to provide a comprehensive view of recent advances in devices that combine memory and computing capabilities, system architectures, and algorithms based on new advances in computer architecture and applications. Topics of interest for this Special Issue include, but are not limited to:

  • Non-volatile memory solutions with computing capabilities;
  • Novel circuit design solutions for computing-in-memory;
  • Computing-in-memory applications and architectures;
  • EDA tools for the design and benchmarking of computing-in-memory architectures;
  • Novel electronic devices that show computing-in-memory capabilities;
  • Device modeling.

Dr. Mariagrazia Graziano
Dr. Fabrizio Riente
Dr. Giovanna Turvani
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Non-volatile memory
  • MRAM
  • RRAM
  • Nano-computing
  • Memristor
  • Ferroelectric
  • Spin transfer torque
  • Voltage-controlled magnetic switching
  • Spin–orbit torque
  • Phase-change memory
  • Skyrmions
  • Computing-in-memory
  • Monolithic 3D devices
  • EDA Tools for design
  • Computing-in-memory architectures
  • Device modeling

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Published Papers (6 papers)

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Research

10 pages, 1759 KiB  
Article
Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory
by Zupei Gu, Huidong Zhao, Xiaoqin Wang, Shushan Qiao and Yumei Zhou
Electronics 2022, 11(9), 1376; https://doi.org/10.3390/electronics11091376 - 26 Apr 2022
Cited by 1 | Viewed by 2236
Abstract
To increase the throughput of computing-in-memory (CIM) designs, multi-row read methods have been adopted to increase computation in the analog region. However, the nonlinearity created by doing so degrades the precision of the results obtained. The results of CIM computation need to be [...] Read more.
To increase the throughput of computing-in-memory (CIM) designs, multi-row read methods have been adopted to increase computation in the analog region. However, the nonlinearity created by doing so degrades the precision of the results obtained. The results of CIM computation need to be precise in order for CIM designs to be used in machine learning circumstances involving complex algorithms and big data sets. In this study, a low computing leakage, wide-swing output compensation circuit is proposed for linearity improvement in such circumstances. The proposed compensation circuit is composed of a current competition circuit (as dynamic feedback of the bitline discharge current), a current mirror (to separate the result capacitor and provide charge current), and an additional pull-down circuit (for better precision in high voltage results). Measurements show that by applying our method, an almost full-swing output with 51.2% nonlinearity decrement compared with no compensation can be achieved. Power consumption is reduced by 36% per round on average and the computing leakage current, after wordlines are deactivated for 1 ns, is reduced to 55% of that when using conventional methods. A figure of merit (FOM) is proposed for analog computing module evaluation, presenting a comprehensive indicator for the computation precision of such designs. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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11 pages, 3378 KiB  
Article
Novel In-Memory Computing Adder Using 8+T SRAM
by Soonbum Song and Youngmin Kim
Electronics 2022, 11(6), 929; https://doi.org/10.3390/electronics11060929 - 16 Mar 2022
Cited by 7 | Viewed by 4516
Abstract
Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8+T SRAM [...] Read more.
Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8+T SRAM IMC circuit based on 8+T differential SRAM (8+T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8+T SRAM-based IMC approximate adder, which are based on the 8+T SRAM IMC circuit. The 8+T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8+T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8+T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8+T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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32 pages, 710 KiB  
Article
Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories
by Fabrizio Ottati, Giovanna Turvani, Guido Masera and Marco Vacca
Electronics 2021, 10(18), 2291; https://doi.org/10.3390/electronics10182291 - 17 Sep 2021
Cited by 3 | Viewed by 4245
Abstract
The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. [...] Read more.
The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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25 pages, 15040 KiB  
Article
Robust Circuit and System Design for General-Purpose Computational Resistive Memories
by Felipe Pinto and Ioannis Vourkas
Electronics 2021, 10(9), 1074; https://doi.org/10.3390/electronics10091074 - 1 May 2021
Cited by 6 | Viewed by 3105
Abstract
Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts [...] Read more.
Resistive switching devices (memristors) constitute a promising device technology that has emerged for the development of future energy-efficient general-purpose computational memories. Research has been done both at device and circuit level for the realization of primitive logic operations with memristors. Likewise, important efforts are placed on the development of logic synthesis algorithms for resistive RAM (ReRAM)-based computing. However, system-level design of computational memories has not been given significant consideration, and developing arithmetic logic unit (ALU) functionality entirely using ReRAM-based word-wise arithmetic operations remains a challenging task. In this context, we present our results in circuit- and system-level design, towards implementing a ReRAM-based general-purpose computational memory with ALU functionality. We built upon the 1T1R crossbar topology and adopted a logic design style in which all computations are equivalent to modified memory read operations for higher reliability, performed either in a word-wise or bit-wise manner, owing to an enhanced peripheral circuitry. Moreover, we present the concept of a segmented ReRAM architecture with functional and topological features that benefit flexibility of data movement and improve latency of multi-level (sequential) in-memory computations. Robust system functionality is validated via LTspice circuit simulations for an n-bit word-wise binary adder, showing promising performance features compared to other state-of-the-art implementations. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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11 pages, 1652 KiB  
Article
A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM
by Jeong Hwan Choi, Young-Ho Gong and Sung Woo Chung
Electronics 2021, 10(5), 623; https://doi.org/10.3390/electronics10050623 - 8 Mar 2021
Cited by 3 | Viewed by 3177
Abstract
Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy [...] Read more.
Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy of the data movements. However, due to the additional transistors, the CiM SRAMs suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile, monolithic 3D (M3D) integration enables fine-grained 3D integration, reducing the 2D wire length in small functional units. In this paper, we propose a BNN accelerator (BNN_Accel), composed of a 9T CiM SRAM (CiM_SRAM), input buffer, and global periphery logic, to execute the computations in the binarized convolution layers of BNNs. We also propose CiM_SRAM with the subarray-level M3D integration (as well as the transistor-level M3D integration), which reduces the wire latency and energy compared to the 2D planar CiM_SRAM. Across the binarized convolution layers, our simulation results show that BNN_Accel with the 4-layer CiM_SRAM reduces the average execution time and energy by 39.9% and 23.2%, respectively, compared to BNN_Accel with the 2D planar CiM_SRAM. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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15 pages, 3900 KiB  
Article
Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search
by Luca Gnoli, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch and Mariagrazia Graziano
Electronics 2021, 10(2), 155; https://doi.org/10.3390/electronics10020155 - 12 Jan 2021
Cited by 15 | Viewed by 3452
Abstract
In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required [...] Read more.
In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation. Full article
(This article belongs to the Special Issue Computing-in-Memory Devices and Systems)
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