Next Article in Journal
Real-Time Monte Carlo Optimization on FPGA for the Efficient and Reliable Message Chain Structure
Previous Article in Journal
SAND/3: SDN-Assisted Novel QoE Control Method for Dynamic Adaptive Streaming over HTTP/3
Article Menu

Export Article

Open AccessArticle

A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

1
SoC Development Group, SK Hynix Memory Solutions, San Jose, CA 95134, USA
2
School of Electrical Engineering, University of Ulsan, Ulsan 44610, Korea
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(8), 865; https://doi.org/10.3390/electronics8080865
Received: 8 June 2019 / Revised: 22 July 2019 / Accepted: 30 July 2019 / Published: 5 August 2019
(This article belongs to the Section Circuit and Signal Processing)
  |  
PDF [1285 KB, uploaded 8 August 2019]
  |  

Abstract

Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study memory that can perform computation as well as store data within a generic memory array in a non-Von Neumann architecture way. Memory array can innately perform NOR operation that is functionally complete and thus realize any Boolean functions like inversion (NOT), disjunction (OR) and conjunction (AND) operations. With theoretical exploration of memory array performing Boolean computation along with storing data, we demonstrate another potential of memory array with a test chip fabricated in a 90 nm logic process. Measurement results confirm valid in-situ memory logic operations in a 32-kbit memory system that successfully operates down to 135 mV consuming 130 nW at 750 Hz, reducing power and data traffic between the units by five orders of magnitude at the sacrifice of performance. View Full-Text
Keywords: memory logic operation; embedded memory; eDRAM; SRAM; ultra-low power; subthreshold operation memory logic operation; embedded memory; eDRAM; SRAM; ultra-low power; subthreshold operation
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Hwang, M.-E.; Kwon, S. A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS. Electronics 2019, 8, 865.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Electronics EISSN 2079-9292 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top