Bitwise Logical Operations in VCMA-MRAM

Abstract

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder.

1. Introduction

In conventional von Neumann computer architectures, the limited data bandwidth and data transfer between the processor and the memory consume high energy and latency, causing significant degradation of the system’s performance and efficiency. These issues being called “memory wall” and “power wall” are causing unprecedented challenges for traditional computing to handle big data [1,2,3]. To overcome these issues, in-memory processing (IMP) paradigm has been proposed for incorporating a limited number of processing units inside the memory [4]. This paradigm pre-processes the raw data and transfers only intermediate results to the processor instead of moving all the raw data. This paradigm improves performance by reducing the power and data transfer bandwidth overhead courtesy of simple logic operations in the memory. However, these paradigms are rather complex and costly because of the manufacturing of the performance-optimized processing units and the density-optimized memory on the same chip. Furthermore, the scaling of complementary metal-oxide-semiconductor (CMOS) devices is becoming challenging due to associated static and dynamic power dissipation [5]. Therefore, researchers are exploring other computer architectures by utilizing new emerging technologies (spintronics [6], memristors [7], carbon nanotube field-effect transistors (CNFETs) [8], and nanowire field-effect transistors (NWFETs) [9], etc.) to enhance the performance of the computing systems.

Magnetic-based logic devices have become a promising alternative to CMOS logic devices in dealing with the aforementioned issues. Magnetic domain walls [10], magnetic vortexes [11], magnetic skyrmions [12], and magnetic tunnel junction (MTJ) [13] have nowadays become a central area of research due to the achievements in the science and technology towards miniaturization of devices into the nanometer length scale. The MTJ offers low-power consumption, non-volatility, and high endurance making them an ideal candidate for designing processors and memories in combination with CMOS technology [14,15,16,17,18,19,20,21,22]. An MTJ is a non-volatile device that can store 1-bit of data depending upon its state. Figure 1a shows a typical MTJ structure comprising two relatively thick ferromagnetic layers (a fixed layer and a free layer) separated by a relatively thin tunnel barrier layer. When the fixed and the free layers have the same magnetic direction, as shown in Figure 1b, the MTJ shows a lower resistance. On the contrary, when the magnetic directions of both layers are anti-parallel, as shown in Figure 1c, the MTJ shows a higher resistance. The tunnel magnetoresistance (TMR) ratio characterizes the resistance difference and is defined by the following equation:

$$TMR=\frac{R_{AP}-R_P}{R_P}\times 100$$

(1)

where ($R_{AP}$) and ($R_P$) are the MTJ’s resistances in anti-parallel and parallel states, respectively. If the difference between the resistances in parallel and anti-parallel is significant, it shows higher TMR and readability. In this paper, we examined the switching characteristics of the VCMA-assisted STT switching based on the Landau–Lifshitz–Gilbert (LLG) equation. The proposed scheme has the advantage of the deterministic switching state. The LLG equation [23,24,25,26] is given by:

$$\frac{1+{\alpha }^2}{\gamma }·\frac{dM}{dt}=-M\times H{}_{eff}\left(V\right)-\alpha ·M\times (M\times H{}_{eff}\left(V\right))+\frac{\hslash PJ}{2e{t}_F{M}_s}·M\times (M\times M{}_P)$$

(2)

where M is the magnetization vector of the free layer, $H{}_{eff}\left(V\right)$ is the voltage-dependent effective magnetic field, P is the spin polarization factor, ℏ is the reduced Planck’s constant, J is the switching current density, $M{}_P$ is fixed layer’s magnetization vector, and e is the electron charge. $H{}_{eff}\left(V\right)$ consists of different field components that affect the free layer [25].

$$H{}_{eff}\left(V\right)=H{}_{ext}+H{}_d+H{}_{th}+H{}_{K\perp eff}\left(V\right)$$

(3)

$$H{}_{K\perp eff}\left(V\right)=(0x,0y,\left(\frac{2K_i\left(V\right)}{{\mu }_0{M}_s{t}_F}\right)m_{z}z)$$

(4)

where $H{}_{ext}$ is the external magnetic field, $H{}_d$ is the demagnetization field, $H{}_{th}$ is the thermal field, $H{}_{K\perp eff}\left(V\right)$ is the voltage-dependent effective perpendicular anisotropy field, ${\mu }_0$ is the permeability, m = [$m_x$, $m_y$, $m_z$] is the magnetization moment, and [x, y, z] is the unit vector.

Several methods have been discussed in the literature to change the switching states of an MTJ. For instance, spin-transfer torque (STT) [23], spin Hall effect (SHE) [24], voltage-controlled magnetic anisotropy (VCMA) [25], STT-assisted SHE [24], VCMA-assisted STT [25], and VCMA-assisted SOT [27]. The conventional STT switching-based MTJ has poor write endurance and suffers from high switching energy as charge current flows through the MTJ stacks [28]. To overcome these issues, a three-terminal SOT switching-based MTJ has been introduced where write and read paths are separated by adding a heavy metal layer under MTJ’s free layer. This isolation significantly improves the reliability of the device since the write current now flows through the heavy metal and generates SOT and SHE to switch the magnetization of the MTJ’s free layer [27,29]. However, an additional in-plane magnetic field is required to achieve deterministic switching for the MTJ. Another emerging write mechanism is VCMA which lowers the energy barrier and switches the magnetization by applying a voltage across the MTJ [30]. Reference [31] discusses the basic concepts of the approximate computing (AC) paradigm and focuses on the design and testing of integrated circuits for AC-based systems. A survey on AC is discussed in [32] to provide researchers with knowledge of how AC approaches work and to promote more study in order to make AC the standard computing paradigm in upcoming systems. A progressive scaling scheme for STT-RAM arrays is presented in [33] that reduces the power consumption at the cost of minor quality degradation. Reference [34] provides a summary of the challenges involved in designing energy-efficient IoT edge devices and summarizes recent studies that have suggested potential solutions to these challenges. Reference [35] reports a circuit that performs Read/NOT, AND/NAND, OR/NOR, Sum, and carry operations. It consists of eight MTJs and eleven MOSFETs excluding the writing circuit for MTJs in its logic tree. Reference [18] presents a circuit that performs all the basic logic operations such as NOT, NAND/AND, OR/NOR, and memory read. The hardware requires only six MTJs in its logic tree excluding the writing circuit.

This paper presents a fully non-volatile hybrid MTJ/CMOS logic-in-memory computing-based multi-functional circuit that performs all the basic logic operations such as Read/NOT, AND/NAND, OR/NOR, and arithmetic operation SUM (1-bit approximate adder with 75% accuracy for sum and accurate carry out) by a slight modification using the control signals. All the simulations have been performed in 45 nm CMOS technology with VCMA-MTJ compact model [25] using the HSPICE simulator. The proposed multi-functional circuit will be the main building block of the future MTJ-based processors where CMOS transistors will be replaced by hybrid MTJ/CMOS or only MTJ. The rest of the paper is organized as follows. Section 2 covers the basics of the VCMA-MRAM bank. Section 3 demonstrates the working principle of the proposed multi-functional circuit. Simulation results are discussed in Section 4. Section 5 finally concludes the paper.

2. Fundamentals of VCMA-MRAM

The schematic diagram of the VCMA-MRAM bank is illustrated in Figure 2. A conventional bit cell consists of one MTJ and one transistor; both are in series and an array of bit-cells is designed with multiple word-lines, source-lines, and bit-lines [36]. The spintronic memory bank contains a bit-cell array, a sense amplifier, a word-line driver, a write driver, a row/column decoder, and an input/output interface. The row and column decoder are used to select a particular bit cell according to its row and column address. The data in the MTJs are written by passing shaped voltage pulse through a write driver [37]. The shaped voltage pulse changes the magnetization state of the free layer of the MTJ or can say data is written in the bit-cell. In this paper, the circuit is designed by selecting five bit cells from the memory array in which three bit cells are connected to one arm of a differential sense amplifier and the other two bit cells are connected to the other arm. The implementation and working principle of other peripheral circuits are beyond the scope of this paper.

3. Proposed Multi-Functional Circuit

The schematic diagram of the proposed logic-in-memory-based multi-functional circuit is shown in Figure 3. The hybrid MTJ-CMOS circuit performs all the basic logic operations such as Read/NOT, AND/NAND, OR/NOR, and an arithmetic SUM operation (1-bit approximate adder with 75% accuracy for sum and accurate carry out) by slight modification using the control signals illustrated in

Table 1. Operation of the control signals.

Control Signal	Operation
Ci = 0	AND/NAND
Ci = 1	OR/NOR
A = B	Read/NOT
Ci = Cinput	Approximate Adder

.

The circuit shown in Figure 3 consists of two parts: (1) sense amplifier; SRAM-based sense amplifier is cross-coupled with two inverters that sense the small voltage difference across the nodes and pulls one of its nodes to the full swing voltage level and the other one to zero in the differential manner in the sensing mode, and (2) logic tree; made up of MTJs that store input logic values in their spin. The reconfigurable MTJs in the left arm of the sense amplifier uses the VCMA-assisted STT switching mechanism while the MTJs in the right arm of the sense amplifier have resistances, RL1 and RL2 that are fixed and both the MTJs are in low resistance mode. In order to function the circuit correctly, the net resistance of the right arm should be in between RL‖RL‖RH and RH‖RH‖RL, hence, is fixed at RL‖RL. Additionally, the TMR of the circuit must be greater than 100%. The multi-functional circuit is a dynamic circuit that works in two phases: (1) pre-charge phase, and (2) evaluate phase. In the pre-charge phase, when Clk = 0, all the transistors turn ON except the transistor N3; output nodes are pre-charged to supply voltage minus the threshold voltage of the PMOS transistors. In evaluate phase, when Clk = 1, all the transistors turn ON except the transistor P2; based on the inputs logic values stored on the MTJs and one of its output nodes is discharged to zero through a lower resistance path and pulls the other output node to a full supply voltage, VDD.

The mode of the circuit is controlled by the left arm’s MTJs as mentioned in Table 1. When the MTJ Ci is at a low logic value (offers high resistance), the circuit performs two inputs AND/NAND operations between inputs logic A and logic B, gives simultaneously AND and NAND logic values to the output nodes OUT_L and OUT_R, respectively. When the control signal (Ci) is kept at a high logic value then the circuit performs 1-bit OR and NOR operations between inputs logic A and logic B. The output nodes OUT_L and OUT_R give OR and NOR logical values, respectively. The circuit acts as a logical Read/NOT operation when the MTJ_A and MTJ_B store the same logic values that are considered to be the input to the gate irrespective of the values of the MTJ Ci. The output node OUT_L and OUT_R give logical NOT values and read the data, respectively. Moreover, the circuit performs arithmetic SUM operation; the MTJ_A, and the MTJ_B are one-bit inputs to the adder, and the carry from the previous bit is fed to the MTJ Ci. The operations are performed among the inputs and hence logical SUM (Asum) with 75% accuracy and carry output (Cout) with 100% accuracy as per the truth

Table 2. Truth table of the proposed 1-bit Approximate Full Adder.

A	B	Ci	Rleft	Rright	Asum	Cout
0	0	0	RH‖RH‖RH	RL‖RL	1	0
0	0	1	RH‖RH‖RL		1	0
0	1	0	RH‖RL‖RH		1	0
0	1	1	RH‖RL‖RL		0	1
1	0	0	RL‖RH‖RH		1	0
1	0	1	RL‖RH‖RL		0	1
1	1	0	RL‖RL‖RH		0	1
1	1	1	RL‖RL‖RL		0	1

are stored in output nodes OUT_L and OUT_R, respectively.

To understand the operation of the circuit with more clarity, let’s consider that the inputs MTJ A store logical value 1, MTJ B store the logical value 0, and the carry from the previous bit is applied to the MTJ Ci i.e., high logic value. Therefore, the total resistance of the left arm is RL‖RH‖RL = 11.40 KΩ and the right arm resistances, RL1 and RL2 are in low resistance mode, hence, it offers a resistance of RL‖RL = 13.25 KΩ as illustrated in the seventh row of Table 2. Consequently, the output node OUT_L discharges faster than the output node OUT_R. Hence, OUT_L is at zero voltage level while the OUT_R node is at a full swing supply voltage. Likewise, the rest of the combinations can be explained.

4. Simulations and Discussion

The simulations of the proposed circuit have been performed in 45 nm CMOS technology using predictive technology model (PTM) and VCMA-assisted STT switching mechanism at VCMA coefficient value of 105 fJV⁻¹m⁻¹ using VCMA-MTJ compact model [25] with HSPICE simulator in order to validate its functionalities as well as its robustness against the counterpart circuits [18,35]. The comparison circuits are also simulated with the same MTJ and CMOS model for fair comparison which is illustrated in

Table 3. Performance metrics of the multifunctional circuit and its counterpart circuits (T = 300 K, TMR = 208, RL = 26.5 K, RH = 81.7 K).

	CKT1 [18]			CKT2 [35]				Proposed Circuit
Parameter	Read/NOT	AND/NAND	OR/NOR	Read/NOT	AND/NAND	OR/NOR	Sum/Cout	Read/NOT	AND/NAND	OR/NOR	ASum/Cout
Sensing delay (ps)	20.35/27.21	27.35/27.45	27.57/27.20	103.57/95.09	73.43/63.92	84.63/73.88	84.27/73.81	31.27/25.90	30.43/37.46	31.36/39.58	37.84/31.35
Sensing energy (aJ)	13.00	13.36	13.35	26.68	28.60	28.29	56.39	12.87	12.78	13.48	13.11
Sensing power (10${}^{-10}$ W)	26.01	26.72	26.70	53.37	57.21	56.58	112.78	25.74	25.57	26.97	26.23
Switching delay (ns)	0.975	1.00	1.00	0.899	0.948	1.031	0.910	0.979	0.900	0.906	0.900
Switching energy (aJ)	0.93	3.58	3.25	89.14	85.97	98.37	238.74	2.39	3.099	2.281	3.923
EDP (1 × 10${}^{-29}$)	26.45	36.53	36.80	276.32	210.00	239.41	475.19	40.2	47.87	53.35	49.60

.

The transient response of the logic operation NOT is shown in Figure 4. Figure 5 presents the transient response of the logic operations AND, NAND, OR, and NOR. Similarly, Figure 6 demonstrates the arithmetic SUM operation (approximate adder) for all possible input combinations. A clock voltage pulse of 0.9 V peak to peak amplitude and 8 ns period with a duty cycle of 50% is applied for all the operations. When CLK = 0; reconfigurable MTJs are in the writing phase. The MTJs store logic values by applying a shaped voltage pulse (Vpulse) of amplitude 0.8 V for VCMA switching followed by a lower voltage (for STT switching) of +0.55 V for high logic value or −0.55 V for lower logic value as shown in Figure 4. When CLK = 1; the circuit is in the evaluation phase so it gives the logical NOT values as NOT (A) of applied input A as shown in Figure 4 and logical AND/NAND, OR/NOR values of inputs logic values A and B as shown in Figure 5. The input-output waveforms of the approximate adder (SUM) are illustrated in Figure 6 according to the truth table shown in Table 2.

The performance metrics of the proposed circuit along with the previously existing circuits CKT1 [18], and CKT2 [35] are tabulated in Table 3. The sensing power of the proposed circuit is slightly less than the CKT1 and less than half than the CKT2. Moreover, the proposed approximate adder consumes 4.3 times less power than the exact adder of the CKT2. This is due to the presence of two sense amplifiers and additional transistors in the reconfigurable MTJs’ path of the CKT2. The CKT2 calculates Sum and Cout separately while the proposed circuit uses one sense amplifier for both and calculates ASum and Cout simultaneously, but the accuracy of the sum is 75% and the carry output is accurate. The delay depends upon the net resistance of discharging path of a circuit. The CKT1 has all the six MTJs, that are reconfigurable in the logic tree: three of the MTJs are parallelly connected to one arm of the sense amplifier and the other three MTJs are to the other arm in a complementary manner. Hence, the net maximum resistance of the CKT1’s discharging path always be less than the proposed circuit’s maximum resistance of discharging path. So the delay of the CKT1 is roughly about 20% less as compared to the proposed circuit although the CKT1 lags behind in terms of the number of operations. Both the CKT2 and the proposed circuit perform all the basic logic operations and addition operations while the CKT1 only performs basic logic operations. So, the better counterpart to the proposed circuit is CKT2, but in this case, the delay of the proposed circuit is winning and far less than the CKT2–delay of the CKT2 is 2.3 times of the proposed circuit. The switching energy depends upon the number of reconfigurable MTJs and operations of the circuits or arrangement of the MTJs and the transistors in the logic tree that’s why it varies hugely from one circuit to others. The energy-delay product (EDP) of the CKT2 is 9.5 times the proposed circuit.

5. Conclusions

This paper presents a logic-in-memory multi-functional circuit that performs the main logic functions like Read/NOT, AND/NAND, OR/NOR, and an arithmetic SUM function (approximate full adder) with 75% accuracy and Cout with 100% accuracy by using the control signals. It requires less hardware (five MTJs in the logic tree, six transistors in the sense amplifier) as compared to the previous works. The proposed circuit’s approximate adder is 2.3 times faster than CKT2’s exact adder and saves energy by about 330%. Overall, the proposed adder EDP is remarkably greater than the exact adder of the CKT1. The fully non-volatile functionality of the proposed circuit lowers the energy consumption over the buses that connect the memory to the processor, has no need for refreshing energy, and also reduces the leakage power to near zero.