Robust Hybrid Computing-in-Memory System Based on 2T-2C and 4T-2C FRAM Cells

Abstract

The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified.

1. Introduction

In the ever-evolving landscape of computational technology, the pursuit of optimal performance and efficiency has propelled the exploration of groundbreaking paradigms. At present, the traditional von Neumann architecture has gradually failed to meet the requirements. In the von Neumann architecture, the storage and processing of data are separated, and the data is transmitted between the memory and the processor, which has several disadvantages. First of all, the access speed of the memory is far less than the processing speed of the processor, so the overall computing speed of the system will be limited by bandwidth, resulting in the actual computing power of the processor being far lower than the theoretical computing power. It is difficult to meet the needs of fast computing of intelligent chips; this problem is called the “memory wall” problem. By increasing the bandwidth and clock frequency, the performance of the processor can be improved to a certain extent, but at the same time, this will lead to large power consumption and integration costs, so its scalability is seriously limited. Secondly, in the von Neumann architecture, the storage and processing of data are separated, and the data are frequently transferred between the storage module and the computing module, which generates huge transmission power consumption; this is also known as the “power wall” problem [1,2,3,4]. For example, Nvidia research reports that floating-point operations require about 200 times more data transfer power than data processing power [5]. These “memory wall” and “power wall” problems have become major bottlenecks of conventional von Neumann architectures. Therefore, the evolution of in-memory computing has emerged as a transformative force, reshaping traditional approaches to data processing. In-memory computing diverges from conventional architectures by executing computations directly within the storage medium, eliminating the need for frequent data transfers between storage and processing cells.

A variety of computing-in-memory (CiM) architectures with different storage media have been proposed here. In 2019, Static Random-Access Memory (SRAM)-based CiM architectures were proposed, which can realize the convolutional operation of neural networks with binary weights [6]. In 2020, there have been proposed a CiM chip based on Resistive Random-Access Memory (RRAM), which can greatly improve computing power while reducing computing delay [7]. In 2021, some scholars proposed a Dynamic Random-Access Memory (DRAM) CiM architecture, which can realize the acceleration of neural networks [8]. Moreover, several different in-memory computing architectures have been reported recently, such as in-memory computing architectures based on SRAM, DRAM, Flash, RRAM, Phase Change Memory (PCM), Ferroelectric Field Effect Transistor (FeFET), and Magnetoresistive Random-Access Memory (MRAM) [9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30].

As a storage cell for CiM applications, Ferroelectric Random-Access Memory (FRAM) based on ferroelectric capacitors has advantages over other storage media. Compared to DRAM and SRAM, ferroelectric memory is non-volatile memory with the ability to preserve data in the event of power failure, which facilitates low-power design. Compared with DRAM, FRAM has better reliability for computing-in-memory. FRAM has lower read and write power consumption than MRAM, Flash, and PCM, which is consistent with the low power consumption requirements of computing-in-memory. FRAM has faster read and write speed than Flash and PCM, which has the potential to increase the speed of CiM accelerators. Compared with FeFET, FRAM has a mature process, which is more conducive to the formation of mature products. FRAM based on Hf_0.5Zr_0.5O₂ has the advantages of high compatibility with CMOS technology [31,32,33,34,35,36,37,38,39,40].

In this work, we propose a bitwise in-memory computing architecture based on 2T-2C and 4T-2C FRAM cells. We use the intrinsic characteristics of 2T-2C FRAM cells to complete computations by activating multiple word lines (WLs). The two vectors to be added are stored in the same column to avoid carry shifting and minimize data transfer. The proposed FRAM CiM technique supports column-parallel operation, while the larger 4T-2C cells are selectively deployed only in dedicated compute rows to limit area overhead.

To summarize, the key highlights of this work are:

• A hybrid 2T-2C/4T-2C FRAM CiM architecture is proposed. The input operands, intermediate data, and output results are stored and processed within the same FRAM subarray, thereby reducing data movement between the memory array and external processing units. The conventional 2T-2C cells are retained as the primary storage and computing elements to preserve the density of the FRAM array.
• A 4T-2C FRAM cell with normal and cross-coupled bit-line access paths is introduced to support in-array inversion and complementary-result write-back. While the conventional 2T-2C cells perform majority-derived AND and OR operations through multi-row activation, the selectively embedded 4T-2C cells provide NOT functionality. Their combination enables NAND, NOR, functionally complete Boolean logic, and majority-based full-addition operations within the FRAM subarray.
• HSPICE simulations indicate that the proposed FRAM CiM architecture provides a large sensing margin and stable sensing under the evaluated global PVT conditions: the minimum bit-line voltage difference reaches 337 mV during triple-row activation and 214 mV during quintuple-row activation, respectively. In addition, PVT simulations demonstrate less than 4.62% variation in the bit-line voltage difference over temperatures ranging from −40 °C to 125 °C.
• The proposed architecture provides ADC-free bitwise computing with binary inputs and outputs, thereby avoiding the associated conversion-circuit overhead. The larger 4T-2C cells are selectively deployed only in dedicated computing rows, while conventional 2T-2C cells are used for dense data storage and majority computation. An 8 × 8 hybrid FRAM CiM prototype, consisting of six rows of 2T-2C cells and two rows of 4T-2C cells, was fabricated in a 180 nm CMOS process for physical implementation and basic array-level functional verification.

2. Background of 2T-2C FRAM Cell

The structure diagram of the 2T-2C FRAM cell is shown in Figure 1a. It consists of two transistors and two ferroelectric capacitors, one end of which is connected to the plate line (PL) and the other end is connected to a pair of complementary bit-lines (BL, BLN) through a transistor [41]. The ferroelectric capacitor stores data according to its hysteresis loop, as shown in Figure 1b [42]. When writing data “1” to the 2T-2C FRAM cell, a high voltage is applied at WL, ferroelectric capacitors A₁ and A₂ are connected to BL and BLN, and then a high voltage pulse is given at PL, while a high voltage pulse is given at BL and a voltage of 0 V is applied at BLN (Figure 2a). At this time, the hysteresis loop of A₁ first reaches 2, and when the high voltage pulse on BL ends, the hysteresis loop of A₁ stays at 3. The hysteresis loop of A₂ reaches 4 first, and after the high voltage pulse on PL ends, the hysteresis loop of A₂ stays at 1. When reading data “1”, a high voltage is applied at WL, ferroelectric capacitors A₁ and A₂ are connected to BL and BLN, and then a high voltage pulse is given at PL, while both BL and BLN are subjected to 0 V. At this time, the hysteresis loop of A₁ starts at 3, and when the PL high voltage pulse is applied, the hysteresis loop of A₁ reaches 4, releasing charge Q₁ and forming voltage V₁ on BL. The hysteresis loop of A₂ starts at 1, and when the PL high voltage pulse is applied, the hysteresis loop of A₂ reaches 4, releasing charge Q₂ and forming voltage V₂ on BLN. Since Q₁ is larger than Q₂ and V₁ is larger than V₂, the sense amplifier will pull V₁ up to VDD and pull V₂ down to 0 V, finally resulting in a voltage of VDD on BL and 0 V on BLN, thus reading data “1”. When writing data “0”, the operation is the same as when writing data 1, except that a 0 V voltage is applied to BL and a high voltage pulse is applied to BLN (Figure 2b). Reading the data “0” results in a voltage of 0 V on BL and VDD on BLN. The 2T-2C FRAM cell is fast-reading and non-volatile, making it suitable for in-memory computing.

3. Bit Computing-in-Memory of FRAM Cell

3.1. Majority-Based Computing Using 2T–2C FRAM Cell

In the CiM architecture of FRAM, we perform bit operations by simultaneously activating multiple 2T-2C cells. Triple-row activation simultaneously asserts the WLs of three 2T-2C cells on the same bit-line. Although the stored inputs and sensed outputs are binary and no ADC/DAC conversion is required, simultaneous row activation first produces analog BL/BLN voltages through ferroelectric charge sharing. The sense amplifier then resolves the differential voltage into a binary result, so the operation depends on the available sensing margin rather than on a strictly digital internal data path. In order to analyze the bit-line voltage during triple-row activation, let us assume that the transistors and bit-lines behave ideally (no resistance). Under these assumptions, the charge-sharing voltages follow V = Q/C: the charge released onto BL or BLN forms the numerator, and the total capacitance on that line forms the corresponding denominator. The first and second fractions in Equation (1) therefore give V_BL and V_BLN, respectively, and their difference defines the signed bit-line deviation ΔV ≡ V_BL − V_BLN:

$$\begin{array}{c}{V}_{\mathrm{B}\mathrm{L}}={\displaystyle \frac{(k_1\times C_1+k_2\times C_2)\times V_{\mathrm{D}\mathrm{D}}}{k_1\times C_1+k_2\times C_2+C_b}}\\ V_{\mathrm{B}\mathrm{L}\mathrm{N}}={\displaystyle \frac{(k_2\times C_1+k_1\times C_2)\times V_{\mathrm{D}\mathrm{D}}}{k_2\times C_1+k_1\times C_2+C_b}}\\ \Delta V\equiv V_{\mathrm{B}\mathrm{L}}-V_{\mathrm{B}\mathrm{L}\mathrm{N}}={\displaystyle \frac{C_b\times V_{\mathrm{D}\mathrm{D}}\times (k_1-k_2)\times (C_1-C_2)}{(k_1\times C_1+k_2\times C_2+C_b)\times (k_2\times C_1+k_1\times C_2+C_b)}}\end{array}$$

(1)

Here, V_BL and V_BLN are the charge-sharing voltages on BL and BLN, respectively; ΔV ≡ V_BL − V_BLN; k₁ and k₂ are the numbers of activated cells whose positive-polarization capacitors are connected to BL and BLN, respectively (k₁ + k₂ = 3 for triple-row activation); C₁ and C₂ are the effective read capacitances of the positively and negatively polarized ferroelectric capacitors, respectively; C_b is the parasitic/load capacitance on each bit-line; and V_DD is the applied high read voltage. Because C₁ > C₂, ΔV < 0 for k₁ = 0 or 1 and ΔV > 0 for k₁ = 2 or 3. Thus, the sense amplifier resolves BL high when at least two activated cells are positively polarized and resolves BL low when at least two are negatively polarized.

A schematic of the triple-row activation is shown in Figure 3. First, data “1” is written to two of the three 2T-2C cells, and data “0” is written to one of the three 2T-2C cells (Figure 3a,b). Then, high voltage is applied to WL₁, WL₂ and WL₃ at the same time, and the data in the three 2T-2C cells are read out with a PL pulse. In this case, V_BL = 2V₁ + V₀ and V_BLN = 2V₀ + V₁, where V₁ and V₀ denote the single-cell readout contributions of positive and negative polarization, respectively. Then we turn on the enable signal of the sense amplifier. Since V₁ is larger than V₀, the voltage on BL is pulled up to VDD and the voltage on BLN is pulled down to 0 V. It is clear under triple-row activation, the readout data will be determined by the majority data in the three activated 2T-2C cells. For example, when two data “1” and one data “0” are stored in three FRAM cells, the read data will be “1”; when two data “0” and one data “1” are stored in three FRAM cells, the data read out is “0”. For the data A, B and C stored in the 2T-2C FRAM cell, if we read them out simultaneously, the voltage on the corresponding bit-line can be expressed as:

$$\mathrm{O}\mathrm{U}\mathrm{T}=\mathrm{C}\left(\mathrm{A}+\mathrm{B}\right)+\overline{\mathrm{C}}\left(\mathrm{A}\mathrm{B}\right)$$

(2)

The single-bit AND and OR operations are performed by simultaneously activating the word lines of three 2T-2C FRAM cells. If the value of C is set to 1, a single-bit OR computation can be achieved. The values of A, B and C are read out at the same time, and after resolution by the sense amplifier, the voltage on BL represents A + B (Figure 4a). If the value of C is set to 0, a single-bit AND computation can be achieved. The values of A, B and C are read out at the same time, and after resolution by the sense amplifier, the voltage on BL represents AB (Figure 4b).

Furthermore, a multi-bit bitwise operation in FRAM 2T-2C cells was designed. We define the calculation result as being equal to the majority data in the activated 2T-2C cells, referred to as the majority operation. The majority calculation can be defined as a function in which the result follows the majority of the input data. Therefore, we can perform multi-bit consecutive computations in the FRAM 2T-2C cells through the majority formula:

$$S=ABC=Majority(A,B,C,0,0)$$

(3)

$$S=A+B+C=Majority (A,B,C,1,1)$$

(4)

$$S=ABCD=Majority \left(A,B,C,D,0,0,0\right)$$

(5)

$$S=A+B+C+D=Majority (A,B,C,D,1,1,1)$$

(6)

It is clear that the FRAM CiM architecture can flexibly calculate multi-bit consecutive AND and OR computations. The consecutive 3-bit computation can be performed through quintuple-row activation (Figure 5), while the consecutive 4-bit computation can be achieved via septuple-row activation (Figure 6). This capability extends the supported operand width of the proposed FRAM CiM architecture through additional row activation.

3.2. 4T–2C FRAM Cell for In-Array Inversion

Although conventional 2T-2C FRAM cells can efficiently implement majority-derived AND and OR operations, their fixed differential connections to BL and BLN prevent the polarity of a sensed intermediate result from being reversed and directly written back into the array. To address this limitation, we propose a 4T-2C FRAM cell with normal and cross-coupled bit-line access paths, as shown in Figure 7. Ferroelectric capacitor A₁ is connected to BL through transistor T₁ and to BLN through transistor T₃, whereas ferroelectric capacitor A₂ is connected to BLN through transistor T₂ and to BL through transistor T₄. The normal access transistors T₁ and T₂ are controlled by WL, while the cross-coupled access transistors T₃ and T₄ are controlled by WLN.

During normal read/write operation, WL is asserted while WLN remains deasserted, such that A₁ and A₂ are connected to BL and BLN, respectively, as in a conventional 2T–2C FRAM cell. During the inverting write-back operation, WL is deasserted and WLN is asserted together with the corresponding plate-line pulse. The connections between the ferroelectric capacitors and the complementary bit-lines are thereby exchanged: A₁ is connected to BLN, while A₂ is connected to BL. Consequently, when the sense amplifier produces D on BL and its complement on BLN, the cross-coupled access paths write the reversed differential polarity into the 4T–2C cell. A subsequent normal read operation therefore outputs the complementary result on BL. Accordingly, the NOT path maps a stored input X to its complement in three steps: (1) normally sense X so that BL/BLN carries X/$\overline{\mathrm{X}}$; (2) with WL deasserted, assert WLN together with the corresponding PL pulse to cross-write the sensed differential into the 4T-2C cell; and (3) deassert WLN and normally read the cell through WL, which yields $\overline{\mathrm{X}}$ on BL.

The proposed 4T–2C cell enables in-array NOT computation and complementary intermediate-result storage without routing the sensed result to a dedicated external CMOS inverter. In the hybrid FRAM CiM architecture, conventional 2T–2C cells provide dense storage and majority-derived AND/OR operations, whereas the 4T–2C cells are selectively employed where inversion or complementary write-back is required. Since AND, OR, and NOT form a functionally complete Boolean basis, their combination enables NAND, NOR, and arbitrary Boolean logic operations within the FRAM subarray, while also supporting the complementary intermediate data required by the proposed full-adder implementation.

3.3. Functionally Complete Logic in the Hybrid FRAM Subarray

The NAND/NOR mapping in Figure 8 proceeds in four steps. Step 1 (operand initialization): write A and B into the first two 2T-2C cells and preset the third cell to C = 1 for NOR or C = 0 for NAND. Step 2 (majority evaluation): simultaneously assert WL₁, WL₂, and WL₃ and apply the corresponding PL pulses. After sensing, BL carries R = Majority(A, B, C), while BLN carries $\overline{\mathrm{R}}$; hence, R = A ∨ B for C = 1 and R = A ∧ B for C = 0. Step 3 (inverting write-back): while the sense amplifier holds R/$\overline{\mathrm{R}}$, keep WL₄ deasserted and assert the cross-coupled WLN₄ together with the corresponding PL pulse. D₁ is thereby connected to BLN and D₂ to BL, so the 4T-2C cell stores $\overline{\mathrm{R}}$ with respect to its normal read orientation. Step 4 (output read): deassert WLN₄ and assert the normal WL₄ to read cell D. BL then outputs $\overline{\mathrm{R}}$, giving “A NOR B” when C = 1 and “A NAND B” when C = 0.

The subarray of the FRAM CiM architecture replaces part of the 2T-2C cell in the FRAM memory array with a 4T-2C cell, which can realize all the logical operations of bits in FRAM. All input and output vectors are stored and computed in the FRAM subarray, which greatly reduces data transmission. The FRAM CiM subarray has the functions of storage and computing data. As a non-volatile memory, FRAM retains data with low power consumption.

4. The In-FRAM Full Adder Design

FRAM in-memory calculation involves reading the stored data by activating multiple WLs at the same time and obtaining the calculation results after amplification by the sense amplifier. Such calculations follow the majority function. In order to match the FRAM CiM subarray, we design the full adder based on the majority function. We calculate the carry-out and the sum using the following formula:

$$C_i=Majority (A_i,B_i,C_{i-1})$$

(7)

$$S_i=Majority (A_i,B_i,C_{i-1},\overline{Ci},\overline{Ci})$$

(8)

where A_i and B_i are the input data, C_i−1 is the input carry signal, C_i is the output carry signal, and S is the sum signal.

Under the FRAM CiM architecture, the full addition computation needs to be performed in two steps. The WLs corresponding to A, B and C_i−1 are first activated, and the carry output C_i is calculated according to the majority formula (Figure 9a). It should be noted that the calculated C_i needs to be stored in two different 4T-2C cells to get the $\overline{{\mathrm{C}}_{\mathrm{i}}}$ data needed for the next calculation. Then, WLs corresponding to A, B, C_i−1 and two $\overline{{\mathrm{C}}_{\mathrm{i}}}$ are activated, and the calculated result sum is obtained on BL according to the majority formula (Figure 9b).

The data readout of the 2T-2C FRAM cell is destructive, so we adopt the method of copying data to avoid destructive readout of FRAM. Data in the same column of the FRAM subarray can be transferred from one row to another, as shown in Figure 10. In a column of 2T-2C FRAM, data “1” is stored in cell A. First, a high voltage is applied to WL₁, and the data “1” in A is read out with the voltage pulse of PL₁. After resolution by the sense amplifier, the voltage on BL is VDD and the voltage on BLN is 0 V. A high voltage is applied to WL_n of the target M cell, and voltage pulses are applied to PL₁ and PL_n to write data “1” back to A and also to M. Finally, WL₁ and WL_n are turned off. Through the above operations, the data “1” is successfully copied from A to M without destroying the original data stored in A. Accordingly, one row-to-row replication comprises two sequential array-operation phases: (i) destructive readout and sensing of the source cell and (ii) simultaneous restoration of the source cell and writing of the destination cell. Each replication event, therefore, adds one read/sense phase and one restore/write phase before the subsequent CiM operation, and its energy overhead consists of the energy consumed by these two phases.

Therefore, the FRAM CiM subarray is divided into three parts: data rows, result rows and compute rows (Figure 11). The data rows store the original input vectors, which are then copied to the compute rows for computation. This approach ensures that the original input data is not destroyed during the read-out process. The computed results are stored in the result rows, awaiting invocation or retrieval.

Based on the aforementioned FRAM CiM subarray, multi-bit full addition operations can be implemented. In the multi-bit full addition calculation, the lowest carry output (C₀) and sum (S₀) are calculated first. Then, C₁, S₁, C₂, S₂… are calculated. Taking the 8-bit full addition in the FRAM CiM architecture as an example (Figure 12), first, the input vectors A and B are stored in the data rows (Figure 12a). Then, A₀ and B₀ are copied from the data rows to the compute rows, and data “0” is written in the compute rows as the input carry (Figure 12b). It should be noted that A₀ and B₀ are copied to two different FRAM cells, and the data “0” should be written to two different FRAM cells. This is because A₀, B₀ and “0” need to be read out twice in the subsequent calculation. A₀, B₀ and data “0” are then read out and calculated to get the output carry C₀. The C₀ is stored in the 2T-2C FRAM cell corresponding to the A₀, B₀, and data “0” that were read out previously. $\overline{{\mathrm{C}}_0}$ is stored in two different 4T-2C cells (Figure 12c). A₀, B₀, “0” and the two $\overline{{\mathrm{C}}_0}$ are then read out to calculate the lowest sum signal (S₀). The calculated S₀ is written to the result rows. At this time, three 2T-2C FRAM cells in the compute rows are still storing C₀ data, which are used as the input carry to calculate the output carry of the higher bit (Figure 12d). The serial calculation in FRAM memory ensures high accuracy in multi-bit calculation. Under this full addition computing architecture, the signal addresses in the compute rows are switched cyclically, making it convenient to design serial full addition computing. The input vector, output vector and all calculations are carried out in the FRAM computing-in-memory subarray, which reduces data transmission and cache, thereby reducing the transmission power consumption of the chip. Destructive readout during the bit-serial multi-bit full-adder operation in Figure 12 is managed by performing majority reads on replicated operands in the compute rows, rather than on the original operands in the data rows. Within each BL/BLN column, bit positions are processed serially from the least to the most significant bit. Before bit i, the replication operation in Figure 10 copies A_i and B_i into designated compute rows while restoring the source cells; two working copies of A_i, B_i, and C_i−1 are prepared because these values are used in both the carry and sum evaluations. The first destructive majority read consumes one copy set and produces C_i, which is immediately written into the vacated 2T-2C working cells, while its complement is written into two 4T-2C cells. The second destructive majority read uses the remaining operand/carry copies and the two complementary carry values to produce S_i, which is written into the result row. The stored C_i then serves as the input carry for bit i + 1, and the same compute rows are overwritten by the next operand copies and reused. Thus, destructive readout is confined to temporary compute-row copies, while the original multi-bit operands remain preserved in the data rows. Replication increases the number of polarization-switching events because each destructive read is followed by restoration. For context, HfZrO_x FRAM has demonstrated endurance of up to 10¹² cycles at 27 °C and 10¹⁰ cycles at 120 °C [43], providing a device-level reference for the additional access stress.

Within each column, successive full-adder bit positions are processed serially according to the schedule in Figure 12, whereas independent columns can share the same WL/PL command sequence. Accordingly, the 512 × 1024 organization in Figure 13 illustrates algorithmic column-level parallelism under uniform WL/PL delivery and adequate per-column sensing margin: 1024 independent 8-bit additions follow the same scheduled row-operation sequence as one 8-bit addition. This operation-count equivalence does not imply array-size-independent latency, energy, or sensing robustness because these quantities depend on array dimensions and interconnect loading, as discussed in Section 5. In Figure 13, A0–A1023 and B0–B1023 denote operand words, while sum0–sum1023 denotes the corresponding result words. The active column count and operand width depend on subarray partitioning and the target application.

5. Results and Discussion

To evaluate the functionality and PVT-dependent sensing stability of the proposed FRAM CiM circuit, HSPICE simulations were performed using a 180 nm CMOS process. All the ferroelectric capacitance models adopted the Lim model [44,45]. The circuit simulation power supply voltage, capacitance area and transistor parameters are shown in

Table 1. Critical parameters in circuit simulation of FRAM computing-in-memory architectures.

Parameters	Value
Technology	180 nm
Cell Capacitance Area	0.77 um × 0.78 um
Supply Voltage VDD	3.3 V
Access Transistor W/L	1500 nm/400 nm

.

Table 2. Main parameters of the FeCAP Lim model.

Parameter	Value
Coercive voltage, Vc	1.2106 V
Thermal voltage, Vo	0.3839 V
Saturation polarization, Ps	15.42165 μC/cm2
Linear capacitance density, Ccommon	3.81964 μF/cm2

lists the principal parameters of the FeCAP Lim model.

Figure 14a shows the transient simulation curve of the triple-row activation operation. In this operation, two of the three activated 2T-2C cells store data “1” and the others store data “0” (the voltage difference between BL and BLN is minimized). The three WLs are activated, and a high-voltage pulse is applied to the corresponding PL to read the cells. Figure 14b shows the transient simulation curve of the quintuple-row activation operation. In this operation, three of the five activated 2T-2C cells store data “1” and the others store data “0” (the voltage difference between BL and BLN is minimized). The sense amplifier resolves the ΔV between BL and BLN and drives the complementary bit lines to VDD and 0 V, respectively. Therefore, the voltage difference between BL and BLN determines the accuracy and functionality of FRAM in-memory calculation. The ΔV of the triple-row activation operation proposed in this paper can reach 337 mV, which is much higher than the ΔV of the DRAM in-memory calculation circuit (only 65 mV,

Table 3. Comparison of ΔV of bit-lines during triple-row activation in FRAM and DRAM (the stored data is “110”).

FRAM	DRAM
ΔV = 337 mV	ΔV = 65 mV

) [8]. These simulation results indicate a larger sensing margin than that of the referenced DRAM CiM circuit under the evaluated conditions.

In the practical application of the circuit, a load capacitance is typically present on each bit-line (bit-line capacitor) of the FRAM CiM subarray. The matching of bit-line capacitance in the FRAM CiM subarray is studied in this paper. Figure 15 shows the ΔV resulting from a triple-row activation operation at 3.3 V with different bit-line capacitors when the stored data is “110”. When the bit-line capacitance is increased to 0.36 pF, the bit-line ΔV reaches a maximum of 337 mV. Continuing to increase the value of the bit-line capacitance causes the ΔV to decrease, and when the bit-line capacitance reaches 1.44 pF, the ΔV decreases to 117 mV. Figure 15 also shows the ΔV resulting from a quintuple-row activation operation at 3.3 V with different bit-line capacitors when the stored data is “11100”. When the bit-line capacitance is increased to 0.54 pF, the bit-line ΔV reaches a maximum of 215 mV. However, when the bit-line capacitance is 0.36 pF, ΔV can also reach 214 mV, which is very close to the maximum value of ΔV. Similar to the triple-row activation operation, increasing the value of the bit-line capacitance causes the ΔV to decrease, and when the bit-line capacitance reaches 1.44 pF, the ΔV decreases to 112 mV. Considering both scenarios of triple-row and quintuple-row activation operations in computational requirements, a bit-line capacitance of 0.36 pF exhibits optimal compatibility with the FRAM CiM subarray.

Array scaling introduces different parasitic loads along the two array dimensions. Increasing the number of cells sharing a BL/BLN and the associated wire length increases bit-line capacitance and distributed resistance. Under the charge-sharing relation in Equation (1), the polarization-dependent charge is resolved against this load; once Cb exceeds its operating optimum, additional capacitance reduces ΔV and increases settling time. Figure 15 directly shows this sensitivity: increasing Cb from 0.36 to 1.44 pF reduces ΔV from 337 to 117 mV for triple-row activation and from 214 to 112 mV for quintuple-row activation. These results indicate that bit-line segmentation, the sensing point, and the array dimensions must be co-optimized. Measurements of 2T-2C FeRAM circuits have likewise related bit-line capacitance to the number of connected cells and metal parasitics, while identifying the highly capacitive plate line as a major component of access timing [46].

Increasing the number of columns increases the WL fanout to access-transistor gates and the PL load presented by ferroelectric-capacitor electrodes. Their distributed RC delay produces position-dependent rise/fall times and pulse skew, so far-end cells may be activated later or experience a different effective PL pulse. Multi-row activation imposes a separate, data-dependent constraint. For an odd-N majority operation at the nearest decision boundary, the useful polarization-charge excess corresponds to one cell while the total connected capacitance grows with N; under the idealized assumptions of Equation (1), the initial differential therefore tends to decrease. This is not a universal monotonic relation with row count because operand replication or a larger majority imbalance can increase the net charge difference. The allowable activation count must satisfy the worst-case ΔV relative to sense-amplifier offset and noise, together with decoder, WL/PL-driver, timing skew, peak current, and restoration constraints; related charge-sharing CiM analyses explicitly include BL/WL resistance, capacitance, and component variation [30]. Septuple-row and higher-order operations should consequently be evaluated against the same worst-case margin criterion. Practical scale-up would therefore use segmented subarrays and short local bit lines [40], local sense amplifiers, hierarchical or repeated WL/PL drivers, and bounded multi-row activation groups.

To evaluate the sensing stability of the FRAM CiM circuit under global PVT conditions, PVT simulations were conducted by varying three critical parameters: process corners, polarization voltage, and temperature. The simulation results are summarized in

Table 4. ΔV resulting from PVT simulation during triple-row operations when the stored data pattern was “110”.

Polarization Voltage	Temperature	TT	FF	SS	SF	FS
3 V	−40 °C	306 mV	312 mV	304 mV	305 mV	303 mV
	25 °C	301 mV	303 mV	307 mV	302 mV	302 mV
	125 °C	297 mV	303 mV	291 mV	289 mV	296 mV
3.3 V	−40 °C	344 mV	345 mV	342 mV	335 mV	331 mV
	25 °C	337 mV	339 mV	344 mV	332 mV	337 mV
	125 °C	341 mV	346 mV	342 mV	334 mV	338 mV
3.6 V	−40 °C	360 mV	366 mV	359 mV	356 mV	364 mV
	25 °C	366 mV	363 mV	365 mV	358 mV	361 mV
	125 °C	364 mV	371 mV	370 mV	365 mV	370 mV

and

Table 5. ΔV resulting from PVT simulation during quintuple-row operations when the stored data pattern was “11100”.

Polarization Voltage	Temperature	TT	FF	SS	SF	FS
3 V	−40 °C	177 mV	185 mV	176 mV	175 mV	179 mV
	25 °C	177 mV	174 mV	177 mV	174 mV	179 mV
	125 °C	174 mV	170 mV	167 mV	163 mV	174 mV
3.3 V	−40 °C	212 mV	210 mV	214 mV	213 mV	211 mV
	25 °C	214 mV	207 mV	208 mV	206 mV	215 mV
	125 °C	202 mV	201 mV	198 mV	200 mV	202 mV
3.6 V	−40 °C	248 mV	256 mV	250 mV	247 mV	249 mV
	25 °C	242 mV	245 mV	246 mV	243 mV	253 mV
	125 °C	243 mV	244 mV	244 mV	234 mV	234 mV

. Specifically, Table 4 presents the PVT simulation during triple-row operations when the stored data pattern was “110”. Notably, variations in FRAM polarization voltage directly influence the polarization strength of ferroelectric capacitors, which governs bit-line voltage fluctuations. Consequently, an increase in polarization voltage leads to enhanced ΔV on the bit-line. When varying process corners and temperature in the FRAM CiM circuit, the bit-line ΔV exhibited only minor fluctuations of a few mV. Similarly, during quintuple-row activation operations with the stored data pattern “11100”, ΔV variations remained negligible under altered process corners and temperature conditions (Table 5). PVT analysis showed <4.62% ΔV variation across the evaluated temperature range (−40 °C to 125 °C) for the triple-row and quintuple-row activation operations at 3.3 V. In FRAM CiM arrays, the output signal is achieved by amplifying the bit-line ΔV through a sense amplifier. Consequently, the stability of ΔV is a direct indicator of sensing stability under the evaluated global PVT conditions. The PVT simulation results indicate stable bit-line voltage differences across the evaluated process corners, polarization voltages, and temperatures.

Figure 16 shows the layout of the 8 × 8 FRAM CiM circuit, which comprises six rows of 2T-2C FRAM cells, two rows of 4T-2C cells, and peripheral circuits. The size of the FRAM CiM circuit is 1930 um × 1080 um. SPICE simulations were conducted for the 8 × 8 FRAM CiM circuit, as shown in Figure 17. In this configuration, X₃, X₂, X₁, and X₀ represent the 4-bit address signals, Q₁–Q₈ denote the data channels, and C_EN serves as the computation enable signal. When C_EN is at a logic-low level, the simulated circuit operates in the standard read/write mode, allowing data to be written into or read from the FRAM cells. When C_EN is asserted high, the circuit enters the computing mode and performs bitwise operations on the stored 8-bit data.

To further evaluate the performance of the proposed FRAM CiM architecture, the energy consumption and calculation latency of the OR, AND, and NOT operations were extracted from transient HSPICE simulations of the 8 × 8 FRAM CiM compute-array circuit model. The simulated circuit model includes the hybrid 2T-2C/4T-2C FRAM compute array, the address decoder, word-line boosting/driver circuitry, plate-line transmission circuitry, discharge modules, bit-line data paths, and sense amplifiers. The energy consumption per bit was obtained directly from the transient HSPICE simulation of one 8-bit parallel computing operation and normalized by the eight output bits. The simulated calculation latency was extracted from the activation of the computing control signals to the stabilization of the sensed output. As summarized in

Table 6. Simulated energy consumption per bit and calculation latency for a single 8-bit OR, AND, or NOT operation in the 8 × 8 FRAM CiM compute-array circuit model.

Parameter	OR	AND	NOT
Energy Consumption	3.40 pJ/bit	3.46 pJ/bit	1.94 pJ/bit
Calculation Latency	0.599 ns	0.599 ns	1.167 ns

, the OR and AND operations exhibit nearly identical energy consumption and latency because their operation sequences are the same, with the only difference being the logic value stored in the preset 2T-2C cell. The NOT operation is performed using the cross-coupled access paths of the 4T-2C cell and requires a different operation sequence.

Figure 18 compares the simulated FRAM energy with the DDR3-interface baseline in [30]. The DDR3 result includes DRAM and DDR3-channel energy, whereas the FRAM result includes the compute array and its peripheral circuits. Both results include their respective memory-side circuitry and exclude processor energy. Across the evaluated bitwise operations, the proposed FRAM CiM architecture reduces energy consumption by 4.86×–5.90× compared with the DDR3-based design.

As a physical implementation of the proposed hybrid architecture, an 8 × 8 FRAM CiM prototype was fabricated in a 180 nm CMOS process. As shown in Figure 19a, the fabricated prototype integrates six rows of conventional 2T-2C FRAM cells, two rows of 4T-2C FRAM cells, and the associated peripheral circuits. Figure 19b shows the FPGA-based test setup, which consists of a DE2-115 FPGA board, the fabricated FRAM CiM prototype, and a dedicated test PCB. The FPGA-based setup was used to verify the basic functionality of the fabricated array, while the quantitative CiM performance results reported in this work were obtained from HSPICE simulations.

To provide a broader cross-technology context,

Table 7. Comparison with representative CiM designs for bitwise Boolean operations.

Memory Technology	Boolean Logic	Technology Node	Energy Consumption (pJ/bit)	Calculation Latency (ns)
FRAM	OR/AND/NOT	180 nm	3.40/3.46/1.94	0.599/0.599/1.167
SRAM [47]	NAND/AND/NOR/OR/XOR	45 nm	0.0293 (avg.)	3
DRAM [48]	XOR/XNOR	16 nm	0.595	149
RRAM [49]	AND/OR/XOR	65 nm	N.R.	4.9
MRAM [50]	AND/OR	28 nm	0.05943	2.5

Note: N.R. denotes not reported.

compares the proposed FRAM CiM circuit with representative Boolean CiM designs based on SRAM [47], DRAM [48], RRAM [49], and MRAM [50]. Energy consumption is expressed in pJ/bit, and calculation latency in ns.

As shown in Table 7, the proposed FRAM CiM circuit achieves calculation latencies of 0.599 ns for OR and AND and 1.167 ns for NOT. Within the reported results, these values demonstrate low computation latency despite the use of mature 180 nm technology. The short latency is mainly enabled by the 8-bit parallel operation and the direct sense-amplifier-based binary sensing path, which avoids ADC/DAC conversion. Moreover, the hybrid 2T-2C/4T-2C array provides a functionally complete OR, AND, and NOT set while retaining nonvolatile storage.

The simulated energy consumption of 1.94–3.46 pJ/bit is higher than the reported values of several comparison designs. This difference is partly attributable to the mature 180 nm technology and to the present simulation boundary, which includes the 8 × 8 compute array, word-line boosting and driver circuitry, plate-line transmission circuitry, discharge modules, bit-line data paths, and sense amplifiers.

Beyond the bitwise Boolean CiM designs summarized in Table 7, the RRAM work in [51] presents application-specific analog and hybrid-domain architectures for polynomial transformation, neural-network inference, and intelligent decision-making, whereas the PCM core in [52] implements large-scale signed analog MVM with multibit input/output conversion and drift/temperature compensation. In contrast, the proposed FRAM architecture targets functionally complete bitwise Boolean computation: conventional 2T-2C cells provide majority-derived AND/OR, selectively embedded 4T-2C cells provide in-array inversion and complementary-result write-back, and the charge-sharing/sense-amplifier path produces binary outputs without ADC/DAC conversion. Accordingly, the novelty of this work lies in the hybrid-cell FRAM organization that combines nonvolatile storage, Boolean completeness, and full-adder support within the same subarray.

6. Conclusions

This paper proposes a novel CiM architecture based on FRAM. The cell operation, circuit structure, and system architecture were designed and evaluated through HSPICE simulations. The proposed FRAM CiM architecture stores both input and output vectors within the FRAM subarray, significantly reducing cache area and transmission power consumption. Compared with volatile memories, FRAM retains stored data without periodic refresh, thereby reducing standby and data-retention energy. SPICE simulations indicate a large bit-line voltage difference of 337 mV (ΔV), which can be resolved by the sense amplifier under the evaluated conditions. PVT simulations show that the ΔV variation remains below 4.62% across the evaluated temperature range (−40 °C to 125 °C). The proposed FRAM CiM architecture supports parallel processing and provides ADC-free bitwise computing with binary inputs and outputs. Its internal computation, however, remains mixed-signal because analog BL/BLN voltage differences are formed by charge sharing and resolved by the differential sense amplifier; robustness, therefore, depends on the available sensing margin. An 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed architecture, and its basic array functionality was verified. Overall, the simulation results suggest that the proposed FRAM-based CiM architecture has potential for low-power AI acceleration, with stable sensing demonstrated across the evaluated global PVT conditions.