Chips

Test time per chip plays an essential role in manufacturing tests. Keeping a low number of test patterns becomes one of the prime objectives in concurrence with achieving the desired fault coverage. Unfortunately, finding an optimum set is an NP-hard problem. Today’s commercial ATPG tools have significantly reduced the number of test patterns to achieve a high fault coverage. However, there is still a huge gap for reducing the total pattern count, equivalent to minimizing test costs in the production phase. In this paper, we propose two novel methods to lower the test pattern count to detect all stuck-at faults in a circuit with the same or higher fault coverage as in the commercial ATPG tool, e.g., TetraMAX II. The first approach begins by applying a small set of random patterns to solve easy-to-detect faults. The remaining faults are detected by the SAT-based attack on logic locking with converting all the remaining faults into one locked circuit. Each stuck-at fault is modeled with its equivalent key gate. The second approach selects the first few patterns generated by the ATPG tool and applies the SAT attack of logic locking to determine the test patterns for detecting the undetected faults. By exploiting the overall linear iteration complexity and the exponential removal of incorrect key combinations per each SAT attack iteration, it is feasible to significantly reduce the total pattern count while maintaining the same or higher fault coverage as the ATPG counterpart. We demonstrate the effectiveness of both approaches and show that we are able to achieve a more compact test pattern set compared to a commercial ATPG tool.

This paper presents the design of a 140 GHz vector-sum phase shifter in a 28 nm CMOS process. Two variable-gain amplifiers—Gilbert cell and current-steering amplifiers—are investigated and compared. The Gilbert cell-based phase shifter controls the tail current source in a common-source amplifier. However, this configuration exhibits insufficient gain at D-band frequencies. To address this issue, we designed a current-steering variable-gain amplifier in cascode form to improve the gain performance. I/Q signals are generated by Marchand baluns and Lange couplers, and a 13-bit digital-to-analog converter enables fine bias control. Simulation results show that the current-steering phase shifter achieves up to a 4.4 dB higher gain than the Gilbert cell-based phase shifter, with an RMS gain error below 1.3 dB and an RMS phase error below 4.8° across 129–144 GHz.

This paper proposes a novel fault-tolerant routing method without creating faulty regions for 3D mesh Network-on-Chips (NoCs). Most conventional methods create faulty regions containing faulty nodes and route packets around them to reach the destinations. However, the creation of faulty regions results in low communication performance and low node utilization. To overcome the two problems, the proposed method does not create faulty regions based on the idea of predefining paths in the absence of shortest paths while allowing the passage of faulty nodes. Simulation results show that, compared with conventional methods, the proposed method reduces average latency by about 44.5% and improves node utilization rate by about 41.2% for 3D mesh NoCs of nodes.