Chips

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min. Full article

This paper presents an advanced Controller Area Network (CAN) bus transceiver designed to enhance security using frame-level authentication with the concept of a nonphysical virtual auxiliary data channel. We describe the newly conceived transceiver security features and provide results concerning the design, implementation, fabrication and test of the transceiver to validate its functionality and robust operation in the presence of systemic error sources including Process, Voltage, and Temperature (PVT) variations. The virtual auxiliary channel integrates CAN frame authentication signatures into the primary data payload via phase modulation while also providing compatibility with existing CAN protocols, interoperability with non-enhanced systems and requiring no network or software modifications. Enhanced rail converters are designed to facilitate single-rail to dual-rail data conversion and vice versa, preserving phase information and minimizing phase errors across various nonideal effects such as frequency drift, Process, Voltage, and Temperature (PVT) variations, and cable phase mismatch. This ensures reliable data transmission and robust authentication in the presence of adversarial cyberattacks such as packet injection. The receiver recovers both the CAN frame data and the security signature, comparing the latter with an authorized signature to provide a real-time “GO/NO_GO” signal for verifying packet authenticity and without exceeding the CAN clock jitter specifications. Full article

FPGAs are popular in many fields but have yet to gain wide acceptance for accelerating HPC codes. A major cause is that whilst the growth of High-Level Synthesis (HLS), enabling the use of C or C++, has increased accessibility, without widespread algorithmic changes these tools only provide correct-by-construction rather than fast-by-construction programming. The fundamental issue is that HLS presents a Von Neumann-based execution model that is poorly suited to FPGAs, resulting in a significant disconnect between HLS’s language semantics and how experienced FPGA programmers structure dataflow algorithms to exploit hardware. We have developed the high-level language Lucent which builds on principles previously developed for programming general-purpose dataflow architectures. Using Lucent as a vehicle, in this paper we explore appropriate abstractions for developing application-specific dataflow machines on reconfigurable architectures. The result is an approach enabling fast-by-construction programming for FPGAs, delivering competitive performance against hand-optimised HLS codes whilst significantly enhancing programmer productivity. Full article

Physical side-channel attacks utilize power, electromagnetic (EM), or timing signatures from cryptographic implementations during operation to retrieve sensitive information from security-critical devices. This paper provides a comprehensive review of these potent attacks against cryptographic hardware implementations, with a particular emphasis on pre-silicon leakage assessment methodologies. We explore the intricacies of cryptographic algorithms, various side-channel attacks, and the latest mitigation techniques. Although leakage assessment techniques are widely adopted in the post-silicon phase, pre-silicon leakage assessment is an emerging field that addresses the inherent limitations of its post-silicon counterpart. We scrutinize established post-silicon techniques and provide a detailed comparative analysis of pre-silicon leakage assessment across different abstraction levels in the hardware design and verification flow. Furthermore, we categorize and discuss existing pre-silicon power and electromagnetic modeling techniques for leakage detection and mitigation that can be integrated with electronic design automation (EDA) tools to automate security assessments. Lastly, we offer insights into the future trajectory of physical side-channel leakage assessment techniques in the pre-silicon stages, highlighting the need for further research and development in this critical area of cybersecurity. Full article

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma ($\mathsf{\Delta }\Sigma$) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC. Full article

With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physics properties, and are promising to be used in non-volatile memory devices. Various kinds of advanced non-volatile memory devices with semiconductor, insulator, ferroelectric, magnetic, and phase-change two-dimensional materials have been investigated in recent years to promote performance enhancement and functionality extension. In this article, the recent advances in two-dimensional material-based non-volatile memory devices are reviewed. Performance criteria and strategies of high-performance two-dimensional non-volatile memory devices are analyzed. Two-dimensional non-volatile memory array structures and their applications in compute-in-memory architectures are discussed. Finally, a summary of this article and future outlooks of two-dimensional non-volatile memory device developments are given. Full article

The analog–mixed signal simulation environment, used for verifying non-volatile memory macrocells, is presented. It has been adopted over the last decade, providing excellent results in verification coverage, efficiency, and flexibility. This methodology ensures a smooth and effective transition from full transistor/fully analog simulations to fully digital simulations while maintaining most of the environment’s features. This allows verification designers to exchange data, stimuli, and results, thereby enhancing debugging capabilities and reducing simulation time. Full article

Oxygen vacancy engineering in metal oxides is a propitious route to modulate their resistive switching properties for memory and neuromorphic applications. This review provides an account of the research works on tailoring RS behavior in oxide thin-film-based memristor devices by oxygen vacancy engineering. We discuss the recent research progress on controlling oxygen vacancy concentration in metal oxide thin films and its impact on their resistive switching properties for application in electronic memory and neuromorphic computing devices. Full article

This study introduces a rectenna, functioning as an RF envelope detector, utilizing a 16 nm bulk MOS transistor (metal-oxide-semiconductor field-effect transistor) for nonlinear detection. A circuit architecture is presented alongside a detailed design methodology and simulations. The detector efficiently demodulates a 2.4 GHz OOK (On/Off Keying) encoded signal, comprising a 32-bit word, within 320 μs. Remarkably, the circuit operates passively, requiring no voltage supply or bias current, and functions effectively with $-53$ dBm input power at the antenna. This capability enables the decoding of 32-bit unsigned integer radio packets as a wakeup radio event. The effectiveness of the envelope detector is substantiated through comprehensive simulations. Full article

This paper provides a comparative analysis of AES (Advanced Encryption Standard) and Salsa20 algorithm implementations, focusing on power consumption efficiency in passive RFID (radio-frequency identification) tags and ultra-low-power devices. The main objective of this work is to determine which of these algorithms is more suitable to operate in these types of devices. For this purpose, ASIC (application-specific integrated circuit) implementations of AES and Salsa20 based on low-power approaches were developed and their power consumption was evaluated. The results demonstrate that Salsa20 power consumption is lower than AES (about 17%), indicating that Salsa20 is a much better choice than AES for passive RFID tags. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

Datapath synthesis is a crucial step in synthesis flow and aims at globally minimizing an area by identifying shareable logic structures. This paper introduces a novel Directed Acyclic Graph (DAG)-based datapath synthesis method based on graph isomorphism and gate reconfiguration. Unlike algorithms that identify common specification logic, our approach simplifies the problem by focusing on searching for common topology. Leveraging the concept of gate reconfiguration, our algorithm extends the applicability of DAG-based datapath synthesis by transforming a topology-equivalent network into a specification-equivalent network. Experimental results demonstrate up to 23.6% improvement when optimizing the adder–subtractor circuit, a scenario not addressed by existing DAG-based datapath synthesis algorithms. Full article

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed. Full article

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well. Full article

This review is aimed at the integrated circuit design community and it explores slew-rate enhancement techniques for switched-capacitor amplifiers, with a primary focus on optimizing settling time within power constraints. Key challenges are addressed, including the selection between single-stage and two-stage amplifiers, along with the utilization of advanced circuit-level techniques for slew-rate enhancement. Presently, there exists a gap in comprehensive discussion, with reliance primarily on two Figures of Merit aimed at assessing power efficiency under specific capacitive loads. However, these metrics fail to adequately assess the performance of the existing slew-rate enhancer solutions at different values of capacitive loads. As a consequence, the designer lacks clear guidelines in practical situations. This review provides a state-of-the art mapping under a figure of merit dedicated to assess the whole settling delay, and also introduces a novel performance metric which highlights the role of the circuital architectures, regardless of external operating conditions. By offering a thorough examination, this review seeks to steer future research in switched-capacitor amplifier design, thereby facilitating informed decision-making and fostering innovation in the field. Full article

Because of the large number of parameters that interact in amplifier functions, determining dynamic regime parameters as well as the mode of function of amplifier stages is an extremely complex problem. This paper describes a LabVIEW application for studying the functioning of an amplifier in various connections. The user selects the generator’s parameters, the type of connection and its parameters, as well as the load circuit characteristics. The application can determine both the stage characteristics and the Bode characteristics. The amplifier’s stability zone, as well as its gain and phase, are determined based on these characteristics. An important advantage of this application is that the design of the amplifier stage can be created starting from some parameters that the amplifier can establish, from which the values of components can be determined. In order to validate the simulation results from the LabVIEW application, the specialized program Multisim was used, as well as experimental measurements using the Electronics Explorer Board. Both Multisim and Electronics Explorer Board can determine Bode characteristics. In both simulations and experimental amplifiers, the same schemes with the same transistor were used. The application can be used for educational purposes as well as to design an amplifier’s stage to achieve specific parameters. Full article

This paper presents a novel CMOS RF-to-DC converter for ultra-low-power wireless sensor nodes powered by RF wireless power transfer. The proposed converter achieves 10% higher power conversion efficiency than a conventional rectifier, with only a 1% increase in power consumption. The system employs a reconfigurable Dickson topology, operates on the unlicensed 868 MHz ISM band, and includes a built-in power-efficient MPPT system architecture. Experimental measurements show a maximum power conversion efficiency of 55% in the power range from −22 dBm to 0 dBm, with a power sensitivity of −22 dBm for a DC output voltage of 2.4 V. The proposed converter offers a promising solution for efficient wireless power transfer and energy harvesting in ultra-low-power wireless sensor nodes. Full article

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm²/ch, 7.16 μW/ch, 0.0168 mm²/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively. Full article

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 $\mathrm{n}\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}$ @1 kHz, small-signal power-bandwidth FoM_ss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoM_npb of 1.15 × 10⁻⁶ (($\mathrm{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}$)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications. Full article