# In-Memory Computing with Resistive Memory Circuits: Status and Outlook

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## Abstract

**:**

## 1. Introduction

## 2. RRAM Device Structure

## 3. Analog Memory Programming Techniques and Variations

#### 3.1. Program-Verify Algorithms and Device-to-Device Variations

#### 3.2. Conductance Drift and Fluctuations

## 4. RRAM Conductance Mapping Techniques

#### 4.1. Multilevel

#### 4.2. Binary

#### 4.3. Unary

#### 4.4. Multilevel with Redundancy

#### 4.5. Slicing

#### 4.6. Simulation Results

**Table 1.**Comparison of various mapping schemes, in terms of conductance range, variability-induced error and resulting maximum number of programmable bits.

Technique | ${\mathit{G}}_{\mathbf{range}}$ | ${\mathit{\sigma}}_{\mathit{\u03f5}}$ | ${\mathit{N}}_{\mathbf{max}}$ |
---|---|---|---|

Multilevel | ${G}_{max}$ | ${2}^{N}\frac{{\sigma}_{G}}{{G}_{max}}$ | $lo{g}_{2}\left(\frac{{\sigma}_{\u03f5}{G}_{max}}{{\sigma}_{G}}\right)$ |

Binary | $({2}^{N}-1){G}_{max}$ | $\sqrt{\frac{{2}^{2N}-1}{3}}\frac{{\sigma}_{G}}{{G}_{max}}$ | $lo{g}_{2}\left(\right)open="["\; close="]">1+3{\left(\right)}^{\frac{{\sigma}_{\u03f5}{G}_{max}}{{\sigma}_{G}}}2/2$ |

Unary | $({2}^{N}-1){G}_{max}$ | $\sqrt{{2}^{N-1}}\frac{{\sigma}_{G}}{{G}_{max}}$ | $2lo{g}_{2}\left(\frac{{\sigma}_{\u03f5}{G}_{max}}{{\sigma}_{G}}\right)+1$ |

Multilevel with redundancy | $M{G}_{max}$ | ${2}^{N}\frac{{\sigma}_{G}}{{G}_{max}\sqrt{M}}$ | $lo{g}_{2}\left(\frac{{\sigma}_{\u03f5}{G}_{max}\sqrt{M}}{{\sigma}_{G}}\right)$ |

Slicing | $({2}^{M}N-1){G}_{max}$ | $\frac{\sqrt{1+{2}^{2\left(\right)open="("\; close=")">\frac{N}{M}-1}}}{{\sigma}_{G}}$ | $\frac{M}{2}\left(\right)open="["\; close="]">1+lo{g}_{2}\left(\right)open="("\; close=")">\frac{{\sigma}_{\u03f5}^{2}{G}_{max}^{2}}{{\sigma}_{G}^{2}}-1$ |

## 5. Array-Level Reliability Issues

## 6. Circuit Primitives for Analog Computing

#### 6.1. MVM Accelerator

#### 6.2. Analog Closed-Loop Accelerators

#### 6.3. Analog CAM

## 7. Outlook on Memory Technologies and Computing Applications

## 8. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**A conceptual illustration of the different scales of in-memory computing. Computing relies on fundamental physical laws that are implemented in various types of memory devices and circuit designs. To perform large-scale computation, new architectures have to be developed for accelerating real world applications. New applications can also arise given the possibility of performing highly-parallel computation. The design and optimization of each different level should be performed by considering all the hierarchical stack.

**Figure 2.**RRAM structure and operation. (

**a**) RRAM device made of a metallic TE and BE, with an interposed dielectric layer. After a forming procedure it is possible to set/reset the device and switch from LRS to HRS and vice versa. (

**b**) Typical I-V curve of a RRAM device with 1T1R configuration for increasing gate voltage ${V}_{G}$ during set operation demonstrating analog programmability. Adapted from [31,38].

**Figure 3.**Crosspoint memory structure to perform analog MVM. At the intersection of each TE lines (orange) with each BE line (grey), a RRAM is placed (blue). By programming the RRAM conductance to the matrix entries of A and applying a voltage vector V on the columns, the resulting current flowing in each row j tied to ground according to Kirchoff’s law is ${I}_{j}={\sum}_{i=1}^{N}{G}_{ij}{V}_{i}$. Adapted from [29].

**Figure 4.**Analog programming with set pulses at increasing ${I}_{C}$ according to the IGPP algorithm. (

**a**) Conceptual schematic of the IGPP algorithm. (

**b**) Conductance as a function of pulse number for multiple iterations (grey lines) and the average behavior (blue). (

**c**) Cumulative distribution function (CDF) of the conductance for increasing gate voltage ${V}_{G}$. (

**d**) Standard deviation of the conductance ${\sigma}_{G}$ as a function of the average conductance G. Adapted from [51].

**Figure 5.**Analog programming with reset pulses. (

**a**) Conceptual schematic of the IRPP algorithm. (

**b**) Conductance as a function of pulse number for multiple iterations (grey lines) and the average behavior (blue). (

**c**) Cumulative distribution function (CDF) of the conductance for increasing stop voltage ${V}_{STOP}$. (

**d**) Standard deviation of the conductance ${\sigma}_{G}$ as a function of the average conductance G for IRPP and IGPP algorithms. Adapted from [51].

**Figure 6.**Program and verify algorithm. (

**a**) Conceptual schematic of ISPVA program and verify algorithm. (

**b**) Mean conductance as a function of set voltage ${V}_{TE}$ for multiple values of the gate voltage ${V}_{G}$. (

**c**) Probability density function (PDF) of programmed conductance levels. Reprinted from [43,57].

**Figure 7.**Drift and fluctuations in RRAM devices. (

**a**) Conductance as function of time for 4 different analog levels after heating at 150 °C. (

**b**) Different fluctuations’ effect as a function of time. (

**c**) Cumulative distributions of 5 programmed levels before and after annealing at T = 125 °C. (

**d**) Conceptual schematic of the neural network used to evaluate the effect of drift and its accuracy in classifying the MNIST dataset before (

**e**) and after (

**f**) annealing. Adapted from [43,58,59].

**Figure 8.**Programming mapping techniques. Conceptual representation of multilevel (

**a**), binary (

**b**), unary (

**c**), multilevel with redundancy (

**d**) and multilevel with slicing (

**e**) programming. Adapted from [51].

**Figure 9.**Comparison between analytical formula (top) and MC simulations (bottom) of standard deviation of the programming error ${\sigma}_{\u03f5}$ as a function of the number of bits N and the standard deviation of the conductance ${\sigma}_{G}$ for multilevel (

**a**,

**f**), binary (

**b**,

**g**), unary (

**c**,

**h**), multilevel with redundancy factor $M=4$ (

**d**,

**i**) and slicing in $M=2$ units (

**e**,

**j**). Adapted from [51].

**Figure 10.**Figures of merit of various programming strategies. (

**a**) Standard deviation of the overall programming error ${\sigma}_{G}$ as a function of the conductance error ${\sigma}_{G}$ assuming $N=7$ bits. (

**b**) Maximum number of bits ${N}_{max}$ as a function of the conductance error ${\sigma}_{G}$ considering a programming error ${\sigma}_{\u03f5}=1\%$. (

**c**) Bit density as a function of the conductance error ${\sigma}_{G}$. Adapted from [51].

**Figure 11.**IR drop in crosspoint arrays. (

**a**) Explicit representation of the parasitic resistance in a crosspoint array, namely the input resistance ${R}_{in}$, output resistance ${R}_{out}$ and wire resistance r. (

**b**) Memory array with current controlled memory element programmed to various saturation currents. (

**c**) Comparison of the impact of IR drop for ohmic and saturated characteristics. Reprinted from [67].

**Figure 12.**Bipolar conductance mapping and IR drop. (

**a**) Typical bipolar conductance mapping in two adjacent 1T1R columns with the positive one (red) encoding the positive part of the weights and the negative one (blue) encoding the negative part of the weights. Currents are then subtracted in the digital domain after conversion. (

**b**) To reduce the impact of IR drop, conductance representing the positive and negative weights can be summed up in the analog domain with a dedicated ST-2T2R circuit structure. Reprinted from [69].

**Figure 13.**Schematic of IMC circuits for various applications. (

**a**) MVM accelerator performing $I=AV$, where V is the input voltage vector, A is the conductance stored in the crosspoint array and I is the vector of the current in each row. (

**b**) Linear system solver performing $V={A}^{-1}I$ where I is the vector of the row input currents and V is the output vector of column voltages. (

**c**) Regression problem solver performing $v=-{\left({X}^{T}X\right)}^{-1}{X}^{T}i$ where i is the vector of the input row currents at the left crosspoint array, X is the matrix of conductances in the two crosspoint arrays and v is the output voltage of the second stage of amplifiers. (

**d**) Analog CAM cell, a range is stored in the memory conductance $M1$ and $M2$, the ML is pre-charged and an analog input is applied to the DL line. If the analog input is in the range of acceptance given by $M1$ and $M2$ the ML remains charged otherwise it discharges. Reprinted from [31,73].

**Figure 14.**Application requirements (

**a**) and figures of merit for various memory technologies with 2-terminal (

**b**) and -terminal structure (

**c**).

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Pedretti, G.; Ielmini, D.
In-Memory Computing with Resistive Memory Circuits: Status and Outlook. *Electronics* **2021**, *10*, 1063.
https://doi.org/10.3390/electronics10091063

**AMA Style**

Pedretti G, Ielmini D.
In-Memory Computing with Resistive Memory Circuits: Status and Outlook. *Electronics*. 2021; 10(9):1063.
https://doi.org/10.3390/electronics10091063

**Chicago/Turabian Style**

Pedretti, Giacomo, and Daniele Ielmini.
2021. "In-Memory Computing with Resistive Memory Circuits: Status and Outlook" *Electronics* 10, no. 9: 1063.
https://doi.org/10.3390/electronics10091063