# Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

## Abstract

**:**

## 1. Introduction

## 2. Memristive Logic

## 3. In-Memory Majority Logic

#### 3.1. V–R Majority Logic

#### 3.2. R–V Majority Logic

## 4. In-Memory One-Bit Full Adders Using Different Logic Primitives

## 5. In-Memory Eight-Bit Adders Using Different Logic Primitives

## 6. Conclusions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) 1S–1R and 1T–1R configuration of memristive memory array (

**b**) If resistance is the only state variable, a memristive logic is said to be stateful. If voltage is also used in addition to resistance, it is said to be non-stateful (

**c**) 1-bit full adder in terms of NOR gates [31], NAND gates [32,33] and majority gates [34]; Majority logic achieves less logical depth than NAND/NOR for 1-bit full adder.

**Figure 2.**Illustration of V–R majority logic. Arrow indicates the state transition, which depends on the initial state of the RRAM cell C and the voltage applied across its terminals ($A,B$); dotted lines indicate the state variable of C, which is resistance, while A and B are voltages [18].

**Figure 3.**(

**a**) In-memory majority gate proposed in [45,46]: When three rows are activated ($W{L}_{1-3}$) simultaneously in a 1T-1R array, the three resistances ${R}_{A},{R}_{B},{R}_{C}$ will be in parallel (Inputs of the majority gate $A,B,C$ are represented as resistances ${R}_{A},{R}_{B},{R}_{C}$). An ‘in-memory’ majority gate can be implemented by accurately sensing the effective resistance ${R}_{eff}$ during READ. (

**b**) NOT operation implemented with a 2:1 multiplexer at the output of the SA. With majority and NOT gate implemented as READ, multiple levels of logic can be executed by writing the data back to the array, simplifying computing to READ and WRITE operations in memory. Multiple majority gates can be executed in parallel in the memory array, thereby reducing latency of in-memory computation.

**Figure 5.**n levels of Boolean logic will require $n+x$ cycles in-memory, where x depends on the memristive logic family. It must be noted that the number of cycles required (10 cycles for NOR, NAND and 6 cycles for MAJORITY) is already optimized by executing multiple gates in parallel (see the mapping for NOR [31], NAND [49] and MAJORITY [45]).

**Figure 6.**An eight-bit parallel-prefix adder (Ladner-Fischer) has 8 logic levels of AND, OR and XOR gates. If the logic family cannot execute XOR gate, it must be expressed as NAND gates, increasing the logic levels to 12.

**Figure 7.**Eight-bit parallel-prefix adder (Ladner-Fischer) expressed as 7 levels of Majority+NOT gates. By executing multiple gates in parallel, the adder can be implemented in memory in 19 cycles, as elaborated in [46].

A | B | C | ${\mathit{M}}_{3}(\mathit{A},\mathit{B},\mathit{C})$ | $\overline{\mathit{B}}$ | ${\mathit{M}}_{3}(\mathit{A},\overline{\mathit{B}},\mathit{C})$ | ${\mathit{RM}}_{3}(\mathit{A},\mathit{B},\mathit{C})$ |
---|---|---|---|---|---|---|

0 | 0 | 0 | 0 | 1 | 0 | 0 |

0 | 0 | 1 | 0 | 1 | 1 | 1 |

0 | 1 | 0 | 0 | 0 | 0 | 0 |

0 | 1 | 1 | 1 | 0 | 0 | 0 |

1 | 0 | 0 | 0 | 1 | 1 | 1 |

1 | 0 | 1 | 1 | 1 | 1 | 1 |

1 | 1 | 0 | 1 | 0 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 1 | 1 |

**Table 2.**Precisely sensing ${R}_{eff}$ results in majority: Logic ‘0’ is LRS (10 k$\mathsf{\Omega}$) and logic ‘1’ is HRS (133.3 k$\mathsf{\Omega}$). Sense amplifier distinguishes between rows shaded grey and those that are not.

A | B | C | ${\mathit{M}}_{3}(\mathit{A},\mathit{B},\mathit{C})$ | ${\mathit{R}}_{\mathit{eff}}$ | ${\mathit{R}}_{\mathit{eff}}$ |
---|---|---|---|---|---|

0 | 0 | 0 | 0 | $\frac{LRS}{3}$ | 3.3 k$\mathsf{\Omega}$ |

0 | 0 | 1 | 0 | $\frac{HRS\xb7LRS}{LRS+2\xb7HRS}$ | 4.8 k$\mathsf{\Omega}$ |

0 | 1 | 0 | 0 | $\frac{HRS\xb7LRS}{LRS+2\xb7HRS}$ | 4.8 k$\mathsf{\Omega}$ |

0 | 1 | 1 | 1 | $\frac{HRS\xb7LRS}{HRS+2\xb7LRS}$ | 8.7 k$\mathsf{\Omega}$ |

1 | 0 | 0 | 0 | $\frac{HRS\xb7LRS}{LRS+2\xb7HRS}$ | 4.8 k$\mathsf{\Omega}$ |

1 | 0 | 1 | 1 | $\frac{HRS\xb7LRS}{HRS+2\xb7LRS}$ | 8.7 k$\mathsf{\Omega}$ |

1 | 1 | 0 | 1 | $\frac{HRS\xb7LRS}{HRS+2\xb7LRS}$ | 8.7 k$\mathsf{\Omega}$ |

1 | 1 | 1 | 1 | $\frac{HRS}{3}$ | 44.4 k$\mathsf{\Omega}$ |

Primitive | Structure | Latency | Ref |
---|---|---|---|

IMPLY | 1D–1R | 43 steps | [50] |

IMPLY | 1R | 35 steps | [32] |

IMPLY | 1R | 27 steps | [51] |

IMPLY | 1R | 23 steps | [52] |

IMPLY(semi-parallel) | 1T–1R | 17 steps | [53] |

IMPLY | 1T–1R | 13 steps | [54] |

ORNOR | 1T–1R | 17 steps | [55] |

NOR | 1S–1R | 10 steps | [48] |

NAND | 1S–1R | 10 steps | [49] |

XOR+NAND (unipolar memristors) | 1S–1R | 8 steps | [56] |

MAJORITY+NOT | 1T–1R | 6 steps | [45] |

Primitive | Array | Adder Type | Latency | Comment/Ref |
---|---|---|---|---|

IMPLY | 1S-1R | Ripple carry | 58 | Each step is IMPLY operation [35] |

IMPLY+OR | 1S-1R | Ripple Carry | 54 | Each step is IMPLY/OR/NOR operation [60] |

IMPLY | – | Parallel-prefix | 25 | Each step is IMPLY operation [58] |

NOR/NOT | 1T-1R | Look-Ahead | 48 | Each step has one or more NOR/NOT operations [61] |

NOR | 1S-1R | algorithm | 38 | Each step has one or more NOR operations [18] |

OR/AND | 1S-1R | Parallel-prefix | 37 | Each step has one or more OR/AND operation [57] |

ORNOR | 1S-1R | Parallel-clocking | 31 | Each step has one or more ORNOR/IMPLY operation [55] |

MAJORITY+NOT | 1T-1R | Parallel-prefix | 19 | Each step is Majority/NOT or WRITE [46] |

XOR | 1T-1R | Ripple carry | 16 * | Each step is XOR [59] |

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Reuben, J.
Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing. *J. Low Power Electron. Appl.* **2020**, *10*, 28.
https://doi.org/10.3390/jlpea10030028

**AMA Style**

Reuben J.
Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing. *Journal of Low Power Electronics and Applications*. 2020; 10(3):28.
https://doi.org/10.3390/jlpea10030028

**Chicago/Turabian Style**

Reuben, John.
2020. "Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing" *Journal of Low Power Electronics and Applications* 10, no. 3: 28.
https://doi.org/10.3390/jlpea10030028