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Review

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

Chair of Computer Science 3—Computer Architecture, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 91058 Erlangen, Germany
J. Low Power Electron. Appl. 2020, 10(3), 28; https://doi.org/10.3390/jlpea10030028
Received: 5 August 2020 / Revised: 25 August 2020 / Accepted: 2 September 2020 / Published: 4 September 2020
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives. View Full-Text
Keywords: memristor; memristive logic; Non-Volatile Memory (NVM); Resistive RAM; in-memory computing; majority logic; adder; Boolean logic; parallel-prefix adder memristor; memristive logic; Non-Volatile Memory (NVM); Resistive RAM; in-memory computing; majority logic; adder; Boolean logic; parallel-prefix adder
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MDPI and ACS Style

Reuben, J. Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing. J. Low Power Electron. Appl. 2020, 10, 28. https://doi.org/10.3390/jlpea10030028

AMA Style

Reuben J. Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing. Journal of Low Power Electronics and Applications. 2020; 10(3):28. https://doi.org/10.3390/jlpea10030028

Chicago/Turabian Style

Reuben, John. 2020. "Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing" Journal of Low Power Electronics and Applications 10, no. 3: 28. https://doi.org/10.3390/jlpea10030028

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