Convolution Kernel Operations on a Two-Dimensional Spin Memristor Cross Array

In recent years, convolution operations often consume a lot of time and energy in deep learning algorithms, and convolution is usually used to remove noise or extract the edges of an image. However, under data-intensive conditions, frequent operations of the above algorithms will cause a significant memory/communication burden to the computing system. This paper proposes a circuit based on spin memristor cross array to solve the problems mentioned above. First, a logic switch based on spin memristors is proposed, which realizes the control of the memristor cross array. Secondly, a new type of spin memristor cross array and peripheral circuits is proposed, which realizes the multiplication and addition operation in the convolution operation and significantly alleviates the computational memory bottleneck. At last, the color image filtering and edge extraction simulation are carried out. By calculating the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) of the image result, the processing effects of different operators are compared, and the correctness of the circuit is verified.


Introduction
In recent years, in emerging data-intensive applications such as deep convolutional neural networks (DCNN) [1,2], image preprocessing tends to consume a lot of time and energy. The convolution processing operation is a widely applicable and far-reaching algorithm in the field of image processing. When convolution operations on images involve multiplication and addition operations, there will have problems of relatively large overhead, high real-time requirement, strong concurrency and frequent data exchange between memory and processor. The existing processing architecture has insufficient memory bandwidth and processing performance, resulting in a "memory wall" effect. Because the technological development of CMOS technology has reached its limit [3][4][5], the focus has been shifted from seeking faster processors to alleviating "memory bottlenecks". Although multicore architecture [6] and near-data structure [7,8] have been tried to improve convolution computing performance, they have not jumped out of the storage and computing separation architecture under the Von Neumann system, and there are still problems such as low energy/area efficiency, expensive hardware cost [9][10][11], etc. Memristor has the characteristics of integration of storage and calculation, so it has a wide range of application prospects in the field of in-memory computing.
Since 1971, Professor Chua predicted the existence of the fourth basic circuit device-memristor [12], and scientists have been searching for the missing memristor for 37 years. effect has been significancly improved. By calculating peak signal-to-noise ratio (PSNR) and structural similarity (SSIM), the filtering and edge extraction effects of the above operators are compared.
The rest of the work in the paper is arranged as follows: Section 2 introduces the spin memristor model and proposes a logic switch based on the spin memristor. In Section 3, we will introduce the spin memristor cross array and its peripheral circuits that implement the convolution operation. In Section 4, the MATLAB simulation results of the circuit (mentioned in Section 3) in the image processing application are given, and the performances are analyzed and discussed respectively by adopting different filter operator and edge extraction operator. Finally, Section 5 summarizes the research content of this paper.

Logic Switch Based on Spin Memristor
The convolutional cross-array circuit proposed in this paper includes three significant modules-memristor cross-array, row/column address selector containing logic switches, and weighted average filter. The memristor cross-aray can store information in the form of conductance. By controlling the row/column address selector, when a voltage is applied to the corresponding column of the memristor cross-array, the current will carry the memristor information, and added together by an operational amplifier. The average filter can filter out polluted pixels in advance. This implementation has the advantages of parallelism, high efficiency, low complexity, fast speed, and easy control (low control voltage). This section will introduce the spin memristor model and the specific principles of spin memristor-based logic switches.

Introduction to Spin Memristors
The spin memristor is a device controlled by electric charge. Its structure diagram and equivalent circuit diagram are shown in Figure 1. The spin memristor is composed of a long spin-valve bar, which contains two layers of ferromagnets: The upper layer is the free layer, and the lower layer is the reference layer. The magnetic polarity of the reference layer is fixed in the magnetic layer by coupling technology. The free layer is divided into two by the magnetic domain wall. The two sections have opposite polarities. The resistance of each section is determined by the relative magnetization direction of the reference layer and free layer. When the magnetization directions of the two layers are opposite (parallel), the resistance of the spin memristor reaches the maximum (minimum). The length, width, and height of the memristor in Figure 1a are represented by D, h, and z, respectively. W is the thickness of the magnetic domain wall. When power is applied to both ends of the spin memristor, the magnetic domain wall will move in the free layer, the total length of the two magnetization directions of the layer will change, leading to the change of the memristance value. Here, r L and r H respectively represent the high and low resistance values of the spin memristor, x represents the distance moved by the magnetic domain wall. Regardless of the domain wall width W, the equivalent circuit diagram of the memristor can be approximated by Figure 1b, and the resistance value of the memristor [15] is: The relationship between the moving speed v of the domain wall and the current density J is expressed as [15]: The relationship between x and the amount of charge passing through the memristor is: Equation (1) shows that the spintronic memristor has good linearity and can meet the requirements of multibit data storage. Here,Γ v is the proportional coefficient, which is related to the structure of the device and the properties of the material. Besides, the adjustment of the memristance value M (x) is limited by the current density threshold. In other words, when the current density J is less than the critical current density J cr , the resistance of the spin memristor is a constant. As long as the current density J is less than the critical current density, the state of the spintronic memristor will remain unchanged no matter how long the sensing voltage is maintained. When the current density J is higher than J cr , the memristance value begins to change. The equation for calculating the current threshold J cr of the device is as follows [15]: where P represents the magnetic susceptibility of the material, M s represents the saturation magnetization, α and γ represent the damping parameter and gyromagnetic ratio of the memristor, respectively. H p and H k represent the hard anisotropy and easy anisotropy of the magnetic material, respectively. A represents the exchange parameter, u B is the Bohr magneton constant, e is the elementary charge. The expression of the current density J of the spin memristor device is [15]: As shown in Figure 2, the state variable x of the spin memristor model will gradually increase under the action of a positive voltage until the threshold condition is met or the maximum value of the state variable x is reached. The state variable x of the spin memristor model will gradually decrease under the action of negative voltage until the threshold condition is met or the minimum value of the state variable x is approached. Figure 3 shows the resistance change curve of the spin memristor and its external excitation voltage curve. V is the voltage applied to the memristor, and M (x) represents the resistance value of the spin memristor when the magnetic domain wall moves by the distance x. Specifically, when the external excitation voltage is V 1 (red line), in the time domain [50, 100 ns], the external excitation voltage is positive and satisfied V 1 / (r H · h · z) ≥ J cr , and the memristance value gradually increases to its maximum value; correspondingly, in the time domain [100 ns, 150 ns], when the external excitation voltage is negative and satisfied |V 1 / (r H · h · z)| ≥ J cr , the memristance value gradually decreases to its minimum value. When the external excitation voltage is V 2 (blue line), in the time domain [50, 100 ns], the external excitation voltage is positive and satisfies the double inequality relationship V 2 / (r H · h · z) > J cr > V 2 / (r L · h · z), the memristance value gradually increases and the real-time current density decreases. If the real-time current density J is equal to the threshold current density J cr , the memristor will remain unchanged. At this time, in the time domain [100 ns, 150 ns], only the polarity of the excitation voltage is changed, the resistance value of the memristor will not change. Appropriately increasing the amplitude of the excitation voltage to V 3 (green line), so that the external excitation voltage is negative and satisfied |V 3 / (r H · h · z)| ≥ J cr , the memristor resistance will decrease, and the real-time current density will increase and is always larger than the threshold current density J cr , the memristance value eventually decreases to its minimum value. Similarly, the time required for the above-mentioned spin memristor resistance change can be derived from Equations (11) and (12). The spin memristive damping parameter used in this paper is 0.002, and the current density threshold J cr is approximately equal to 5.74 × 10 12 , and the critical current can be calculated as I cr = J cr × h × z = 4.018 × 10 −4 A. After determining the structure and material of the device, the length D and width z of the spintronic memristor are the main factors for adjusting the high and low resistance of spin memristors. Besides, to reduce the localization of changes, the high-impedance resistance value of each cross-point memristor is set to 8 KΩ, and it is connected in series with a fixed resistance of 92 KΩ and a diode. The diode causes the current cross array to flow unidirectionally to prevent the sneak path current from affecting the output result. Adding a fixed resistor can prevent the memristance value from changing too small. In the following content, we will use "memristor" to refer to the memristor, resistor, and diode on the same contact, because the resistance part does not affect the training of the current control memristor. When a constant current exceeding the critical value is applied, the memristance value will decrease. Note that the adjustment in this study does not exceed one ns. By changing the critical current density J cr , training current I tr (t), and speed coefficient v, the speed v of memristive decay can be adjusted.

Memristor Switch (MS) Based on Magnetic Flux Control Spin Memristor
The resistance of the spin memristor can be described as [15], where M is the resistance value of the spin memristor, r H and r L are the high resistance and low resistance of the spin memristor, respectively, and D represents the length of the spin memristor. Spin memristor models all have unique threshold characteristics. That is, when the real-time current density J of the spin memristor is less than the threshold current density J cr , it appears as a constant value resistance. On the contrary, when the real-time current density J of the spin memristor is greater than or equal to the threshold current density J cr , the domain wall shifts and changes the resistance of the spin memristor. In this case (J ≥ J cr ), perform differential operations on both sides of Equation (6), we can obtain: where Γ v is the proportional coefficient, J represents the current density, h and z represent the width and height of the spin memristor, respectively, and V is the voltage applied on the spin memristor. Then, integrate both sides of Equation (7) at the same time, to obtain the expression of the resistance value of the spin memristor controlled by the magnetic flux as follows: where M 0 is the initial resistance value of the spin memristor, ϕ is the magnetic flux flowing through the memristor, and its corresponding threshold ϕ th1 ,ϕ th2 depends on the limit memristance value and the initial memristance value of the spin memristor. The auxiliary variable B = ∆r · Γ v /z · h is a fixed constant.
In particular, based on Equation (8), the input voltage V is a constant with a fixed amplitude and the real-time current density of the memristor always satisfies J ≥ J cr . When the memristance changes from r H to r L , the total magnetic flux inside the spin memristor changes as follows: The proposed AND logic switch (MS) based on the memristor is a simplified form of [36], which consists of two memristors P and Q connected through two positive terminals, as shown in Figure 4a. V P and V Q are two input voltages, and V R is the output. In order to ensure the correctness of AND logic operation, R R R P , R Q . The truth table based on the AND operation of the memristor is shown in Figure 4b. The time required to change the memristance from r L to r H or from r H to r L is assumed to be the same. The initial states of the P and Q memristors are arbitrary. Based on ∆ϕ = V · ∆T, the MS switching time T 1 , the M R switching time T 2 is  r H and r L are the high resistance and low resistance of the memristor P and Q, respectively, and r H ' and r L ' are the high resistance and low resistance of the memristor M R , as shown in Figure 4a. Assuming there is no threshold in MS. The output error V e [36] is According to the simulation results of the spin memristor logic switch in Figure 5, there are four special cases as follow: 1. V P = V Q = V H = "1" ("1" stands for logic 1, V H stands for high-level voltage; "0" stands for logic 0, V L stands for low-level voltage, and V L = 0), the output voltage V R is Since there is a positive voltage across M R , its memristive is reduced. After time T 2 , R R = R on , the logic value stored in M R changes to logic 1. 2. V P = V H = "1", V Q = V L = "0", the voltage across M P is negative, and the voltage across M Q is positive. After time T 1 , The logical value is stored in M R to retain logic 0. 3. V P = V L = "0", V Q = V H = "1", the voltage across M P is positive, and the voltage across M Q is negative. After time T 1 , The logical value is stored in M R to retain logic 0. 4. V P = V Q = V L = "0". The output voltage V R = 0, so the logic value is stored in M R to retain logic 0.
Therefore, the total time required for a complete logic switch operation is 2ns 3ns

Spin Memristor Cross-Array Circuit for Realizing Convolution Operation
The convolution kernel (also known as the filter) is usually a 2D matrix. To implement the convolution kernel on the memristor array, the 2D convolution kernel matrix is expanded and its dimensionality is reduced to 1D column vector. The paper uses the N × N convolution kernel matrix; here, we choose a convolution kernel with an odd number of N because if the filter size is even, the size of the input and output cannot be guaranteed unchanged. As shown in Figure 6, the convolution operation is performed on each pixel of the input image and involves three consecutive steps. When the convolution kernel is superimposed on the input image in this way, the operation starts. At first, the image to be processed is padded, and the center pixel of the convolution kernel is aligned with the single-pixel which is convolved in the input image. Then, multiply each pixel value in the input image by the corresponding value in the kernel. In the third step, the sum of the products of the second step is calculated, and the sum becomes the pixel value in the output. To convolve the entire image, it must be moved and received repeatedly to scan the input image pixel by pixel.

Cross Array Circuit Based on Spin Memristor
Assume that a system is in discrete iteration V k of the input, and the index is V k = 1, 2, . . . , V m . During each iteration k, the system will receive a pair of two vectors M and N of size: the input image matrix V k I ∈ R M and the output image matrix V k O ∈ R N . Assuming that the F convolution kernel array is an adjustable N × M matrix, and considering the estimator, where i = 1, 2,. . . , M and j = 1, 2,. . . , N. Figure 7 shows the memristor cross array used for convolution operations, which consists of a single crossbar array of M (g,k) and a 1/R B constant term circuit. By expanding the pixels of an input image and converting them into voltages to be applied to rows, the currents read from multiple columns in an array can be calculated in parallel with the convolution results, which significantly accelerates the calculation speed. Here, g i,j is the memristor conductance at the intersection between the jth row and the kth column. V in,j is the input voltage applied to the jth column. V C,K is the row line voltage on the kth row. The row lines V C,F are connected to all the applied input voltages from V in,1 to V in,m through R B . In Figure 7, V C,F , and negative feedback resistor R 1 enter G F together. The latter constitutes an inverting amplifier. The output voltage of G F is V F , which is connected to all row lines from V C,1 to V C,n through R 1 . By applying Kirchhoff's current law to the row lines V C,F , we can calculate V F [33] as: For the column lines, as shown in Figure 7, each row line is connected to its inverting amplifiers G 1 to G n . For example, V C,1 enters G 1 through negative feedback resistance R 0 , V out,1 is the output voltage of G 1 , V C,k enters G k similarly, and V out,k is the output voltage of G k , V out,k can be calculated by the following Equation [33]: Incorporating Equation (19) into Equation (20), we can get: If m ∑ j=1 R 0 · g B − g j,k is determined by the symmetric convolution kernel F in the kth row and the jth column, then we can rewrite Equation (21) as: Assuming that the conductance value range of the memristor is 0-1024 µS (where 0 means a minimal number, not 0 µS), the maximum number of digits represented by the memristor is 8 bit, so every 12 µS is equivalent to the number 1, assuming g B is 500 µS and R 0 is 83 kΩ. As shown in Figure 7, a 3 × 3 input image block is randomly selected, and a 3 × 3 SRMC operator [2] is used for convolution operation here. First, expand the 3 × 3 SRMC operator into 1 × 9 rows, convert them into conductance values, and store them in the memristor cross-array. Then, expanding the input 3 × 3 image block pixel values into 1 × 9 rows, convert the 0-255 pixels into 0-2.55 V voltages, and input them into the memristor array through the column lines. The final V out , one output voltage is 1.67 V, and the image pixel result calculated by convolution is 167, which verifies the correctness of the circuit.

Convolution Operation on Memristor Cross-Array Circuit
The state of the spin memristor is determined by the amount of charge or magnetic flux passing through it. Within the significant charge and magnetic flux range, if the total amount of charge or total magnetic flux passing through the spin memristor is zero, the memristor will eventually return to the initial value state [37]. Figure 8 shows the state change of the memristor whose initial state is x 0 caused by a symmetrical pulse current. The amplitude of the first half of the current is −I A , and the width is T W , which converts the spin memristor state to x 1 as follows: -I A  The amplitude of the second half current is I A , and the width is T W , and continue to switch the memristor state to x 2 as follows: It can be seen that if the total amount of charge passing through the memristor is zero, the state of the memristor will eventually return to the initial state. If the total magnetic flux passing through the memristor is zero, the same effect will be achieved. For simplicity, suppose the power supply is a symmetrical pulse voltage with amplitudes −V A and V A , and the widths of the two parts are both T W . Using the relationship between the memristance value and magnetic flux in Equation (8), within the effective magnetic flux range, there are: This property can be used for the read operation of the memristive memory. With this symmetrical sourse (current or voltage), the stored memristance value can be accurately read, so that the read operation will not adversely affect the stored memristance value. It is known that the resistance value of the memristor depends on the polarity, size, and time length of the external power. Assuming that the external power is a voltage pulse (amplitude is V W , width is t p ), the write operation can set the memristor from the initial conductance g 0 to g' as follows: Using the symmetrical read voltage mode, the stored memristance value g out = i o /v o = g can be read, and then V W is As shown in Figure 9, the memristor cross array circuit that implements the convolution operation includes a spin memristor cross array, row/column address selector, and address encoder, read/write control, read circuit, weighted average filter.
In the writing mode, the color image is decomposed into three channels of R, G, and B, decomposed into multiple N × N image blocks, expanded into 1 × N 2 rows, and then converted into voltage input from below, range for [0 V, 2.55 V], store the convolution kernel operator into the memristor array by controlling the address selector. The salt and pepper noise in the image is removed by a weighted average filter. When constructing the filter, the switching strategy is adopted to improve the filtering effect. In fact, the mean filter is called an algorithm, which makes an image blurry. In order to solve this problem, this paper proposes a switching strategy to find pixels that may be contaminated, and the mean filter is only applicable to noisy pixels. Specifically, the algorithm using the switching strategy has two-pixel thresholds p 1 and p 2 , which represent the upper threshold and the lower threshold, respectively. Set [p 1 , p 2 ] to [5,250], that is, [V tu , V tl ] to [0.05 V, 2.50 V]. First, execute the read mode to determine whether the current pixel is a noise point. If it is determined to be a normal pixel, inputs a voltage signal. Suppose the pixel value exceeds the range of [p 1 , p 2 ] (that is, the output voltage V O(t) exceeds the voltage range [V tu , V tl ] in the read mode, where V tu and V tl are the upper and lower threshold voltages), the pixel is considered as a noise point that should be processed by the filter. In the image edge extraction application, the weighted average filter in the dashed box in Figure 9 is not needed, so this part is deleted, reflecting the flexibility of the circuit.  Under the control of the address decoder and the row/column address selector, the input writes voltage pulse V W is applied to the selected memristor to change its resistance state. When the write operation is over, the voltage across the memristor is zero, and the memristance value remains unchanged to realize the memory function.
In the read mode, when the read signal is valid, the read-write control circuit controls the selector to generate the symmetrical mode read voltage signal as described above and applies it to the target memristor. At this time, the read circuit can measure the flow through the memory resistor current and output it as an output signal. So far, the write and read operations of the memristor are completed.
To verify the effectiveness of the memristor simulation storage scheme proposed in this paper, computer simulations are carried out, and the memristor used is its mathematical model. The memristor parameters are set to r L = 5 GΩ, r H = 6 GΩ, D = 1000 nm, h = 70 nm, z = 10 nm, and J cr is approximately equal to 5.74·e 12 . A write voltage pulse is applied to a certain memristor in the cross array, as shown in Figure 10a, and the corresponding memristance value change is shown in Figure 10c. The reading voltage as shown in Figure 10b is applied to the memristor, and the corresponding memristance value changes are shown in Figure 10d.

Application of Convolution Circuit in Color Image Denoising and Color Image Edge Extraction
By controlling the row/column address selector in Figure 9, 1-8 convolution operators can be stored in the memristor cross array in the form of conductance, and then the pixels of the image to be processed are converted into voltages. Voltages input from the bottom to the memristor cross array to realize multiplication and addition operations, which can realize different convolution operations, which reflects the flexibility of the circuit. This section introduces two image processing examples. In the first example, the circuit is used to achieve color image denoising and sharpening, and the filtering effects of different operators are compared. The second example is an edge detector, which uses a circuit structure that is faster and simpler than the previous circuit structure. This article uses MATLAB2020(a) version software for application-level simulation. Figure 11 shows the convolution operator used in the weighted average filter, where the operator (a) [34] is implemented by two horizontal and vertical convolutions to store the convolution kernel operator in the memristor array in the training mode. Please note that the sum voltage is 1/12 times the read voltage, so the calculation is weighted, and no additional division is required. By continuously using the operator convolution twice, the memristor at the core of the mask can be modified to the expected state. First, assume that a memristor is a target. Set [p 1 , p 2 ] to [5,250], that is, [V tu , V tl ] to [0.05 V, 2.50 V]. First, execute the read mode to determine whether the current pixel is a noise point. If it is determined to be a normal pixel, the value stored in the corresponding memristor will not change. Secondly, as described in the second section, sequentially store, train, and use convolution. Finally, by moving the image block, sliding processing is realized.  Operator (b) [38] is a median filter operator, taking the average of the nine values in the operator instead of the intermediate pixel value, so it has a smoothing and denoising effect. The gaussian filter operator presents a gaussian distribution in the horizontal and vertical directions, which highlights the weight of the center point after pixel smoothing has a better smoothing effect compared with mean filtering. Operator (c) is a 3 × 3 gaussian filter operator, operator (d) is a 5 × 5 gaussian filter operator [39], and operator (e) is an improved image sharpening operator based on the 5 × 5 gaussian filter operator. What is used is that the edge information in the image has higher contrast than the surrounding pixels, and this contrast is further enhanced after convolution, so that the image appears sharp and clear, which has the effect of sharpening the image.

Color Image Denoising Based on Different Filter Operators
Repeat these steps by applying the above operators until all pixels have removed the salt and pepper noise. We chose Lena as the primary material for the simulation. As shown in Figure 12a, 5% salt and pepper noise is added to the image in Figure 12b. Read the image that is denoised and stored in the original array in Figure 12b. Table 1 shows the power signal-to-noise ratio (PSNR) and structural similarity (SSIM) under different noise ratios. It means that the implementation has sufficient performance for different noise rates and gives correct results. Figure 12g is an improved gaussian filter operator, which achieves sharpened images. In short, the simulation results reported in this paper show that the circuit can implement a weighted average filter and give correct results.

Color Image Edge Detection Based on Different Convolution Operators
In the circuit of Figure 9, the weighted average filter is removed, and the input voltage directly enters the memristor array. Figure 13 shows the operator used for color image edge extraction. Figure 13(a 1 -a 4 ) is the prewitt operator [40], and Figure 9 (b 1 -b 4 ) is the sobel operator [41], both of which are first-order differential operator. The former is an average filter, the latter is a weighted average filter, and the detected image edge may be more significant than 2 pixels. The advantage of these two methods is that the grayscale gradient and low-noise images have better detection effect, but the disadvantage is that the processing effect is not ideal for images with multiple complex noises. Based on this, the above two operators are improved, as shown in operators (a 1 -a 8 ) and operators (b 1 -b 8 ), diagonal operators in 45 • and 135 • directions are added on the basis of the original horizontal and vertical operators. The results are shown in Figure 14b-e, and the extracted edge details are more abundant than the original. The improved sobel operator works best and even retains some of the color details of the image. Figure 13(c 1 -c 8 ) is the kirsch operator [42]. The extraction result is shown in Figure 14f. Eight templates are used to convolve each pixel on the image to obtain the derivative. These eight templates represent eight directions, the maximum response to eight specific edge directions on the image, and the maximum value in the calculation (the weighted sum of 3 × 3 pixels is the sum after the corresponding position is multiplied), which is output as the edge of the image. Figure 14 (d 1 -d 8 ) is robert operator [43], also known as a cross differential operator. The advantage is that the positioning is accurate, and the operator is simple. The disadvantage is that to get a good effect, multiple operators are required to superpose, the calculation speed is slow, and it is more sensitive to noise. The extraction result is shown in Figure 14g, and the extraction effect is average. Figure 14 (e 1 -e 4 ) are laplacian operators. Laplacian operators are more sensitive to noise, so the image is generally smoothed first. Because smoothing is also performed using templates, the usual segmentation algorithms are based on laplacian operators and the smoothing operator, which combined to generate a new template. It can be seen from the extraction result of Figure 14g that in addition to the edge extraction effect, the template also has the effect of sharpening the picture.

Opdrator (a1)
Opdrator (a2) Opdrator (a3) Opdrator (a4) Opdrator (a5) Opdrator (a6) Opdrator (a7) Opdrator (a8) Opdrator (b1) Opdrator (b2) Opdrator (b3) Opdrator (b4) Opdrator (b5) Opdrator (b6) Opdrator (b7) Opdrator (b8) Opdrator (d1) Opdrator (d2) Opdrator (d3) Opdrator (d4) Use the above operators to process the pixel values stored in the memristor array. In the case where the input circuit provides only one summation voltage at the same time, a negative number is included in the convolution. In order to avoid storing negative values (i.e., negative pixels) in the target memristor, we first use positive convolution to limit the negative result to 0 and maintain the positive result normally. In addition, the resulting pixel value has a risk of 255. This problem can be solved by limiting the maximum (current) output of VCCS at 13.209 µA By sliding the image block repeatedly, the edge of the color image can be extracted effectively until all pixels are processed by edge detector. We chose a 256 × 256 pixel picture as the primary material for this simulation. The result is shown in Figure 14. Table 2 shows the power signal-to-noise ratio (PSNR) of the edge extraction results after processing by different operators.

Conclusions
This paper proposes a generalized circuit scheme based on the filtering convolution operator and the edge extraction convolution operator to implement image processing applications on the spin memristor crossover to alleviate the storage bottleneck of data-intensive applications. By adopting a self-updating circuit and parallel multi-bit selective adder and convolution algorithm, we implement color image filtering and edge extraction with different operators, and reduce the dependence on data exchange to the lowest level. All the devices used in this paper are compatible with CMOS technology, so the proposed implementation scheme also shows the advantages of large-scale integrated manufacturing. The practicability and excellent performance of this work in image processing have been proved by algorithm simulation.