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Low Power Memory/Memristor Devices and Systems

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A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (28 February 2022) | Viewed by 56361

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Special Issue Editors

Dr. Alex Serb

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Guest Editor

Department of Electronics and Computer Science (ECS), University of Southampton, Southampton SO17 1BJ, UK
Interests: electronic circuits; neuromorphic engineering; computational neuroscience
Special Issues, Collections and Topics in MDPI journals

Dr. Adnan Mehonic

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Guest Editor

Department of Electronic & Electrical Engineering, University College London, London WC1E 7JE, UK
Interests: functional materials; nanoelectronics; memristors; energy-efficient novel computing paradigms
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Special Issue Information

Dear Colleagues,

The continuing proliferation of AI is underpinning an intense interest in hardware development targeting the specific needs of AI computation. Part of the problem lies in the large memory requirements of systems employing millions of weights that are constantly being used to compute outputs. This places an enormous strain on both memory technology, which has to provide cheaper-better-faster memory, and on the Von Neumann architecture, which attempts to solve the problem by squeezing ever more data through an ever tighter pipeline.

The solution to this problem is not simple and encompasses many fields. Over the last few years, it has become clear that one such field is that of emerging memory technologies. By enlisting the help of nanotechnology, engineers are pushing the boundaries of the energy efficiency of memories in a race to the next generation of memory. Much like FLASH memory once upset a world dominated by magnetic memory, these days a multitude of emerging technologies (often collectively referred to as “memristors”) are vying to earn a place in the mainstream memory landscape, promising ultra-low power and area footprints.

This Special Issue will bring together excellent and inspiring work currently being undertaken in the area of low power memory including the following:

Demonstrations of novel memory devices exhibiting exemplary performance (especially low power operation).
Novel memory circuits and systems (specifically designed to efficiently incorporate/leverage the benefits of novel nanotechnology).
Other circuits and systems demonstrating the use of ultra-efficient memory (especially describing what was required in order to successfully implement or incorporate such memory into the system).

Naturally, this list is not exhaustive or exclusive and any contributions that pave the way towards the future of efficient memory are welcome.

We hope that you will contribute your work to this issue and help map the recent progress of memory technology and techniques.

Dr. Alex Serb
Dr. Adnan Mehonic
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

Low power memory
Memory circuits
Memristors
AI hardware

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Published Papers (12 papers)

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Research

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19 pages, 6639 KiB

Open AccessArticle

A Novel Inductorless Design Technique for Linear Equalization in Optical Receivers

by Diaaeldin Abdelrahman, Christopher Williams, Odile Liboiron-Ladouceur and Glenn E. R. Cowan

J. Low Power Electron. Appl. 2022, 12(2), 19; https://doi.org/10.3390/jlpea12020019 - 1 Apr 2022

Cited by 1 | Viewed by 3360

Abstract

To mitigate the trade-off between gain and bandwidth of CMOS multistage amplifiers, a receiver front-end (FE) that employs a high-gain narrowband transimpedance amplifier (TIA) followed by an equalizing main amplifier (EMA) is proposed. The EMA provides a high-frequency peaking to extend the FE’s [...] Read more.

(f_{b i t})

. The peaking is realized by adding a pole in the feedback paths of an active feedback-based wideband amplifier. By embedding the peaking in the main amplifier (MA), the front-end meets the sensitivity and gain of conventional equalizer-based receivers with better energy efficiency by eliminating the equalizer stages. Simulated in TSMC 65 nm CMOS technology, the proposed front-end achieves 7.4 dB and 6 dB higher gain at 10 Gb/s and 20 Gb/s, respectively, compared to a conventional front-end that is designed for equal bandwidth and dissipates the same power. The higher gain demonstrates the capability of the proposed technique in breaking the gain-bandwidth trade-off. The higher gain also reduces the power penalty incurred by the decision circuit and improves the sensitivity by 1.5 dB and 2.24 dB at 10 Gb/s and 20 Gb/s, respectively. Simulations also confirm that the proposed FE exhibits a robust performance against process and temperature variations and can support large input currents. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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11 pages, 763 KiB

Open AccessArticle

Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

by Kévin Mambu, Henri-Pierre Charles, Maha Kooli and Julie Dumas

J. Low Power Electron. Appl. 2022, 12(1), 18; https://doi.org/10.3390/jlpea12010018 - 16 Mar 2022

Cited by 3 | Viewed by 3551

Abstract

In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by the memory wall. However, it does not address the energy wall problem caused by data transfer over memory hierarchies. This paper proposes the data-locality management unit (DMU) to efficiently transfer data from a DRAM memory to a computational SRAM (C-SRAM) memory allowing IMC operations. The DMU is tightly coupled within the C-SRAM and allows one to align the data structure in order to perform effective in-memory computation. We propose a dedicated instruction set within the DMU to issue data transfers. The performance evaluation of a system integrating C-SRAM within the DMU compared to a reference scalar system architecture shows an increase from

\times 5.73

\times 11.01

in speed-up and from

\times 29.49

\times 46.67

in energy reduction, versus a system integrating C-SRAM without any transfer mechanism compared to a reference scalar system architecture. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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22 pages, 9688 KiB

Open AccessArticle

Silicon-Compatible Memristive Devices Tailored by Laser and Thermal Treatments

by Maria N. Koryazhkina, Dmitry O. Filatov, Stanislav V. Tikhov, Alexey I. Belov, Dmitry S. Korolev, Alexander V. Kruglov, Ruslan N. Kryukov, Sergey Yu. Zubkov, Vladislav A. Vorontsov, Dmitry A. Pavlov, David I. Tetelbaum, Alexey N. Mikhaylov, Sergey A. Shchanikov, Sungjun Kim and Bernardo Spagnolo

J. Low Power Electron. Appl. 2022, 12(1), 14; https://doi.org/10.3390/jlpea12010014 - 2 Mar 2022

Cited by 3 | Viewed by 3516

Abstract

Nowadays, memristors are of considerable interest to researchers and engineers due to the promise they hold for the creation of power-efficient memristor-based information or computing systems. In particular, this refers to memristive devices based on the resistive switching phenomenon, which in most cases are fabricated in the form of metal–insulator–metal structures. At the same time, the demand for compatibility with the standard fabrication process of complementary metal–oxide semiconductors makes it relevant from a practical point of view to fabricate memristive devices directly on a silicon or SOI (silicon on insulator) substrate. Here we have investigated the electrical characteristics and resistive switching of SiO_x- and SiN_x-based memristors fabricated on SOI substrates and subjected to additional laser treatment and thermal treatment. The investigated memristors do not require electroforming and demonstrate a synaptic type of resistive switching. It is found that the parameters of resistive switching of SiO_x- and SiN_x-based memristors on SOI substrates are remarkably improved. In particular, the laser treatment gives rise to a significant increase in the hysteresis loop in I–V curves of SiN_x-based memristors. Moreover, for SiO_x-based memristors, the thermal treatment used after the laser treatment produces a notable decrease in the resistive switching voltage. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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16 pages, 840 KiB

Open AccessArticle

Design of In-Memory Parallel-Prefix Adders

by John Reuben

J. Low Power Electron. Appl. 2021, 11(4), 45; https://doi.org/10.3390/jlpea11040045 - 24 Nov 2021

Cited by 6 | Viewed by 4777

Abstract

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in [...] Read more.

O (n)

). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in

O (l o g (n))

latency in the memory array. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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15 pages, 2215 KiB

Open AccessArticle

A New Physical Design Flow for a Selective State Retention Based Approach

by Joseph Rabinowicz and Shlomo Greenberg

J. Low Power Electron. Appl. 2021, 11(3), 35; https://doi.org/10.3390/jlpea11030035 - 13 Sep 2021

Cited by 3 | Viewed by 3887

Abstract

This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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18 pages, 2199 KiB

Open AccessArticle

Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

by Tommaso Zanotti, Francesco Maria Puglisi and Paolo Pavan

J. Low Power Electron. Appl. 2021, 11(3), 29; https://doi.org/10.3390/jlpea11030029 - 6 Jul 2021

Cited by 8 | Viewed by 5076

Abstract

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >10³ times when performing a BNN inference task with respect to a SIMPLY implementation. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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18 pages, 3895 KiB

Open AccessArticle

Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition

by Fernando Leonel Aguirre, Nicolás M. Gomez, Sebastián Matías Pazos, Félix Palumbo, Jordi Suñé and Enrique Miranda

J. Low Power Electron. Appl. 2021, 11(1), 9; https://doi.org/10.3390/jlpea11010009 - 5 Feb 2021

Cited by 11 | Viewed by 3728

Abstract

In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of the MNIST database, we evaluate the degradation of the inference accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers. Two approaches to reduce the impact of the line resistance are considered and implemented in our simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to the line resistance effect than SLPs and that partitioning is the most effective way to minimize the impact of high line resistance values. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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16 pages, 3159 KiB

Open AccessArticle

A Morphable Physically Unclonable Function and True Random Number Generator Using a Commercial Magnetic Memory

by Mohammad Nasim Imtiaz Khan, Chak Yuen Cheng, Sung Hao Lin, Abdullah Ash-Saki and Swaroop Ghosh

J. Low Power Electron. Appl. 2021, 11(1), 5; https://doi.org/10.3390/jlpea11010005 - 14 Jan 2021

Cited by 4 | Viewed by 3437

Abstract

We use commercial magnetic memory to realize morphable security primitives, a Physically Unclonable Function (PUF) and a True Random Number Generator (TRNG). The PUF realized by manipulating the write time and the TRNG is realized by tweaking the number of write pulses. Our analysis indicates that more than 75% bits in the PUF are unusable without any correction due to their inability to exhibit any randomness. We exploit temporal randomness of working columns to fix the unusable columns and write latency to fix the unusable rows during the enrollment. The intra-HD, inter-HD, energy, bandwidth and area of the proposed PUF are found to be 0, 46.25%, 0.14 pJ/bit, 0.34 Gbit/s and 0.385 μm²/bit (including peripherals) respectively. The proposed TRNG provides all possible outcomes with a standard deviation of 0.0062, correlation coefficient of 0.05 and an entropy of 0.95. The energy, bandwidth and area of the proposed TRNG is found to be 0.41 pJ/bit, 0.12 Gbit/s and 0.769 μm²/bit (including peripherals). The performance of the proposed TRNG has also been tested with NIST test suite. The proposed designs are compared with other magnetic PUFs and TRNGs from other literature. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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21 pages, 1134 KiB

Open AccessArticle

Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays

by Brandon Rumberg, Spencer Clites, Haifa Abulaiha, Alexander DiLello and David Graham

J. Low Power Electron. Appl. 2021, 11(1), 4; https://doi.org/10.3390/jlpea11010004 - 13 Jan 2021

Cited by 5 | Viewed by 3511

Abstract

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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34 pages, 1898 KiB

Open AccessFeature PaperArticle

Logic-in-Memory Computation: Is It Worth It? A Binary Neural Network Case Study

by Andrea Coluccio, Marco Vacca and Giovanna Turvani

J. Low Power Electron. Appl. 2020, 10(1), 7; https://doi.org/10.3390/jlpea10010007 - 22 Feb 2020

Cited by 8 | Viewed by 7985

Abstract

Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is possible to obtain a local computation without the need to fetch data from the main memory. Although this concept introduces a lot of advantages from a theoretical point of view, its implementation could introduce an increasing complexity overhead of the memory itself, leading to a more sophisticated design flow. As a case study, Binary Neural Networks (BNNs) have been chosen. BNNs binarize both weights and inputs, transforming multiply-and-accumulate into a simpler bitwise logical operation while maintaining high accuracy, making them well-suited for a LiM implementation. In this paper, we present two circuits implementing a BNN model in CMOS technology. The first one, called Out-Of-Memory (OOM) architecture, is implemented following a standard Von Neumann structure. The same architecture was redesigned to adapt the critical part of the algorithm for a modified memory, which is also capable of executing logic calculations. By comparing both OOM and LiM architectures we aim to evaluate if Logic-in-Memory paradigm is worth it. The results highlight that LiM architectures have a clear advantage over Von Neumann architectures, allowing a reduction in energy consumption while increasing the overall speed of the circuit. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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Review

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15 pages, 572 KiB

Open AccessReview

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

by John Reuben

J. Low Power Electron. Appl. 2020, 10(3), 28; https://doi.org/10.3390/jlpea10030028 - 4 Sep 2020

Cited by 25 | Viewed by 6930

Abstract

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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30 pages, 18030 KiB

Open AccessTutorial

Graph Coloring via Locally-Active Memristor Oscillatory Networks

by Alon Ascoli, Martin Weiher, Melanie Herzig, Stefan Slesazeck, Thomas Mikolajick and Ronald Tetzlaff

J. Low Power Electron. Appl. 2022, 12(2), 22; https://doi.org/10.3390/jlpea12020022 - 18 Apr 2022

Cited by 20 | Viewed by 4276

Abstract

This manuscript provides a comprehensive tutorial on the operating principles of a bio-inspired Cellular Nonlinear Network, leveraging the local activity of NbO

_{x}

memristors to apply a spike-based computing paradigm, which is expected to deliver such a separation between the steady-state phases of [...] Read more.

This manuscript provides a comprehensive tutorial on the operating principles of a bio-inspired Cellular Nonlinear Network, leveraging the local activity of NbO

_{x}

memristors to apply a spike-based computing paradigm, which is expected to deliver such a separation between the steady-state phases of its capacitively-coupled oscillators, relative to a reference cell, as to unveal the classification of the nodes of the associated graphs into the least number of groups, according to the rules of a non-deterministic polynomial-hard combinatorial optimization problem, known as vertex coloring. Besides providing the theoretical foundations of the bio-inspired signal-processing paradigm, implemented by the proposed Memristor Oscillatory Network, and presenting pedagogical examples, illustrating how the phase dynamics of the memristive computing engine enables to solve the graph coloring problem, the paper further presents strategies to compensate for an imbalance in the number of couplings per oscillator, to counteract the intrinsic variability observed in the electrical behaviours of memristor samples from the same batch, and to prevent the impasse appearing when the array attains a steady-state corresponding to a local minimum of the optimization goal. The proposed Memristor Cellular Nonlinear Network, endowed with ad hoc circuitry for the implementation of these control strategies, is found to classify the vertices of a wide set of graphs in a number of color groups lower than the cardinality of the set of colors identified by traditional either software or hardware competitor systems. Given that, under nominal operating conditions, a biological system, such as the brain, is naturally capable to optimise energy consumption in problem-solving activities, the capability of locally-active memristor nanotechnologies to enable the circuit implementation of bio-inspired signal processing paradigms is expected to pave the way toward electronics with higher time and energy efficiency than state-of-the-art purely-CMOS hardware. Full article

(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

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