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  • Article
  • Open Access
3 Citations
4,142 Views
22 Pages

Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores

  • Larysa Titarenko,
  • Vyacheslav Kharchenko,
  • Vadym Puidenko,
  • Artem Perepelitsyn and
  • Alexander Barkalov

Replacement policies have an important role in the functioning of the cache memory of processor cores. The implementation of a successful policy allows us to increase the performance of the processor core and the computer system as a whole. Replaceme...

  • Article
  • Open Access
3 Citations
3,261 Views
19 Pages

Structural Analysis of Multi-Core Processor and Reliability Evaluation Model

  • Sergo Tsiramua,
  • Hamlet Meladze,
  • Tinatin Davitashvili,
  • Jose-Maria Sanchez-Sáez and
  • Francisco Criado-Aldeanueva

4 February 2025

In the present paper, the models of structural analysis and evaluation of efficiency indicators (reliability, fault tolerance, viability, and flexibility) of a multi-core processor with variable structure, equipped with multi-functional cores, are co...

(This article belongs to the Section E1: Mathematics and Computer Science)
  • Article
  • Open Access
11 Citations
6,912 Views
20 Pages

Design and Evaluation of Open-Source Soft-Core Processors

  • Mario Gazziro,
  • Jecel Mattos de Assumpção Junior,
  • Oswaldo Hideo Ando Junior,
  • Marco Roberto Cavallari and
  • João Paulo Carmo

16 February 2024

The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. Howe...

(This article belongs to the Section Circuit and Signal Processing)
  • Article
  • Open Access
8 Citations
9,333 Views
26 Pages

11 August 2011

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performanc...

(This article belongs to the Special Issue Microprocessors and System-on-Chip)
  • Article
  • Open Access
6 Citations
6,534 Views
14 Pages

Design of a Configurable Five-Stage Pipeline Processor Core Based on RV32IM

  • Yiyang Chang,
  • Yiming Liu,
  • Chong Peng,
  • Jiarui Guo and
  • Yi Zhao

28 December 2023

With the rapid development of the electronics industry, the scale of the global Internet of Things (IoT) industry has shown an exponential growth trend in recent years. The huge demand for IoT equipment makes low cost an important indicator for the s...

  • Article
  • Open Access
15 Citations
9,869 Views
18 Pages

Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS technique is also more and more frequently seen in industrial or even consu...

(This article belongs to the Special Issue Design, Fabrication and Testing of Integrated Circuits and Systems)
  • Article
  • Open Access
4 Citations
4,123 Views
19 Pages

Currently, there is a special interest in validating the use of Commercial-Off-The-Shelf (COTS) multi/many-core processors for critical applications thanks to their high performance, low power consumption and affordability. However, the continuous sh...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
18 Citations
5,665 Views
17 Pages

Dynamic Multimedia Encryption Using a Parallel File System Based on Multi-Core Processors

  • Osama A. Khashan,
  • Nour M. Khafajah,
  • Waleed Alomoush,
  • Mohammad Alshinwan and ,
  • Sultan Alamri,
  • Samer Atawneh and
  • Mutasem K. Alsmadi
  • + 2 authors+ 0 author

Securing multimedia data on disk drives is a major concern because of their rapidly increasing volumes over time, as well as the prevalence of security and privacy problems. Existing cryptographic schemes have high computational costs and slow respon...

  • Article
  • Open Access
8 Citations
6,477 Views
24 Pages

1 November 2012

In transmitting image/video data over Video Sensor Networks (VSNs), energy consumption must be minimized while maintaining high image/video quality. Although image/video compression is well known for its efficiency and usefulness in VSNs, the excessi...

(This article belongs to the Section Sensor Networks)
  • Article
  • Open Access
2 Citations
2,745 Views
25 Pages

19 October 2022

The massive number of users has brought severe challenges in managing cloud data centers (CDCs) composed of multi-core processor that host cloud service providers. Guaranteeing the quality of service (QoS) of multiple users as well as reducing the op...

  • Article
  • Open Access
2,581 Views
17 Pages

Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation

  • Mengqiao Lan,
  • Libo Huang,
  • Ling Yang,
  • Sheng Ma and ,
  • Run Yan,
  • Yongwen Wang and
  • Weixia Xu
  • + 2 authors+ 0 author

29 November 2022

Late-stage (post-RTL implementation) optimization is important in achieving target performance for realistic processor design. However, several challenges remain for modern out-of-order ILP (instruction-level-parallelism) processors, such as simulati...

  • Article
  • Open Access
15 Citations
6,258 Views
17 Pages

A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare

  • Hassan Mushtaq,
  • Sajid Gul Khawaja,
  • Muhammad Usman Akram,
  • Amanullah Yasin and ,
  • Muhammad Muzammal,
  • Shehzad Khalid and
  • Shoab Ahmad Khan
  • + 2 authors+ 0 author

25 November 2018

Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioni...

(This article belongs to the Special Issue Smart, Secure and Sustainable (3S) Technologies for IoT Based Healthcare Applications)
  • Article
  • Open Access
1 Citations
3,386 Views
22 Pages

1 December 2019

This paper presents an efficient pipelined broadcasting algorithm with the inter-node transmission order change technique considering the communication status of processing nodes. The proposed method changes the transmission order for the broadcast o...

(This article belongs to the Special Issue Mathematical Modeling in Industrial Engineering and Electrical Engineering)
  • Article
  • Open Access
3 Citations
1,983 Views
15 Pages

Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

  • Mariusz Węgrzyn,
  • Ernest Jamro,
  • Agnieszka Dąbrowska-Boruch and
  • Kazimierz Wiatr

14 October 2021

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT m...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
5 Citations
3,301 Views
19 Pages

31 October 2025

The widespread adoption of fifth-generation Reduced Instruction Set Computing (RISC-V) processors in embedded systems has driven advancements in domestic processor design. However, research on processor performance optimization methods predominantly...

  • Article
  • Open Access
12 Citations
10,881 Views
20 Pages

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs...

(This article belongs to the Section Internet of Things)
  • Article
  • Open Access
5 Citations
4,065 Views
19 Pages

8 September 2022

Many embedded systems are introducing processing units to accelerate the processing speed of tasks, such as for multi-media applications. The units are mostly customized designs. Another method of designing multi-unit systems is using pre-defined sta...

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)
  • Article
  • Open Access
8 Citations
6,271 Views
20 Pages

A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System

  • Damian Wanta,
  • Waldemar T. Smolik,
  • Jacek Kryszyn,
  • Przemysław Wróblewski and
  • Mateusz Midura

11 February 2022

A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original...

(This article belongs to the Section Artificial Intelligence Circuits and Systems (AICAS))
  • Article
  • Open Access
4 Citations
5,504 Views
19 Pages

Research on Cache Coherence Protocol Verification Method Based on Model Checking

  • Yiqiang Zhao,
  • Boning Shi,
  • Qizhi Zhang,
  • Yidong Yuan and
  • Jiaji He

11 August 2023

This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the proc...

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)
  • Article
  • Open Access
2 Citations
4,498 Views
12 Pages

24 August 2017

In sensory swarms, minimizing energy consumption under performance constraint is one of the key objectives. One possible approach to this problem is to monitor application workload that is subject to change at runtime, and to adjust system configurat...

(This article belongs to the Section Sensor Networks)
  • Article
  • Open Access
23 Citations
8,558 Views
27 Pages

30 December 2021

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of th...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
21 Citations
6,994 Views
27 Pages

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

  • Vanessa Vargas,
  • Pablo Ramos,
  • Jean-Francois Méhaut and
  • Raoul Velazco

17 March 2018

Multi-core and many-core processors are a promising solution to achieve high performance by maintaining a lower power consumption. However, the degree of miniaturization makes them more sensitive to soft-errors. To improve the system reliability, thi...

  • Article
  • Open Access
2 Citations
2,602 Views
18 Pages

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World...

  • Article
  • Open Access
61 Citations
23,324 Views
26 Pages

E/E Architecture Synthesis: Challenges and Technologies

  • Hadi Askaripoor,
  • Morteza Hashemi Farzaneh and
  • Alois Knoll

10 February 2022

In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driv...

(This article belongs to the Topic Intelligent Transportation Systems)
  • Article
  • Open Access
4 Citations
1,834 Views
19 Pages

Parallel Ant Colony Algorithm for Sunway Many-Core Processors

  • Chao Han,
  • Hao Xiong,
  • Haonan Yang,
  • Chaozhong Yang and ,
  • Tao Xue and
  • Feng Liu
  • + 1 author+ 0 author

Ant colony optimization (ACO) has garnered significant attention because of its wide application in route planning problems. Nevertheless, ACO requires a long time to calculate when tackling complex issues. Parallelization emerges as an effective str...

(This article belongs to the Special Issue Computer Architecture & Parallel and Distributed Computing)
  • Article
  • Open Access
6 Citations
9,846 Views
21 Pages

Thread-level and data-level parallel architectures have become the design of choice in many of today’s energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architec...

(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
  • Article
  • Open Access
10 Citations
6,524 Views
21 Pages

15 December 2016

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). T...

(This article belongs to the Section Physical Sensors)
  • Article
  • Open Access
2 Citations
10,702 Views
39 Pages

CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

  • Kushal Datta,
  • Arindam Mukherjee,
  • Guangyi Cao,
  • Rohith Tenneti and ,
  • Vinay Vijendra Kumar Lakshmi,
  • Arun Ravindran and
  • Bharat S. Joshi
  • + 2 authors+ 0 author

Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors...

(This article belongs to the Special Issue Low Power Design Methodologies and Applications)
  • Article
  • Open Access
2 Citations
4,767 Views
21 Pages

3 November 2021

Shared memory is the most popular parallel programming model for multi-core processors, while message passing is generally used for large distributed machines. However, as the number of cores on a chip increases, the relative merits of shared memory...

(This article belongs to the Special Issue 10th Anniversary of Electronics: Recent Advances in Computer Science & Engineering)
  • Article
  • Open Access
5 Citations
7,078 Views
13 Pages

24 May 2017

As part of network security processes, network intrusion detection systems (NIDSs) determine whether incoming packets contain malicious patterns. Pattern matching, the key NIDS component, consumes large amounts of execution time. One of several trend...

(This article belongs to the Special Issue Networks, Communication, and Computing)
  • Article
  • Open Access
4 Citations
8,321 Views
20 Pages

Comparison of the Usability of Apple M1 Processors for Various Machine Learning Tasks

  • David Kasperek,
  • Michal Podpora and
  • Aleksandra Kawala-Sterniuk

20 October 2022

In this paper, the authors have compared all of the currently available Apple MacBook Pro laptops, in terms of their usability for basic machine learning research applications (text-based, vision-based, tabular). The paper presents four tests/benchma...

(This article belongs to the Special Issue Intelligent Sensors and Machine Learning)
  • Article
  • Open Access
7 Citations
19,759 Views
18 Pages

Comparison of the Usability of Apple M2 and M1 Processors for Various Machine Learning Tasks

  • David Kasperek,
  • Pawel Antonowicz,
  • Marek Baranowski,
  • Marta Sokolowska and
  • Michal Podpora

8 June 2023

Thispaper compares the usability of various Apple MacBook Pro laptops were tested for basic machine learning research applications, including text-based, vision-based, and tabular data. Four tests/benchmarks were conducted using four different MacBoo...

(This article belongs to the Special Issue Sensors Data Processing Using Machine Learning)
  • Article
  • Open Access
6 Citations
4,814 Views
17 Pages

9 November 2019

Recently, thanks to the miniaturization and high performance of commercial-off-the-shelf (COTS) computer systems, small satellites get popular. However, due to the very expensive launching cost, it is critical to reduce the physical size and weight o...

(This article belongs to the Section Remote Sensors)
  • Feature Paper
  • Article
  • Open Access
4 Citations
4,416 Views
17 Pages

Developing Efficient Discrete Simulations on Multicore and GPU Architectures

  • Daniel Cagigas-Muñiz,
  • Fernando Diaz-del-Rio,
  • Manuel Ramón López-Torres,
  • Francisco Jiménez-Morales and
  • José Luis Guisado

In this paper we show how to efficiently implement parallel discrete simulations on multicore and GPU architectures through a real example of an application: a cellular automata model of laser dynamics. We describe the techniques employed to build an...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
9 Citations
5,806 Views
23 Pages

A RISC-V Processor Design for Transparent Tracing

  • Iván Gamino del Río,
  • Agustín Martínez Hellín,
  • Óscar R. Polo,
  • Miguel Jiménez Arribas and ,
  • Pablo Parra,
  • Antonio da Silva,
  • Jonatan Sánchez and
  • Sebastián Sánchez
  • + 3 authors+ 0 author

7 November 2020

Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines sta...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
2 Citations
3,604 Views
21 Pages

A DFT-Based Running Time Prediction Algorithm for Web Queries

  • Oscar Rojas,
  • Veronica Gil-Costa and
  • Mauricio Marin

4 August 2021

Web search engines are built from components capable of processing large amounts of user queries per second in a distributed way. Among them, the index service computes the top-k documents that best match each incoming query by means of a document ra...

(This article belongs to the Section Network Virtualization and Edge/Fog Computing)
  • Article
  • Open Access
1 Citations
735 Views
20 Pages

A Lightweight Convolution-Aware RISC-V Soft Processor for Intelligent Wearable Systems

  • Fernando L. Pizarro Diaz,
  • Booker A. Robinson and
  • Juan F. Patarroyo Montenegro

Resource-constrained wearable systems often need to be able to execute signal processing and AI workloads. There are many trade-offs to consider for this type of application. This paper presents a lightweight convolution-aware soft processor for embe...

(This article belongs to the Special Issue Ubiquitous Computing and Mobile Computing)
  • Article
  • Open Access
8 Citations
5,794 Views
13 Pages

An Educational RISC-V-Based 16-Bit Processor

  • Jecel Mattos de Assumpção,
  • Oswaldo Hideo Ando,
  • Hugo Puertas de Araújo and
  • Mario Gazziro

30 November 2024

This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key...

  • Review
  • Open Access
3 Citations
3,826 Views
16 Pages

On-Chip Bus Protection against Soft Errors

  • Ján Mach,
  • Lukáš Kohútka and
  • Pavel Čičák

19 November 2023

The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besi...

(This article belongs to the Special Issue Progress and Future Development of Real-Time Systems on Chip)
  • Article
  • Open Access
10 Citations
8,978 Views
15 Pages

Software and DVFS Tuning for Performance and Energy-Efficiency on Intel KNL Processors

  • Enrico Calore,
  • Alessandro Gabbana,
  • Sebastiano Fabio Schifano and
  • Raffaele Tripiccione

Energy consumption of processors and memories is quickly becoming a limiting factor in the deployment of large computing systems. For this reason, it is important to understand the energy performance of these processors and to study strategies allowi...

  • Article
  • Open Access
7 Citations
4,650 Views
16 Pages

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

  • Wenheng Ma,
  • Qiao Cheng,
  • Yudi Gao,
  • Lan Xu and
  • Ningmei Yu

10 March 2021

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performan...

(This article belongs to the Section E: Engineering and Technology)
  • Article
  • Open Access
7 Citations
3,888 Views
15 Pages

10 September 2022

Neuromorphic processors, the new generation of brain-inspired non-von Neumann computing systems, are developed to better support the execution of spiking neural networks (SNNs). The neuromorphic processor typically consists of multiple cores and adop...

(This article belongs to the Section Artificial Intelligence)
  • Article
  • Open Access
6 Citations
7,134 Views
12 Pages

The Design of a 2D Graphics Accelerator for Embedded Systems

  • Hyun Woo Oh,
  • Ji Kwang Kim,
  • Gwan Beom Hwang and
  • Seung Eun Lee

15 February 2021

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and...

(This article belongs to the Special Issue Recent Advances in Embedded Computing, Intelligence and Applications)
  • Article
  • Open Access
2 Citations
4,495 Views
22 Pages

14 December 2017

In wireless sensor networks (WSNs), sensor nodes are deployed for collecting and analyzing data. These nodes use limited energy batteries for easy deployment and low cost. The use of limited energy batteries is closely related to the lifetime of the...

(This article belongs to the Special Issue Mobile Sensing Applications)
  • Article
  • Open Access
1 Citations
6,121 Views
20 Pages

20 September 2016

Many-core processors are becoming mainstream computing platforms nowadays. How to map the application threads to specific processing cores and exploit the abundant hardware parallelism of a many-core processor efficiently has become a pressing need....

  • Article
  • Open Access
2 Citations
4,407 Views
16 Pages

22 November 2023

Development of a general-purpose PLC based on a typical dual-core processor as a hardware platform is presented. The cores run two cooperating projects involving data exchange through shared memory. Such a solution is equivalent to a single-core PLC...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
20 Citations
5,480 Views
17 Pages

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

  • Douglas A. Santos,
  • André M. P. Mattos,
  • Douglas R. Melo and
  • Luigi Dilillo

Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increas...

(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume III)
  • Article
  • Open Access
2,157 Views
15 Pages

The prefetcher is one of the key performance subsystems in RISC-V processors, and its design can significantly enhance memory access efficiency, reduce latency, and improve overall processor performance. This paper conducts in-depth research on the d...

(This article belongs to the Section Computer Science & Engineering)
  • Article
  • Open Access
2 Citations
2,475 Views
12 Pages

OMPEGAS: Optimized Relativistic Code for Multicore Architecture

  • Elena N. Akimova,
  • Vladimir E. Misilov,
  • Igor M. Kulikov and
  • Igor G. Chernykh

21 July 2022

The paper presents a new hydrodynamical code, OMPEGAS, for the 3D simulation of astrophysical flows on shared memory architectures. It provides a numerical method for solving the three-dimensional equations of the gravitational hydrodynamics based on...

(This article belongs to the Special Issue Parallel Computing and Applications)
  • Article
  • Open Access
31 Citations
7,465 Views
12 Pages

Intellino: Processor for Embedded Artificial Intelligence

  • Young Hyun Yoon,
  • Dong Hyun Hwang,
  • Jun Hyeok Yang and
  • Seung Eun Lee

The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI de...

(This article belongs to the Special Issue Recent Machine Learning Applications to Internet of Things (IoT))

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