Special Issue "Recent Advances in Embedded Computing, Intelligence and Applications"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 31 May 2020.

Special Issue Editors

Prof. Dr. Jorge Portilla
Website
Guest Editor
Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
Interests: embedded-system design; wireless-sensor networks; Internet of Things and FPGA-based reconfigurable systems
Prof. Dr. Andres Otero
Website
Guest Editor
Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
Interests: embedded-system design; 3D vision; FPGA-based reconfigurable systems; machine learning in the edge
Prof. Dr. Gabriel Mujica
Website
Guest Editor
Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
Interests: embedded-system design; Internet of things; IoT deployments; sensor networks communication protocols; algorithm distribution in IoT

Special Issue Information

Dear Colleagues,

The latest proliferation of Internet of Things deployments and edge computing combined with artificial intelligence has led to new exciting application scenarios, where embedded digital devices are key enablers of such ecosystems. Moreover, new powerful and efficient devices are appearing to cope with workloads formerly reserved for the cloud, such as deep learning, processing close to where data is being generated, and avoiding bottlenecks due to communications limitations.

In this Special Issue, we look forward to present new works on offloading processing tasks from the cloud to the edge with the new devices available in the market nowadays, including neural accelerators, FPGAs, and embedded processors with AI enhancements. Application papers showing implementations and deployments in this context are very welcome as well.

Prof. Dr. Jorge Portilla
Prof. Dr. Andres Otero
Prof. Dr. Gabriel Mujica
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Artificial intelligence in the edge
  • Neural processors in edge platforms
  • Artificial intelligence in IoT
  • Deep learning in the edge
  • Edge computing in embedded electronics
  • Machine Learning in IoT devices
  • Machine learning applications in the edge

Published Papers (3 papers)

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Research

Open AccessArticle
Performance of Two Approaches of Embedded Recommender Systems
Electronics 2020, 9(4), 546; https://doi.org/10.3390/electronics9040546 - 25 Mar 2020
Abstract
Nowadays, highly portable and low-energy computing environments require programming applications able to satisfy computing time and energy constraints. Furthermore, collaborative filtering based recommender systems are intelligent systems that use large databases and perform extensive matrix arithmetic calculations. In this research, we present an [...] Read more.
Nowadays, highly portable and low-energy computing environments require programming applications able to satisfy computing time and energy constraints. Furthermore, collaborative filtering based recommender systems are intelligent systems that use large databases and perform extensive matrix arithmetic calculations. In this research, we present an optimized algorithm and a parallel hardware implementation as good approach for running embedded collaborative filtering applications. To this end, we have considered high-level synthesis programming for reconfigurable hardware technology. The design was tested under environments where usual parameters and real-world datasets were applied, and compared to usual microprocessors running similar implementations. The performance results obtained by the different implementations were analyzed in computing time and energy consumption terms. The main conclusion is that the optimized algorithm is competitive in embedded applications when considering large datasets and parallel implementations based on reconfigurable hardware. Full article
(This article belongs to the Special Issue Recent Advances in Embedded Computing, Intelligence and Applications)
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Open AccessFeature PaperArticle
A Modular IoT Hardware Platform for Distributed and Secured Extreme Edge Computing
Electronics 2020, 9(3), 538; https://doi.org/10.3390/electronics9030538 - 24 Mar 2020
Abstract
The hardware of networked embedded sensor nodes is in continuous evolution, from those 8-bit MCUs-based platforms such as Mica, up to powerful Edge nodes that even include custom hardware devices, such as FPGAs in the Cookies platform. This evolution process comes up with [...] Read more.
The hardware of networked embedded sensor nodes is in continuous evolution, from those 8-bit MCUs-based platforms such as Mica, up to powerful Edge nodes that even include custom hardware devices, such as FPGAs in the Cookies platform. This evolution process comes up with issues related to the deployment of the Internet of Things, particularly in terms of performance and communication bottlenecks. Moreover, the associated integration process from the Edge up to the Cloud layer opens new security concerns that are key to assure the end-to-end trustability and interoperability. This work tackles these questions by proposing a novel embedded Edge platform based on an EFR32 SoC from Silicon Labs with Contiki-NG OS that includes an ARM Cortex M4 MCU and an IEEE 802.15.4 transceiver, used for resource-constrained low-power communication capabilities. This IoT Edge node integrates security by hardware, adding support for confidentiality, integrity and availability, making this Edge node ultra-secure for most of the common attacks in wireless sensor networks. Part of this security relies on an energy-efficient hardware accelerator that handles identity authentication, session key creation and management. Furthermore, the modular hardware platform aims at providing reliability and robustness in low-power distributed sensing application contexts on what is called the Extreme Edge, and for that purpose a lightweight multi-hop routing strategy for supporting dynamic discovery and interaction among participant devices is fully presented. This embedded algorithm has served as the baseline end-to-end communication capability to validate the IoT hardware platform through intensive experimental tests in a real deployment scenario. Full article
(This article belongs to the Special Issue Recent Advances in Embedded Computing, Intelligence and Applications)
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Open AccessFeature PaperArticle
High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images
Electronics 2019, 8(12), 1494; https://doi.org/10.3390/electronics8121494 - 06 Dec 2019
Abstract
Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and [...] Read more.
Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations. Full article
(This article belongs to the Special Issue Recent Advances in Embedded Computing, Intelligence and Applications)
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