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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (15 July 2022) | Viewed by 11576

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Prof. Dr. Luis Parrilla

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Universidad de Granada, Departamento de Electrónica y Tecnología de Computadores, Granada, Spain
Interests: FPGAs; cryptography; biosignal processing; computer arithmetic; hardware acceleration; smart instrumentation.
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Prof. Dr. Antonio García

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Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: reconfigurable instruments; biosignal processing; cryptography; computer arithmetic
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Prof. Dr. Encarnación Castillo

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Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain
Interests: biosignal processing; FPGA; smart instrumentation; computer arithmetic; cryptography
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

FPGAs are currently involved in a continuous update of characteristics and features, thus becoming the technology of choice for many final designs, with new fields of application arising. As a consequence, low-cost FPGAs are increasing the number of logic elements while reducing power consumption, becoming a valid option for IoT applications requiring high performance and/or high levels of security. On the other hand, the latest generations of high-performance FPGAs include embedded processors and high-speed memories within the same device, opening up new possibilities in the development of hardware accelerators, AI applications, database servers, and so on. This Special Issue, entitled “Recent FPGA Architectures and Applications”, is intended to present the latest advances in applications benefiting from new FPGA architectures and features, new applications of low-cost FPGAs to fields such as IoT or digital control, and the emerging applications of high-performance FPGAs to AI, high-performance servers, and hardware-accelerated systems.

Prof. Dr. Luis Parrilla
Prof. Dr. Antonio García
Prof. Dr. Encarnación Castillo
Guest Editors

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Published Papers (5 papers)

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Research

19 pages, 6409 KiB

Open AccessArticle

XML-Based Automatic NIOS II Multi-Processor System Generation for Intel FPGAs

by Haotian Cao and Uwe Meyer-Baese

Electronics 2022, 11(18), 2840; https://doi.org/10.3390/electronics11182840 - 08 Sep 2022

Cited by 2 | Viewed by 1715

Abstract

Many embedded systems are introducing processing units to accelerate the processing speed of tasks, such as for multi-media applications. The units are mostly customized designs. Another method of designing multi-unit systems is using pre-defined standard intellectual properties. However, the procedure of arranging IP cores in a system and maintaining a high performance as well are the remaining challenges. Implementing softcore processors on field-programmable gate arrays (FPGAs) is a relatively fast and inexpensive choice to design and validate a desired system. This paper describes the rapid prototyping of hardware/software co-design based on FPGAs. A novel system generator to effortlessly design a multiple NIOS II soft-processor core systems is also purposed. The NIOS II CPU is a configurable RISC processor designed by Altera/Intel and can be trimmed to complete specific tasks. The error-prone and time-consuming process of designing an IP block-based system is improved by the new novel system generator. The detail of the implementation of such system is discussed. To test the performance of a multi-NIOS II system, a parallel application is executed on 1-, 2-, 5-, and 10-core NIOS II systems separately. Test results prove the feasibility of the proposed methodology (for an FIR filter, a dual-core system is 29% faster than a single-core system; a 5-core system is 28% faster than the dual-core system). Full article

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)

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17 pages, 2453 KiB

Open AccessArticle

High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs

by Ali Ebrahim

Electronics 2022, 11(15), 2399; https://doi.org/10.3390/electronics11152399 - 31 Jul 2022

Cited by 2 | Viewed by 1506

Abstract

This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second, performance fine-tuning through high-level pragmas is explored to achieve the best possible throughput. Finally, a technique based on pre-processing the data stream in a small cache memory prior to updating the sketch is evaluated to reduce the dynamic power consumption. Using an Intel HLS compiler, a proposed optimized hardware version of the popular Count-Min sketch utilizing 80% of the embedded RAM in an Intel Arria 10 FPGA, achieved more than 3x the throughput of an unoptimized baseline implementation. Furthermore, the sketch update rate is significantly reduced when the input stream is skewed. This, in turn, minimizes the effect of high throughput on dynamic power consumption. Compared to FPGA sketches in the published literature, the presented sketch is the most well-rounded sketch in terms of features and versatility. In terms of throughput, the presented sketch is on a par with the fastest sketches fine-tuned at the Register Transfer Level (RTL). Full article

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)

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18 pages, 33899 KiB

Open AccessArticle

Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices

by Luis Parrilla, Antonio García, Encarnación Castillo, José Antonio Álvarez-Bermejo, Juan Antonio López-Villanueva and Uwe Meyer-Baese

Electronics 2022, 11(13), 2080; https://doi.org/10.3390/electronics11132080 - 02 Jul 2022

Cited by 4 | Viewed by 2083

Abstract

The development of devices for the Internet of Things (IoT) requires the rapid prototyping of different hardware configurations. In this paper, a modular hardware platform allowing to prototype, test and even implement IoT appliances on low-cost reconfigurable devices is presented. The proposed platform, named Dracon, includes a Z80-clone microprocessor, up to 64 KB of RAM, and 256 inputs/outputs (I/Os). These I/Os can be used to connect additional co-processors within the same FPGA, external co-processors, communications modules, sensors and actuators. Dracon also includes as default peripherals a UART for programming and accessing the microprocessor, a Real Time Clock, and an Interrupt Timer. The use of an 8-bit microprocessor allows the use of the internal memory of the reconfigurable device as program memory, thereby, enabling the implementation of a complete IoT device within a single low-cost chip. Indeed, results using a Spartan 7 FPGA show that it is possible to implement Dracon with only 1515 6-input LUTs while operating at a maximum frequency of 80 MHz, which results in a better trade-off in terms of area and performance than other less powerful and less versatile alternatives in the literature. Moreover, the presented platform allows the development of embedded software applications independently of the selected FPGA device, enabling rapid prototyping and implementations on devices from different manufacturers. Full article

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)

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15 pages, 3932 KiB

Open AccessArticle

A Real-Time FPGA Accelerator Based on Winograd Algorithm for Underwater Object Detection

by Liangwei Cai, Ceng Wang and Yuan Xu

Electronics 2021, 10(23), 2889; https://doi.org/10.3390/electronics10232889 - 23 Nov 2021

Cited by 3 | Viewed by 2428

Abstract

Real-time object detection is a challenging but crucial task for autonomous underwater vehicles because of the complex underwater imaging environment. Resulted by suspended particles scattering and wavelength-dependent light attenuation, underwater images are always hazy and color-distorted. To overcome the difficulties caused by these problems to underwater object detection, an end-to-end CNN network combined U-Net and MobileNetV3-SSDLite is proposed. Furthermore, the FPGA implementation of various convolution in the proposed network is optimized based on the Winograd algorithm. An efficient upsampling engine is presented, and the FPGA implementation of squeeze-and-excitation module in MobileNetV3 is optimized. The accelerator is implemented on a Zynq XC7Z045 device running at 150 MHz and achieves 23.68 frames per second (fps) and 33.14 fps when using MobileNetV3-Large and MobileNetV3-Small as the feature extractor. Compared to CPU, our accelerator achieves 7.5×–8.7× speedup and 52×–60× energy efficiency. Full article

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)

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13 pages, 40788 KiB

Open AccessArticle

Interference Signal Identification of Sensor Array Based on Convolutional Neural Network and FPGA Implementation

by Lin Huang, Xingguang Geng, Hao Xu, Yitao Zhang, Zhiqiang Li, Jun Zhang and Haiying Zhang

Electronics 2021, 10(22), 2867; https://doi.org/10.3390/electronics10222867 - 21 Nov 2021

Cited by 4 | Viewed by 1887

Abstract

The pulse carries important physiological and pathological information about the human body. The piezoresistive sensor used to capture vascular pulsation information has transitioned from a single-point to a sensor array. However, the interference signal between channels has become a key bottleneck restricting the development of the sensor array pulse diagnosis equipment. The sensor in contact with vascular pulsation obtains the pulse signal. When some sensors are displaced due to vascular pulsation, other sensors will be driven to move, which will produce interference signals. Signal interference is a common problem for sensor arrays, but few people have analyzed this problem from the perspective of the algorithm. In this paper, an interference signal recognition algorithm of the sensor array based on a convolutional neural network (CNN) is proposed. Firstly, a simple mechanical structure model was established to analyze the generation mechanism of interference signals in one MEMS sensor array acquisition system. Then, a CNN model with fewer parameters was designed for identifying interference signals. Finally, the CNN model was implemented on a field-programmable gate array (FPGA). The results show that the CNN algorithm could identify interference signals well, and the accuracy of the algorithm was 99.3%. The power consumption of the CNN accelerator was 0.673 W at a working frequency of 100 MHz. The interference signal identification algorithm is proposed to ensure the accurate analysis of array signals. FPGA implementation lays the foundation for the miniaturization and portability of the equipment. Full article

(This article belongs to the Special Issue Recent FPGA Architectures and Applications)

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