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4 pages, 126 KiB

Open AccessEditorial

Advances in Sensors-Centric Microprocessors and System-on-Chip

by Juan A. Gómez-Pulido and Miguel A. Vega-Rodríguez

Sensors 2012, 12(4), 4820-4823; https://doi.org/10.3390/s120404820 - 12 Apr 2012

Viewed by 6072

Abstract

Sensors-based systems are nowadays an extended technology for many markets due to their great potential in the collection of data from the environment and the processing of such data for different purposes. A typical example is the wireless sensor devices, where the outer [...] Read more.

Sensors-based systems are nowadays an extended technology for many markets due to their great potential in the collection of data from the environment and the processing of such data for different purposes. A typical example is the wireless sensor devices, where the outer temperature, humidity, luminosity and many other parameters can be acquired, measured and processed in order to build useful and fascinating applications that contribute to human welfare. In this scenario, the processing architectures of the sensors-based systems play a very important role. The requirements that are necessary for many such applications (real-time processing, low-power consumption, reduced size, reliability, security and many others) means that research on advanced architectures of Microprocessors and System-on-Chips (SoC) is needed to design and implement a successful product. In this sense, there are many challenges and open questions in this area that need to be addressed. [...] Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

Research

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13 pages, 327 KiB

Open AccessArticle

An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems

by Xu Yang and Hu He

Sensors 2012, 12(4), 4466-4478; https://doi.org/10.3390/s120404466 - 2 Apr 2012

Cited by 7 | Viewed by 7619

Abstract

The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems. However, as VLIW codes are mainly compiled statically, the performance of a VLIW [...] Read more.

The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems. However, as VLIW codes are mainly compiled statically, the performance of a VLIW processor is dominated by the behavior of its compiler. In this paper, we present an advanced compiler designed for a VLIW DSP named Magnolia, which will be used in sensor-based systems. This compiler is based on the Open64 compiler. We have implemented several advanced optimization techniques in the compiler, and fulfilled the O3 level optimization. Benchmarks from the DSPstone test suite are used to verify the compiler. Results show that the code generated by our compiler can make the performance of Magnolia match that of the current state-of-the-art DSP processors. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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17 pages, 1090 KiB

Open AccessArticle

Distributed Coding/Decoding Complexity in Video Sensor Networks

by Paulo J. Cordeiro and Pedro Assunção

Sensors 2012, 12(3), 2693-2709; https://doi.org/10.3390/s120302693 - 29 Feb 2012

Cited by 5 | Viewed by 7265

Abstract

Video Sensor Networks (VSNs) are recent communication infrastructures used to capture and transmit dense visual information from an application context. In such large scale environments which include video coding, transmission and display/storage, there are several open problems to overcome in practical implementations. This [...] Read more.

Video Sensor Networks (VSNs) are recent communication infrastructures used to capture and transmit dense visual information from an application context. In such large scale environments which include video coding, transmission and display/storage, there are several open problems to overcome in practical implementations. This paper addresses the most relevant challenges posed by VSNs, namely stringent bandwidth usage and processing time/power constraints. In particular, the paper proposes a novel VSN architecture where large sets of visual sensors with embedded processors are used for compression and transmission of coded streams to gateways, which in turn transrate the incoming streams and adapt them to the variable complexity requirements of both the sensor encoders and end-user decoder terminals. Such gateways provide real-time transcoding functionalities for bandwidth adaptation and coding/decoding complexity distribution by transferring the most complex video encoding/decoding tasks to the transcoding gateway at the expense of a limited increase in bit rate. Then, a method to reduce the decoding complexity, suitable for system-on-chip implementation, is proposed to operate at the transcoding gateway whenever decoders with constrained resources are targeted. The results show that the proposed method achieves good performance and its inclusion into the VSN infrastructure provides an additional level of complexity control functionality. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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26 pages, 720 KiB

Open AccessArticle

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

by Juan Valverde, Andres Otero, Miguel Lopez, Jorge Portilla, Eduardo De la Torre and Teresa Riesgo

Sensors 2012, 12(3), 2667-2692; https://doi.org/10.3390/s120302667 - 28 Feb 2012

Cited by 44 | Viewed by 9931

Abstract

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, [...] Read more.

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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22 pages, 2195 KiB

Open AccessArticle

Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

by Alejandro Castillo Atoche and Javier Vázquez Castillo

Sensors 2012, 12(3), 2539-2560; https://doi.org/10.3390/s120302539 - 24 Feb 2012

Cited by 5 | Viewed by 7197

Abstract

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed [...] Read more.

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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22 pages, 1008 KiB

Open AccessArticle

Parametric Dense Stereovision Implementation on a System-on Chip (SoC)

by Alfredo Gardel, Pablo Montejo, Jorge García, Ignacio Bravo and José L. Lázaro

Sensors 2012, 12(2), 1863-1884; https://doi.org/10.3390/s120201863 - 10 Feb 2012

Cited by 8 | Viewed by 8315

Abstract

This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and [...] Read more.

This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps) of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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14 pages, 511 KiB

Open AccessArticle

A Web Service-Based Framework Model for People-Centric Sensing Applications Applied to Social Networking

by David Nunes, Thanh-Dien Tran, Duarte Raposo, André Pinto, André Gomes and Jorge Sá Silva

Sensors 2012, 12(2), 1688-1701; https://doi.org/10.3390/s120201688 - 7 Feb 2012

Cited by 6 | Viewed by 9033

Abstract

As the Internet evolved, social networks (such as Facebook) have bloomed and brought together an astonishing number of users. Mashing up mobile phones and sensors with these social environments enables the creation of people-centric sensing systems which have great potential for expanding our [...] Read more.

As the Internet evolved, social networks (such as Facebook) have bloomed and brought together an astonishing number of users. Mashing up mobile phones and sensors with these social environments enables the creation of people-centric sensing systems which have great potential for expanding our current social networking usage. However, such systems also have many associated technical challenges, such as privacy concerns, activity detection mechanisms or intermittent connectivity, as well as limitations due to the heterogeneity of sensor nodes and networks. Considering the openness of the Web 2.0, good technical solutions for these cases consist of frameworks that expose sensing data and functionalities as common Web-Services. This paper presents our RESTful Web Service-based model for people-centric sensing frameworks, which uses sensors and mobile phones to detect users’ activities and locations, sharing this information amongst the user’s friends within a social networking site. We also present some screenshot results of our experimental prototype. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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13 pages, 806 KiB

Open AccessArticle

Fast Decision Algorithms in Low-Power Embedded Processors for Quality-of-Service Based Connectivity of Mobile Sensors in Heterogeneous Wireless Sensor Networks

by María D. Jaraíz-Simón, Juan A. Gómez-Pulido, Miguel A. Vega-Rodríguez and Juan M. Sánchez-Pérez

Sensors 2012, 12(2), 1612-1624; https://doi.org/10.3390/s120201612 - 7 Feb 2012

Cited by 6 | Viewed by 7587

Abstract

When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection [...] Read more.

When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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15 pages, 217 KiB

Open AccessArticle

An LDPC Decoder Architecture for Wireless Sensor Network Applications

by Andrea Dario Giancarlo Biroli, Maurizio Martina and Guido Masera

Sensors 2012, 12(2), 1529-1543; https://doi.org/10.3390/s120201529 - 6 Feb 2012

Cited by 18 | Viewed by 8472

Abstract

The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce the dissipated [...] Read more.

The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce the dissipated energy per transmitted bit with respect to uncoded communication. Different Low Density Parity Check (LDPC) codes are considered to this purpose and post layout results are shown for a low-area low-energy decoder, which offers percentage energy savings with respect to the uncoded solution in the range of 40%–80%, depending on considered environment, distance and bit error rate. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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20 pages, 1384 KiB

Open AccessArticle

Historical Building Monitoring Using an Energy-Efficient Scalable Wireless Sensor Network Architecture

by Juan V. Capella, Angel Perles, Alberto Bonastre and Juan J. Serrano

Sensors 2011, 11(11), 10074-10093; https://doi.org/10.3390/s111110074 - 25 Oct 2011

Cited by 26 | Viewed by 8611

Abstract

We present a set of novel low power wireless sensor nodes designed for monitoring wooden masterpieces and historical buildings, in order to perform an early detection of pests. Although our previous star-based system configuration has been in operation for more than 13 years, [...] Read more.

We present a set of novel low power wireless sensor nodes designed for monitoring wooden masterpieces and historical buildings, in order to perform an early detection of pests. Although our previous star-based system configuration has been in operation for more than 13 years, it does not scale well for sensorization of large buildings or when deploying hundreds of nodes. In this paper we demonstrate the feasibility of a cluster-based dynamic-tree hierarchical Wireless Sensor Network (WSN) architecture where realistic assumptions of radio frequency data transmission are applied to cluster construction, and a mix of heterogeneous nodes are used to minimize economic cost of the whole system and maximize power saving of the leaf nodes. Simulation results show that the specialization of a fraction of the nodes by providing better antennas and some energy harvesting techniques can dramatically extend the life of the entire WSN and reduce the cost of the whole system. A demonstration of the proposed architecture with a new routing protocol and applied to termite pest detection has been implemented on a set of new nodes and should last for about 10 years, but it provides better scalability, reliability and deployment properties. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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18 pages, 1788 KiB

Open AccessArticle

Real-Time Telemetry System for Amperometric and Potentiometric Electrochemical Sensors

by Wei-Song Wang, Hong-Yi Huang, Shu-Chun Chen, Kuo-Chuan Ho, Chia-Yu Lin, Tse-Chuan Chou, Chih-Hsien Hu, Wen-Fong Wang, Cheng-Feng Wu and Ching-Hsing Luo

Sensors 2011, 11(9), 8593-8610; https://doi.org/10.3390/s110908593 - 2 Sep 2011

Cited by 17 | Viewed by 17567

Abstract

A real-time telemetry system, which consists of readout circuits, an analog-to-digital converter (ADC), a microcontroller unit (MCU), a graphical user interface (GUI), and a radio frequency (RF) transceiver, is proposed for amperometric and potentiometric electrochemical sensors. By integrating the proposed system with the [...] Read more.

A real-time telemetry system, which consists of readout circuits, an analog-to-digital converter (ADC), a microcontroller unit (MCU), a graphical user interface (GUI), and a radio frequency (RF) transceiver, is proposed for amperometric and potentiometric electrochemical sensors. By integrating the proposed system with the electrochemical sensors, analyte detection can be conveniently performed. The data is displayed in real-time on a GUI and optionally uploaded to a database via the Internet, allowing it to be accessed remotely. An MCU was implemented using a field programmable gate array (FPGA) to filter noise, transmit data, and provide control over peripheral devices to reduce power consumption, which in sleep mode is 70 mW lower than in operating mode. The readout circuits, which were implemented in the TSMC 0.18-μm CMOS process, include a potentiostat and an instrumentation amplifier (IA). The measurement results show that the proposed potentiostat has a detectable current range of 1 nA to 100 μA, and linearity with an R² value of 0.99998 in each measured current range. The proposed IA has a common-mode rejection ratio (CMRR) greater than 90 dB. The proposed system was integrated with a potentiometric pH sensor and an amperometric nitrite sensor for in vitro experiments. The proposed system has high linearity (an R² value greater than 0.99 was obtained in each experiment), a small size of 5.6 cm × 8.7 cm, high portability, and high integration. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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26 pages, 1053 KiB

Open AccessArticle

Network Coding on Heterogeneous Multi-Core Processors for Wireless Sensor Networks

by Deokho Kim, Karam Park and Won W. Ro

Sensors 2011, 11(8), 7908-7933; https://doi.org/10.3390/s110807908 - 11 Aug 2011

Cited by 8 | Viewed by 8762

Abstract

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used [...] Read more.

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine. Full article

(This article belongs to the Special Issue Microprocessors and System-on-Chip)

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