E/E Architecture Synthesis: Challenges and Technologies
2. Basic Concepts
2.1. The Main Bottlenecks of Current E/E Architecture
2.2. The Main Technologies for Future’s E/E Architecture
- Type 1: also called Bare Metal or Native hypervisor, as it is installed and runs directly on top of the host’s hardware without using any host OS. This type of hypervisor has direct control over and access to hardware resources. For example, a type-1 hypervisor can assign a specific core to a partition (an execution environment managed by the hypervisor which uses the virtualized services) in such a way that other partitions cannot access that core.
- Type 2: also known as Hosted hypervisor. It runs as an application in the host OS and uses the hardware resources for its VMs by coordinating calls through the host’s OS. The host OS does not have any knowledge about this type of hypervisor and it treats it as any other normal process .
3. Technologies and Challenges
3.1. Task Mapping in Multi-Core Computing Units
3.1.1. Introduction to Task Mapping
3.1.2. Mapping Techniques
3.1.3. Optimization Parameters in Mapping
3.2. Technologies for Software Integration and Configuration in Design Process
- AADL Model Parser: This interprets and extracts system descriptions from an AADL specification coming from the OSATE tool. The module can access AADL elements such as components, services, buses, etc. The extracted parameters are sent to the Architecture Analysis Module, as an input, which supports the two interfaces for analyzing the model comprising Architecture Constraints Validation and Architecture Quality Evaluation Interface (see Figure 5).
- Architecture Constraints Validation Interface: As displayed in Figure 5, it provides a plug-in point for Constraint Evaluator modules that check a given architecture for constraint satisfaction.
- Architecture Quality Evaluation Interface: In this part, various quality evaluation functions can be taken into account. In ArcheOpterix, the Attribute Evaluator module performs quality evaluation functions, which can be extended for evaluated features. Current integrated features in ArcheOpterix are Service Reliability, Data Transmission Reliability, and Communication Overhead.
- Architecture Optimization Interface: This provides an opportunity to add new optimization algorithms to the framework. The current tool comprises Exact Algorithms, Genetic Algorithms, and Ant Colony Optimization .
4. Future Research Areas
- How to facilitate and automate the assignment of HPCU resources to safety-critical applications while verifying the satisfaction of the specified safety requirements in the design phase to compute a verified and optimized mapping configuration considering the predetermined optimization objectives?
- How to verify the fulfillment of the specified requirements (particularly safety-critical ones) after deployment of the derived configuration to the HPCU at run-time?
- How to evaluate the performance of the calculated mapping configuration at run-time focused on the specified optimization goals in design-time?
- How to discover the source of the conflict among defined constraints in our system while using the DSE approach to find the optimal solution in case of an infeasible solution?
Conflicts of Interest
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|E/E Configurator||Problem||Problem Attributes||Design Space Exploration|
|ArcheOpterix||Deployment and Mapping||Memory Consumption and Response time||Multi-Objective Optimization and Constraints Satisfaction|
including Component/Resource Selection,
Allocation, and Feature Configuration
|Response time||Multi-Objective Optimization|
|MechatronicUML||Model Checking, Deployment,|
Formal Analysis of the Requirements,
and the Design
|Allocation Specification Language||Constraints Satisfaction|
Resource Management, Performance
Simulation, and Validation
|Task Response Time, Scheduling, and|
Partitioning focused on Timing
|Multi-Objective Optimization |
and Constraints Satisfaction
|Autofocus3||Model Checking and Deployment||Schedule Synthesis and Latency||Optimization|
and Constraints Satisfaction
|Clafer||Model Analysis and Feature Modelling||Timing||Multi-Objective Optimization|
and Constraints Satisfaction
|OSATE||Model Analysis and Model Checking||Scheduling Analysis, End-to-End|
Latency, Safety Analysis, Computer
Budget Analysis, and Weight Analysis
excluding DSE method
|AAOL||Deployment and Mapping||Memory Usage, CPU Time, |
Network Bandwidth, and ASIL Level
|Multi-Objective Optimization |
and Constraints Satisfaction
|ASSIST||Deployment and Mapping||Redundancy, Scheduling, and |
Managing Shared Resources
|Multi-Objective Optimization |
and Constraints Satisfaction
|Deepcompass Framework||Model Analysis, Model Validation,|
|Task Completion Latency and |
Missing Deadline in Scheduling
|Multi-Objective Optimization |
and Constraints Satisfaction
|SCALL||Software Component Allocation||Heterogeneous Components Allocation, |
Bandwidth, and Communication Cost
|AQOSA||Software Clustering and Mapping||Task Latencies, Processor Utilization, and|
|Multi-Objective Optimization |
and Constraints Satisfaction
|SQUAT||Software Clustering||Response Time||Multi-Objective Optimization and Constraints Satisfaction|
|E/E Configurator||Optimization Algorithms||Safety-Related Attributes||Optimization Attributes|
|ArcheOpterix||Genetic Algorithm (GA), |
ParetoAnt Colony Algorithm (P-ACO),
Simulated Annealing (SA),
Ayesian Heuristic for Component
Deployment optimization (BHCDO),
Random Search Algorithm,
and Brute-Force Algorithms
|Reliability||Cost, data transmission reliability|
and communication overhead
|PerOpteryx||Genetic Algorithm (GA)||Reliability||Performance, Reliability, |
and Monetary Cost
|MechatronicUML||Not Applicable |
|APP4MC||Genetic Algorithm (GA)||Safety parallelization |
|Load Balancing, Energy Consumption,|
Memory Mapping, and
|Autofocus3||Meta Search, e.g., Binary Search||Safety Integrity Level||Timing and Communication Load|
|Clafer||Guided Improvement Algorithm (GIA)|
Using Alloy, Z3 SMT, and
Choco 3 CSP Solvers
|N.A.||Mass, End-to-End Latency, |
|OSATE||N.A.||FTA, FMEA, and|
|AAOL||Evolutionary Algorithms||ASIL Level||Cost, Weight|
|ASSIST||Heuristic approach |
e.g., Simulated Annealing
|Redundancy||Resource Usage, Weight, Power|
|Deepcompass Framework||Pareto approach||N.A.||Cost, Throughput, and |
|AQOSA||Nondominated Sorting Genetic Algorithm,|
Strength Pareto Evolutionary,
and S-metric Selection
|N.A.||Data Flow Latency, Architecture Cost, |
and Processor Usage
|SQUAT||Genetic Algorithm (GA)||N.A.||Response Time and |
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Askaripoor, H.; Hashemi Farzaneh, M.; Knoll, A. E/E Architecture Synthesis: Challenges and Technologies. Electronics 2022, 11, 518. https://doi.org/10.3390/electronics11040518
Askaripoor H, Hashemi Farzaneh M, Knoll A. E/E Architecture Synthesis: Challenges and Technologies. Electronics. 2022; 11(4):518. https://doi.org/10.3390/electronics11040518Chicago/Turabian Style
Askaripoor, Hadi, Morteza Hashemi Farzaneh, and Alois Knoll. 2022. "E/E Architecture Synthesis: Challenges and Technologies" Electronics 11, no. 4: 518. https://doi.org/10.3390/electronics11040518