This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a
A new controller based on a fractional-order synergetic controller (FOSC) is proposed for a three-level T-type inverter using a shunt active power filter (SAPF). The SAPF is designed to compensate for the reactive power and eliminate the current harm...
Renewable Energy Sources (RES) are widely used worldwide due to their positive effect on the environment, being sustainable, low cost, and controllable. The power generated from RESs must be configured to interface and perfectly synchronize with the...
The dynamic monitoring, control, and protection of modern power systems in real time require time-stamped electrical measurements to accurately estimate the bus voltage phasors using the state estimation function under normal and abnormal conditions....
The use of renewable energy sources (RESs) together with energy storage systems (ESSs) allows for smoothing power variations, thus improving power backup capabilities and power quality in the electric power grid. These applications require power conv...
This study presents a novel dual phase-locked loop two-dimensional synchronized motion modulation (TDSMM-DPLL) system designed to enhance the low-frequency detection capability of magnetoresistive (MR) sensors by effectively mitigating 1/f noise. The...
In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock fre...
In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11
Studying the dynamical behavior of micro- and nano-mechanical systems (MEMSs and NEMSs) is essential in various fields from nonlinear dynamics to quantum technologies. Hence, it is important to precisely monitor the mechanical properties of MEMS and...
The current work employs the HMC830 phase-locked loop chip to design a frequency synthesizer operating in the L-band. The frequency synthesizer can provide a local oscillation signal for the RF receiver front end. This article employs the phase-locke...
A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a cha...
The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1....
Digital phase-locked loop (DPLL) is currently the most commonly used for carrier tracking, and its performance can be easily evaluated by the loop bandwidth. Meanwhile, the Kalman filter-based tracking (KFT) method has been widely studied to further...
We report a coherent beam combining technique using a specific quasi-reinforcement learning scheme. A neural network learned by this method enables the tailoring and locking of a tiled beam array on any phase map. We present the experimental implemen...
The paper presents an automatic frequency calibration (AFC) technique for a charge pump-based phase-locked loop (CPPLL) with 5–6 μsec correction time. The architecture detects frequency offset in real time while keeping the loop active and p...
To improve the precision of the position and speed estimation in ultra-high-speed (UHS) permanent magnet synchronous motors (PMSM) without position sensors, multiple refinements to the traditional extended electromotive force (EEMF) estimation algori...
Phase-Locked Loops (PLLs) are fundamental building blocks in modern electronic systems, enabling precise frequency synthesis, signal synchronization, and clock generation. This paper provides a comprehensive system-level analysis of PLLs, covering th...
In the measurement process of cold atomic gravimeters, Raman laser plays an important role both in the state preparation stage and in the atomic interference stage. This paper discusses Raman laser generation techniques. The optical phase-locked loop...
Synchronization is a crucial problem in the grid-connected inverter’s control and operation. A phase-locked loop (PLL) is a typical grid synchronization strategy, which ought to have a high resistance to power system uncertainties since its sen...
Constant on-time (COT) buck converters offer fast transient responses and a simple architecture but face challenges like switching frequency variation, instability with low-equivalent series resistance (ESR) capacitors, and DC output voltage offset....
Solar energy solutions have become increasingly popular worldwide due to the growing need for renewable energy. This article presents a photovoltaic (PV) system connected to a three-phase power grid, modeled under varying climatic conditions. It cons...
In this paper, an improved single-phase second order generalized integrator (SOGI) fixed-frequency phase-locked loop (FFPLL) is presented. The proposed improvement comprises the modification of the PLL input signal estimated phase angle correction fa...
High-frequency (HF) communication is critical for applications such as over-the-horizon positioning and ionospheric detection. However, precise time-delay estimation in complex HF channels faces significant challenges from multipath fading, Doppler s...
The generation of high-quality wideband frequency sweeps presents a significant challenge, particularly in modern telecommunication, radar, and measurement systems where miniaturization is paramount. While phase-locked loops (PLLs) have become the do...
This paper presents a single-phase Shunt Active Power Filter (SAPF) with a multilevel converter based on an asymmetric full-bridge topology capable of producing five distinct voltage levels. The calculation of the SAPF compensation current is based o...
This article deals with the vector control in dq axes of a three-phase grid-connected photovoltaic system with single-stage topology and low-voltage-ride-through capability. The photovoltaic generator is built using an array of several series-paralle...
Secure communication for critical command nodes has emerged as a pivotal challenge in modern warfare, in particular considering the vulnerability of these nodes to electronic reconnaissance. To cope with the severe interference, this paper proposes a...
This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mix...
The presence of the DC components in the grid voltage adversely affects the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information. Several approaches were proposed to address the DC offset pr...
The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board sat...
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve st...
The improvement of power transmission efficiency (PTE) is an important issue in the design of a wireless power transfer (WPT) system. The WPT system with multiple transmitting (Tx) or receiving (Rx) coils is a way to improve the PTE. This paper deals...
This paper proposes a novel constant power factor loop in the V/f control strategy with stabilization for a permanent magnet synchronous motor (PMSM). The advantage of such an algorithm is the independence of the machine parameters, which vary under...
Discussed in this study is a bidirectional power control technique for a three-phase grid connected inverter under different unbalanced grid conditions. Prior researchers have focused on either solving the unbalanced problem or controlling the power....
This paper presents a non-iterative technique that generates reference current to manage operation of a three-phase four-wire shunt active power filter which employs a three-leg split capacitor voltage source inverter (VSI) topology. The proposed tec...
An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix I...
22 September 2025
This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning application...
In this research, a 14 nm high-performance computing application-specific integrated circuit was coated with a 5–20 nm Al2O3 thin film by atomic layer deposition in room-temperature conditions to study its performance in terms of reliability wi...
This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature...
When three-phase voltages are polluted with unbalance, DC offsets, or higher harmonics, it is a challenge to quickly detect their parameters such as phases, frequency, and amplitudes. This paper proposes a phase-locked loop (PLL) for the three-phase...
This paper demonstrates the design and implementation of an all-digital phase-locked loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique to show the feasibility and effectiveness of the ADPLL in the early desi...
This paper presents a rotation speed estimation and an indirect speed control method for a turbine-generator in a grid-connected 3-phase electrical power conversion system of an organic Rankine cycle (ORC) generation system. In addition to the genera...
With the increasing impedance coupling between inverters and grid caused by the phase-locked loop (PLL), traditional three-phase inverters suffer from the harmonic distortion or instability problems under weak grid conditions. Therefore, the admittan...
In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid...
This work proposes a structural enhancement and a new technique to design the loop filter (LF) of a third-order phase-locked loop (PLL) to enhance the PLL dynamic performance under abnormal grid conditions. The proposed PLL combines a moving average...
High penetration of renewable energy sources into isolated microgrids (µGs) is considered a critical challenge, as µGs’ operation at low inertia results in frequency stability problems. To solve this challenge, virtual inertia contr...
Optical phase locking is a critical technique in space coherent optical communication and active coherent laser beam combining. In a typical optical phase locking loop based on nonplanar ring oscillators, the pull-in range is normally less than 1 MHz...
Interior Permanent Magnet Synchronous Motor (IPMSM) motion-sensorless speed control necessitates precise knowledge of rotor flux, speed, and position. Due to numerous non-ideal aspects, such as converter nonlinearities, detection errors, integral ini...
Today, and especially with the growing interest in distributed renewable energy sources (DRESs), modern electric power systems are becoming more and more complex. In order to increase DRES penetration, grid side converter (GSC) control techniques req...
This paper presents a low-power continuous-time delta-sigma (CT-DS) analog-to-digital converter (ADC) for use in high-sensitivity automotive-grade sub-1 GHz receivers in emerging wireless sensors network applications. The proposed ADC employs a third...
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