PLL-Less Three-Phase Four-Wire SAPF with STF-dq0 Technique for Harmonics Mitigation under Distorted Supply Voltage and Unbalanced Load Conditions

Yap Hoon 1,2,* ID and Mohd Amran Mohd Radzi 1,2 ID 1 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia; amranmr@upm.edu.my 2 Centre for Advanced Power and Energy Research (CAPER), Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia * Correspondence: davidhoon0304@hotmail.com; Tel.: +603-8946-6322


Introduction
Ensuring good quality of power supply is often a challenging task due to ever-increasing usage of power electronics products. These products, which are more commonly known as nonlinear loads, draw non-sinusoidal currents and reactive power from the connected power system, and cause high harmonic distortion (indicated by total harmonic distortion (THD) values) in the source current and deteriorate overall power system efficiency (indicated by power factor). Moreover, in three-phase four-wire system, connection of single-phase loads and unequal loads distribution across the three phases causes excessive neutral currents. These power quality issues can partially be solved by applying passive filter. The viable solution is by using active power filter (APF) connected in parallel to the polluted power system. APFs that are applied in this manner are called the shunt-typed. The good thing about shunt active power filters (SAPFs) is that they are able to deal with unbalanced issues in the source current along with mitigating harmonic current and compensating reactive power.
For application in three-phase four-wire system, SAPFs are available in two basic topologies. First, three-leg split capacitor topology where the middle-point of its dc-link is connected to the neutral Figure 1 shows power circuit arrangement and control structure of a three-phase three-leg four-wire SAPF. A standard two-level inverter with two split dc-link capacitors (serving as the SAPF) is connected to the operating power system at point of common coupling (PCC) between the power supply and nonlinear loads. Note that there is an output filter interfacing between the SAPF and the connected power system. Its main purpose is to minimize switching ripples generated by SAPF so that mitigating opposition current (referred here as injection current i inj ) can effectively be injected into any polluted power system to cancel out harmonic current. Furthermore, the middle-point of the two dc-link capacitors is connected to the return neutral wire N to minimize neutral current. In addition, while performing mitigation function, a certain amount of current (referred here as dc-link charging current i dc ) is also drawn by the SAPF to regulate voltage across its dc-link capacitors. In a three-phase four-wire power system, the connected nonlinear loads can be of single-phase balanced/unbalanced and three-phase balanced loads. When the SAPF is installed and functioning properly, harmonic current and excessive neutral current in the polluted power system will slowly be removed and eventually the source current will be balanced and regain its sinusoidal appearance with fundamental frequency, and neutral current will be maintained at zero.
Energies 2018, 11, x FOR PEER REVIEW 3 of 29 technique is presented in Section 4, focusing on the implemented enhancements. All simulation findings are presented and thoroughly discussed in Section 5. Finally, a brief conclusion is provided to highlight contributions of this work. Figure 1 shows power circuit arrangement and control structure of a three-phase three-leg four-wire SAPF. A standard two-level inverter with two split dc-link capacitors (serving as the SAPF) is connected to the operating power system at point of common coupling (PCC) between the power supply and nonlinear loads. Note that there is an output filter interfacing between the SAPF and the connected power system. Its main purpose is to minimize switching ripples generated by SAPF so that mitigating opposition current (referred here as injection current ) can effectively be injected into any polluted power system to cancel out harmonic current. Furthermore, the middle-point of the two dc-link capacitors is connected to the return neutral wire to minimize neutral current. In addition, while performing mitigation function, a certain amount of current (referred here as dc-link charging current ) is also drawn by the SAPF to regulate voltage across its dc-link capacitors. In a three-phase four-wire power system, the connected nonlinear loads can be of single-phase balanced/unbalanced and three-phase balanced loads. When the SAPF is installed and functioning properly, harmonic current and excessive neutral current in the polluted power system will slowly be removed and eventually the source current will be balanced and regain its sinusoidal appearance with fundamental frequency, and neutral current will be maintained at zero.   To effectively manage operation of SAPF in a three-phase four-wire system, its control system needs to perform few control procedures which include extraction of synchronization phases (sin & cos) from source voltage v S , extraction of harmonic current from load current i L , estimation of I dc (magnitude of the dc-link charging current i dc ) and I balance (balancing current) from split dc-link capacitor voltages (V dc1 and V dc2 ), derivation of reference current i inj, re f by using all the signals obtained in the previous procedures, and generation of switching pulses based on the generated reference current i inj, re f . It is important to note that operation of a typical SAPF is fully based on characteristic of the generated reference current. In this work, other than mitigation of harmonic current, the SAPF is also needed to regulate its dc-link voltage and ensure voltage balance across its split dc-link capacitors. Hence, the generated reference current must contain details on system's harmonics, compatible phases to ensure synchronized operation, amount of dc-link charging current to maintain constant dc-link voltage and balancing current to manage voltage balance of the two split dc-link capacitors.

Ideal / Non-ideal
This manuscript emphasizes on the control procedure of generating reference current where it is performed according to dq0 principle. Further details are presented in Sections 3 and 4. Meanwhile, to regulate dc-link voltage and maintain voltage balance of the split dc-link capacitor, the conventional proportional-integral (PI) technique is adopted due to its straightforward feature [1,11]. Lastly, to generate switching pulses, a standard hysteresis band current control (HBC) technique is applied as it offers the benefits of structure simplicity and quick current controllability [1,2,6]. Figure 2 shows control structure of a standard dq0 technique which is commonly applied for the purpose of generating reference current. According to dq0 principle, extraction of harmonic current from load current is performed on dq0-frames where the load current i Labc (in abc-domain) is first transformed into αβ0-domain by using Clarke-matrix expressed as Equation (1) and then into dq0-frames by using Park-matrix expressed as Equation (2).

Working Principle of the Standard dq0 Technique
Note that sin(ωt) and cos(ωt) denote synchronization reference phases which are particularly delivered by a PLL.
Let the three-phase load current expressed in matrix form be i Labc = [i La i Lb i Lc ] T . Hence, by using Equation (1), the corresponding representation in αβ0-domain can be expressed as: Subsequently, load current i Lαβ in αβ-domain is further transformed into dq-frames according to Equation (4). Note that 0-domain of αβ0-domain is not required in the transformation process, and it is directly applied as 0-frame of dq0-frames. In other words, 0-domain is equivalent to 0-frame. [ In dq-frames, as a consequence of harmonic contamination, the load current signal contains both fundamental (stationary dc) and harmonic (oscillating ac) elements. Hence, the following relationship can be formed: where ( ) and ( ) , respectively, denote the dc and ac elements of the load current in d-frame. The same representation applies to the elements of load current in q-frame. Note that the stationary dc element of d-frame represents the magnitude of fundamental load current whereas the oscillating ac element represents the magnitude of harmonic current. On the other hand, q-frame contains phase information of the load current. Not to forget, 0-frame of dq0-frames which is directly taken from that of αβ0-domain is needed to maintain dc-link voltage balance. In other words, the ac element of d-frame load current ( ) , q-frame load current and 0-frame load current 0 are three distinct unwanted parts of load currents that represent harmonic, reactive and unbalanced currents, respectively.
Hence, in order to remove those unwanted signals, to maintain constant dc-link voltage and to maintain voltage balance across the two split dc-link capacitors, the reference current is derived by considering all those factors according to the following approach: where inverse Park-matrix and inverse Clarke-matrix 0 are given as follows: In dq-frames, as a consequence of harmonic contamination, the load current signal contains both fundamental (stationary dc) and harmonic (oscillating ac) elements. Hence, the following relationship can be formed: where i Ld (dc) and i Ld (ac) , respectively, denote the dc and ac elements of the load current in d-frame.
The same representation applies to the elements of load current in q-frame. Note that the stationary dc element of d-frame represents the magnitude of fundamental load current whereas the oscillating ac element represents the magnitude of harmonic current. On the other hand, q-frame contains phase information of the load current. Not to forget, 0-frame of dq0-frames which is directly taken from that of αβ0-domain is needed to maintain dc-link voltage balance. In other words, the ac element of d-frame load current i Ld(ac) , q-frame load current i Lq and 0-frame load current i L0 are three distinct unwanted parts of load currents that represent harmonic, reactive and unbalanced currents, respectively. Hence, in order to remove those unwanted signals, to maintain constant dc-link voltage and to maintain voltage balance across the two split dc-link capacitors, the reference current i inj(abc), re f is derived by considering all those factors according to the following approach: where inverse Park-matrix T dq αβ and inverse Clarke-matrix T αβ0 abc are given as follows: Meanwhile, I dc symbolizes the amount of dc-link charging current i dc needed to maintain constant dc-link voltage at desired level (denoted as V dc, re f ) and compensate losses associated with switching operation of SAPF, and I balance symbolizes the amount of balancing current needed to maintain the voltage balance.
The oscillating ac element of d-frame load current i Ld(ac) applied in Equation (6) can be obtained by filtering directly the d-frame load current with a high-pass filter (HPF) [1,6,12]. It is worth noting that in some dq0 techniques, the oscillating ac element is also obtained indirectly by using low-pass filter (LPF) associated with a simple calculation, in which the LPF is first applied to obtain the stationary dc element i Ld(dc) and is then subtracted from the actual d-frame load current i Ld [13][14][15]. Next, I dc is estimated by minimizing the error e 1 (t) resulted between reference dc-link voltage V dc, re f and the total instantaneous dc-link voltage (V dc (t) = V dc1 (t) + V dc2 (t)) with a PI controller. Mathematically, the approach can be expressed as: where k p1 and k i1 are the two constant values that respectively symbolize proportional and integral gains of PI 1 (first PI) controller. In this work, the values are set to be 0.3 and 2, respectively. Similarly, a PI controller is applied to estimate I balance by minimizing the error e 2 (t) resulted between the two split dc-link capacitors. Mathematically, the approach can be expressed as: where k p2 and k i2 are the two constant values that respectively symbolize proportional and integral gains of PI 2 (second PI) controller. The values are set to be 0.02 and 0.1, respectively. Figure 3 presents a block diagram that illustrates control structure and particulars of the proposed STF-dq0 technique. Basically, the proposed STF-dq0 technique generates reference current in a similar manner to that of a standard dq0 technique where both techniques perform according to the consecutive transformation sequences of "abc-αβ0-dq0-αβ0-abc". However, in the proposed technique, two modifications are made to further enhance capability of SAPF in performing its intended functions. First, the conventional PLL circuit is removed and replaced with a straightforward synchronization technique. Second, instead of applying HPF to perform direct extraction of harmonic element on dq0-frames, a self-tuning-filter (STF) is employed to extract the harmonic element indirectly on αβ0-domain (an earlier transformation stage before entering the dq0-frames).  In the proposed STF-dq0 technique, the process of extracting synchronization phases from the source voltage is rather straightforward and non-iterative. Let the three-phase source voltage expressed in matrix form be = [ ] T , and by using Clarke-transform matrix (considers only two phases αβ-domain), the source voltage signals (in abc-domain) can be transformed into αβ-domain according to:

Working Principle the Proposed STF-dq0 Technique
where In αβ-domain, under influence of distortions, the voltage signals can respectively be decomposed into fundamental and harmonic elements. Hence, the following relationship can be formed: where ( ) and ( ) denote the fundamental (dc) and harmonic (ac) elements of source voltage in α-domain, respectively. The same representation applies to element of source voltages in β-domain. To generate synchronization phases, the dc elements in both αβ-domain are required. A self-tuning filtering approach [16] is applied to extract the dc elements. The applied STF is capable of suppressing all the harmonic elements existed in the distorted voltage signals and thus improving quality of the extracted synchronization phases. As revealed in [16][17][18], the transfer function (after performing Laplace transformation) of a typical STF can be expressed as follow: In the proposed STF-dq0 technique, the process of extracting synchronization phases from the source voltage is rather straightforward and non-iterative. Let the three-phase source voltage expressed in matrix form be v Sabc = [v Sa v Sb v Sc ] T , and by using Clarke-transform matrix (considers only two phases αβ-domain), the source voltage signals (in abc-domain) can be transformed into αβ-domain according to: where In αβ-domain, under influence of distortions, the voltage signals can respectively be decomposed into fundamental and harmonic elements. Hence, the following relationship can be formed: where v Sα(dc) and v Sα(ac) denote the fundamental (dc) and harmonic (ac) elements of source voltage in α-domain, respectively. The same representation applies to element of source voltages in β-domain.
To generate synchronization phases, the dc elements in both αβ-domain are required. A self-tuning filtering approach [16] is applied to extract the dc elements. The applied STF is capable of suppressing all the harmonic elements existed in the distorted voltage signals and thus improving quality of the extracted synchronization phases. As revealed in [16][17][18], the transfer function (after performing Laplace transformation) of a typical STF can be expressed as follow: where K 1 is a constant gain parameter and f c1 is the cutoff frequency of STF 1 (first STF). In this work, the values are set to be 20 and 50 Hz, respectively. With availability of v Sα(dc) and v Sβ(dc) , the synchronization phases, sin(ωt) and cos(ωt) can be obtained according to following approach: By using Equation (18), the service from conventional PLL can be neglected and the synchronization phases can now effectively be generated regardless of any distortions in the source voltage.
On the other hand, for harmonic extraction, a STF is also employed to perform indirect extraction of harmonic elements from the load current on αβ-domain. By using Equation (3), the three-phase load current in abc-domain is first transformed into αβ-domain. Focusing only on αβ-domain (0-domain does not involve in harmonic extraction), due to harmonic contamination, the load current signals i Lαβ can respectively be decomposed into fundamental and harmonic elements. Hence, the following relationship can be formed: where i Lα(dc) and i Lα(ac) denote the fundamental (dc) and harmonic (ac) elements of load current in α-domain, respectively. The same representation applies to elements of load current in β-domain.
The transfer function (after performing Laplace transformation) of STF applied to extract the dc elements (i Lα(dc) and i Lβ(dc) ) of load current in αβ-domain is given as follows: where K 2 is a constant gain parameter and f c2 is the cutoff frequency of STF 2 (second STF). In this work, the values are set to be 20 and 50 Hz, respectively. With availability of dc elements (i Lα(dc) and i Lβ(dc) ), the ac elements (i Lα(ac) and i Lβ(ac) ) can be obtained by using simple calculation expressed as: From Equation (21), it can be seen that according to this STF approach, the ac elements are obtained by subtracting the dc elements (extracted in advance using the STF) from the actual load current signal in αβ-domain i Lαβ . Therefore, in this manner, the harmonic or ac elements are said to be extracted indirectly.
Next, the ac elements obtained from Equation (21) and synchronization phases obtained from Equation (18) are applied to perform transformation of αβ-domain into d-frame (contains only ac elements) according to the following approach: i Ld(ac) = i Lα(ac) sin(ωt) + i Lβ(ac) cos(ωt) (22) and meanwhile, the original load current signal in αβ-domain i Lαβ and the similar synchronization phases are applied to perform transformation of αβ-domain into q-frame according to the following approach: Note that 0-domain of αβ0-domain does not need to be transformed, and it is directly applied as 0-frame of dq0-frames. Finally, together with I dc (obtained from Equation (10)) and I balance (obtain from Equation (12)), Equations (6) and (7) are applied to generate the reference current i inj(abc), re f .

Results and Discussion
Simulation work which includes connection of SAPF circuits, design of its control system, and performance assessment of the proposed STF-dq0 technique is performed in MATLAB-Simulink platform (R2012a). Figure 4 shows the simulation model developed for this work. It is constructed using simple Simulink-blocks, and is executed in discrete environment. A standard two-level inverter with split dc-link capacitors of 3300 µF (each) is employed as the SAPF. Its output is connected to a simple 5 mH L-typed filter to minimize switching ripples. The line inductance is set to be 1 mH. For this work, the reference dc-link voltage is set to be 880 V (440 V for each split capacitor). The procedures applied for designing and determining parameter specifications of the SAPF are reported in [19][20][21]. Meanwhile, for the sources of harmonics, two types of nonlinear loads are considered. The first nonlinear load comprises of three single-phase nonlinear loads distributed unequally (in unbalanced manner) across the three phases of the connected power system (referred here as Load 1). The second nonlinear load comprises of three unbalanced single-phase nonlinear loads connected in parallel with a balanced three-phase nonlinear load (referred here as Load 2). Particulars of Loads 1 and 2 are summarized in Table 1. Analysis is performed in a comparative manner, i.e., by benchmarking performance demonstrated by SAPF while applying the proposed STF-dq0 technique, with the one using the standard dq0 technique. Steady-state simulation studies are conducted, considering four scenarios of source voltages, i.e., in scenario A, a sinusoidal-balanced source voltage, in scenario B, non-sinusoidal-balanced source voltage, in scenario C, sinusoidal-unbalanced source voltage, and in scenario D, non-sinusoidal-unbalanced source voltage. For these four scenarios, particulars of the source voltages applied are given as follows:

Sinusoidal-Balanced Source Voltage (Scenario A)
In Scenario A, an ideal situation of sinusoidal-balanced source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 5-9. Meanwhile, Table 2 summarizes the findings in comparative manner. Referring to Figure 5, it can clearly be observed that both the proposed STF-dq0 and standard dq0 techniques are able to accurately detect synchronization phase value ωt (appear in the form of sawtooth wave-shape) from a sinusoidal-balanced source voltage. Next, from Figure 6, both techniques are revealed to have effectively directed their respective SAPF in mitigating harmonic currents generated by Loads 1, where the source currents are found to have regained sinusoidal shape with THD values (as tabulated in Table 2) well-maintained below the 5% harmonic limit set by IEEE standard 519 [22]. Note that no significant differences can be observed between the THD values resulted by the proposed STF-dq0 and standard dq0 techniques. In addition, it also can be seen that high neutral currents caused by connection of single-phase loads has effectively been reduced by both SAPFs, proving the ability of both techniques in removing excessive neutral currents.
Furthermore, as indicated in Table 2, large phase differences that resulted between the source current and voltage have been minimized by both SAPFs. In other words, it proves that both techniques are able to effectively synchronize operation of SAPF with the operating power system. This is basically due to the accurate synchronization phase value ωt detected by both techniques (as indicated in Figure 5). As a result, the source current seems to work in phase with the source voltage and thus it leads to almost unity power factor of 0.999. Similar findings can be observed for Load 2, as indicated in Figure 8 and Table 2. Therefore, as an overall, both techniques show almost similar performances when operating under sinusoidal-balanced source voltage scenario. currents caused by connection of single-phase loads has effectively been reduced by both SAPFs, proving the ability of both techniques in removing excessive neutral currents. Furthermore, as indicated in Table 2, large phase differences that resulted between the source current and voltage have been minimized by both SAPFs. In other words, it proves that both techniques are able to effectively synchronize operation of SAPF with the operating power system. This is basically due to the accurate synchronization phase value detected by both techniques (as indicated in Figure 5). As a result, the source current seems to work in phase with the source voltage and thus it leads to almost unity power factor of 0.999. Similar findings can be observed for Load 2, as indicated in Figure 8 and Table 2. Therefore, as an overall, both techniques show almost similar performances when operating under sinusoidal-balanced source voltage scenario.
Other than effective harmonic mitigation, ability to regulate dc-link voltage is also an important feature of SAPF, thus must thoroughly be assessed. Figures 7 and 9 provide the related results. From the findings, while applying the proposed STF-dq0 technique, the SAPF is found to have effectively regulated and maintained its dc-link voltage at the desired level of 880 V, for both Loads 1 and 2. Similarly, it is also clear from the findings that voltages across the two split dc-link capacitors ( 1 and 2 ) are evenly regulated at half the value of overall dc-link voltage , i.e., 440 V. This implies that the two PI techniques applied respectively for regulating the dc-link voltage and ensuring voltage balance of the two split dc-link capacitors have performed effectively and are compatible with the proposed STF-dq0 technique. Other than effective harmonic mitigation, ability to regulate dc-link voltage is also an important feature of SAPF, thus must thoroughly be assessed. Figures 7 and 9 provide the related results. From the findings, while applying the proposed STF-dq0 technique, the SAPF is found to have effectively regulated and maintained its dc-link voltage at the desired level of 880 V, for both Loads 1 and 2. Similarly, it is also clear from the findings that voltages across the two split dc-link capacitors (V dc1 and V dc2 ) are evenly regulated at half the value of overall dc-link voltage V dc , i.e., 440 V. This implies that the two PI techniques applied respectively for regulating the dc-link voltage and ensuring voltage balance of the two split dc-link capacitors have performed effectively and are compatible with the proposed STF-dq0 technique.
Scenario A.

Non-Sinusoidal-Balanced Source Voltage (Scenario B)
In Scenario B, a non-sinusoidal-balanced (harmonic distorted) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 10-14. Meanwhile, Table 3 summarizes the findings in comparative manner. Referring to Figure 10, it can clearly be observed that the proposed STF-dq0 technique effectively detects synchronization phase value (appear in the form of sawtooth wave-shape) from a non-sinusoidal-balanced source voltage, where the detected phase value is found to accurately match the desired phase value. In contrast, for the standard 0 technique, discrepancies existed between the detected and desired phase value, where the resulted sawtooth waveform of the detected phase value is observed to be oscillating along the desired phase value. This implies that the standard 0 technique cannot work as desired when the source voltage suffers from distortion.

Non-Sinusoidal-Balanced Source Voltage (Scenario B)
In Scenario B, a non-sinusoidal-balanced (harmonic distorted) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 10-14. Meanwhile, Table 3 summarizes the findings in comparative manner. Referring to Figure 10, it can clearly be observed that the proposed STF-dq0 technique effectively detects synchronization phase value ωt (appear in the form of sawtooth wave-shape) from a non-sinusoidal-balanced source voltage, where the detected phase value is found to accurately match the desired phase value. In contrast, for the standard dq0 technique, discrepancies existed between the detected and desired phase value, where the resulted sawtooth waveform of the detected phase value is observed to be oscillating along the desired phase value. This implies that the standard dq0 technique cannot work as desired when the source voltage suffers from distortion.

Non-Sinusoidal-Balanced Source Voltage (Scenario B)
In Scenario B, a non-sinusoidal-balanced (harmonic distorted) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 10-14. Meanwhile, Table 3 summarizes the findings in comparative manner. Referring to Figure 10, it can clearly be observed that the proposed STF-dq0 technique effectively detects synchronization phase value (appear in the form of sawtooth wave-shape) from a non-sinusoidal-balanced source voltage, where the detected phase value is found to accurately match the desired phase value. In contrast, for the standard 0 technique, discrepancies existed between the detected and desired phase value, where the resulted sawtooth waveform of the detected phase value is observed to be oscillating along the desired phase value. This implies that the standard 0 technique cannot work as desired when the source voltage suffers from distortion.         Next, referring to Figure 11, it can be seen that while using the proposed STF-dq0 technique, SAPF is observed to have successfully mitigated harmonic currents generated by Load 1, where the source currents have regained sinusoidal shape with THD values (as tabulated in Table 3) complying with the 5% harmonic limit. In contrast, SAPF that applies the standard dq0 technique is only capable of reducing distortion level suffered by the source currents but it fails to provide mitigation performance that complies with IEEE standard 519. In this case, the mitigated source currents fail to recover the desired sinusoidal shape and the recorded THD values are far beyond 5%. Nevertheless, both techniques are able to remove excessive neutral currents caused by connection of single-phase loads.
Furthermore, as indicated in Table 3, both techniques are able to direct their respective SAPF in minimizing the large phase differences that resulted between the source current and voltage. With minimum phase differences, an almost unity power factor of 0.999 can be achieved when the proposed STF-dq0 technique is applied. In contrast, due to high-level of distortion retained in the mitigated source current, the standard dq0 technique can only provide a power factor up to 0.997 even though the phase differences have been minimized. Similar findings can be observed for Load 2, where the proposed STF-dq0 technique is revealed to outperform the standard dq0 technique when operating under non-sinusoidal-balanced source voltage scenario (as indicated in Figure 13 and Table 3).
Moreover, the assessment on behavior of dc-link voltage is also conducted to confirm correct operation of SAPF under Scenario B, while applying the proposed STF-dq0 technique. Figures 12 and 14 provide the related results recorded for Loads 1 and 2, respectively. As expected from the findings, all dc-link voltages of the SAPF are effectively regulated and maintained at the desired level, i.e., at 880 V for the overall dc-link voltage V dc and at 440 V (half of overall dc-link voltage) for the voltages across two split dc-link capacitors (V dc1 and V dc2 ). Hence, once again, it is certain that the proposed STF-dq0 technique can work effectively together with the two PI techniques applied respectively for regulating the dc-link voltage and ensuring voltage balance of the two split dc-link capacitors, and eventually directed the SAPF to work as desired under non-sinusoidal-balanced source voltage scenario.

Sinusoidal-Unbalanced Source Voltage (Scenario C)
In Scenario C, a sinusoidal-unbalanced (magnitude unbalanced) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 15-19. Meanwhile, Table 4 summarizes the findings in comparative manner. Based on Figure 15, the synchronization phase value ωt (appear in the form of sawtooth wave-shape) detected by the proposed STF-dq0 technique is found to work in accordance with the desired phase value. In contrast, for the standard dq0 technique, minor discrepancies can be observed between the detected and desired phase value. Hence, it implies that the standard dq0 technique cannot work exactly as desired when the magnitude of a three-phase source voltage is unbalanced across the three phases.
Subsequently, from Figure 16, it is obvious that by using the proposed STF-dq0 technique, SAPF have successfully mitigated harmonic currents generated by Load 1, where the source currents have regained sinusoidal shape with THD values (as tabulated in Table 4) complying with the 5% harmonic limit. In contrast, SAPF that applies the standard dq0 technique fails to perform in accordance to IEEE standard 519, where the recorded THD values are beyond 5% and the mitigated source currents fail to regain a complete sinusoidal shape. Nevertheless, both techniques are able to remove excessive neutral currents caused by connection of single-phase loads. Furthermore, as indicated in Table 4, both techniques are found to be able to direct their respective SAPF in minimizing the large phase differences that resulted between the source current and voltage. With minimum phase differences, an almost unity power factor of 0.999 can be achieved when the proposed STF-dq0 technique is applied. However, due to higher distortion level of the mitigated source current, the standard dq0 technique can only provide a power factor up to 0.998 even though the phase differences have been minimized.
On the other hand, for the case of Load 2 as illustrated in Figure 18, both the proposed STF-dq0 and the standard dq0 techniques are found to perform effectively as the THD values have been maintained below the 5% harmonic limit, excessive neutral current have been removed, the large phase differences have been minimized, and almost unity power factor of 0.999 is achieved. Nevertheless, the proposed STF-dq0 technique is revealed to outperform the standard dq0 technique by providing THD values of 1.88-2.13% lower (as indicated in Table 4). Hence, as an overall, judging from the performance of each technique in dealing with Loads 1 and 2, the proposed STF-dq0 technique can be claimed to be more reliable than the standard dq0 technique when they are required to work under sinusoidal-unbalanced source voltage scenario. proposed STF-dq0 technique is applied. However, due to higher distortion level of the mitigated source current, the standard dq0 technique can only provide a power factor up to 0.998 even though the phase differences have been minimized. On the other hand, for the case of Load 2 as illustrated in Figure 18, both the proposed STF-dq0 and the standard dq0 techniques are found to perform effectively as the THD values have been maintained below the 5% harmonic limit, excessive neutral current have been removed, the large phase differences have been minimized, and almost unity power factor of 0.999 is achieved. Nevertheless, the proposed STF-dq0 technique is revealed to outperform the standard dq0 technique by providing THD values of 1.88-2.13% lower (as indicated in Table 4). Hence, as an overall, judging from the performance of each technique in dealing with Loads 1 and 2, the proposed STF-dq0 technique can be claimed to be more reliable than the standard dq0 technique when they are required to work under sinusoidal-unbalanced source voltage scenario.          Moreover, assessment on behavior of dc-link voltage is also conducted to further justify that the SAPF is working correctly under Scenario C, while applying the proposed STF-dq0 technique. Figures 17 and 19 provide the related results obtained for Loads 1 and 2, respectively. As expected, all dc-link voltages of the SAPF are effectively regulated and maintained at the desired level, i.e., overall dc-link voltage at 880 V and voltages across the two split dc-link capacitors ( 1 and 2 ) at 440 V (half of overall dc-link voltage). Hence, once again, it is certain that the SAPF can work appropriately under sinusoidal-unbalanced source voltage scenario while applying the proposed STF-dq0 technique.

Non-Sinusoidal-Unbalanced Source Voltage (Scenario D)
In Scenario D, a non-sinusoidal-unbalanced (harmonic distorted and magnitude unbalanced) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 20-24. Meanwhile, Table 5 summarizes the findings in comparative manner. As shown in Figure 20, the synchronization phase value (appear in the form of sawtooth wave-shape) detected by the proposed STF-dq0 technique is in line with the desired phase value. In contrast, for the standard dq0 technique, the detected phase value seems to be oscillating along the desired phase value. Hence, once again the findings show that the proposed STF-dq0 technique can accurately track the desired phase value when the source voltage is distorted and unbalanced, while the standard dq0 technique has failed to do so.
Next, from Figures 21 and 23, it is clear that by using the proposed STF-dq0 technique, the SAPF have successfully mitigated harmonic currents generated by Loads 1 and 2, where the mitigated source currents for both cases have regained sinusoidal shape with THD values (as tabulated in Table 5) complying with the 5% harmonic limit. However, SAPF that applies the standard dq0 technique fails to comply with IEEE standard 519 in both cases, where the recorded THD values are beyond 5% and the mitigated source currents fail to recover the desired sinusoidal shape. Nevertheless, both techniques are able to remove excessive neutral currents caused by connection of single-phase loads.
In addition, as indicated in Table 5, both techniques have effectively minimized the large phase differences between the source current and voltage caused by connection of Loads 1 and 2. With minimum phase differences, almost unity power factor of 0.999 can be achieved when the proposed STF-dq0 technique is applied. However, due to higher distortion level of the mitigated source Moreover, assessment on behavior of dc-link voltage is also conducted to further justify that the SAPF is working correctly under Scenario C, while applying the proposed STF-dq0 technique. Figures 17 and 19 provide the related results obtained for Loads 1 and 2, respectively. As expected, all dc-link voltages of the SAPF are effectively regulated and maintained at the desired level, i.e., overall dc-link voltage V dc at 880 V and voltages across the two split dc-link capacitors (V dc1 and V dc2 ) at 440 V (half of overall dc-link voltage). Hence, once again, it is certain that the SAPF can work appropriately under sinusoidal-unbalanced source voltage scenario while applying the proposed STF-dq0 technique.

Non-Sinusoidal-Unbalanced Source Voltage (Scenario D)
In Scenario D, a non-sinusoidal-unbalanced (harmonic distorted and magnitude unbalanced) source voltage is considered. All the simulation waveforms obtained under this scenario are shown in Figures 20-24. Meanwhile, Table 5 summarizes the findings in comparative manner. As shown in Figure 20, the synchronization phase value ωt (appear in the form of sawtooth wave-shape) detected by the proposed STF-dq0 technique is in line with the desired phase value. In contrast, for the standard dq0 technique, the detected phase value seems to be oscillating along the desired phase value. Hence, once again the findings show that the proposed STF-dq0 technique can accurately track the desired phase value when the source voltage is distorted and unbalanced, while the standard dq0 technique has failed to do so.
Next, from Figures 21 and 23, it is clear that by using the proposed STF-dq0 technique, the SAPF have successfully mitigated harmonic currents generated by Loads 1 and 2, where the mitigated source currents for both cases have regained sinusoidal shape with THD values (as tabulated in Table 5) complying with the 5% harmonic limit. However, SAPF that applies the standard dq0 technique fails to comply with IEEE standard 519 in both cases, where the recorded THD values are beyond 5% and the mitigated source currents fail to recover the desired sinusoidal shape. Nevertheless, both techniques are able to remove excessive neutral currents caused by connection of single-phase loads.
In addition, as indicated in Table 5, both techniques have effectively minimized the large phase differences between the source current and voltage caused by connection of Loads 1 and 2. With minimum phase differences, almost unity power factor of 0.999 can be achieved when the proposed STF-dq0 technique is applied. However, due to higher distortion level of the mitigated source current, the standard dq0 technique can only provide a power factor up to 0.998 even though the phase differences have been minimized.       Furthermore, assessment on behaviour of dc-link voltage is also conducted to justify that the SAPF is working correctly under Scenario D, while applying the proposed STF-dq0 technique. Figures 22 and 24 provide the related results obtained for Loads 1 and 2, respectively. From the results obtained, all dc-link voltages of the SAPF are revealed to have effectively been regulated and maintained at the desired level, i.e., overall dc-link voltage V dc at 880 V and voltages across the two split dc-link capacitors (V dc1 and V dc2 ) at 440 V (half of overall dc-link voltage). Hence, once again, it is certain that the SAPF can work appropriately under non-sinusoidal-unbalanced source voltage scenario while applying the proposed STF-dq0 technique.
Overall, based on all the findings obtained in Scenarios A to D, design concept and functionality of the proposed STF-dq0 technique can be confirmed to be correct. By applying the proposed STF-dq0 technique, the SAPF is revealed to perform effectively in dealing with both unbalanced nonlinear loads and all the scenarios of source voltages which have been considered in this work. The highly distorted source currents have regained the desired sinusoidal shape with low THD values ranging from 0.92% to 2.97%, complying with IEEE standard 519. Next, excessive neutral currents have been reduced to a level that the mitigated source currents are balanced. In addition, large phase differences have been reduced to the range of 0.00-0.80 • , thereby achieving power factor of 0.999 which is almost unity. Furthermore, all dc-link capacitor voltages have been regulated as desired and are balanced, thus ensuring that the SAPF is able to mitigate harmonics appropriately. More importantly, the proposed STF-dq0 technique outperforms and is more reliable than the standard dq0 technique when dealing with distorted and unbalanced source voltages.

Conclusions
In this paper, a control technique that generates reference current to manage operation of a three-phase four-wire SAPF has successfully been demonstrated. The proposed technique is named as the STF-dq0 technique, as it is developed by integrating together the strengths of STF and working concept of the dq0 principle, without relying on any PLL element. Comprehensive tests and analyses involving two types of unbalanced nonlinear rectifier loads and four distinct scenarios of source voltages are conducted to evaluate performance of the proposed STF-dq0 technique in comparison to the standard dq0 technique. Based on the exhaustive simulation results presented, the proposed technique is revealed to perform effectively regardless of specifications of nonlinear loads and scenarios of source voltages. More importantly, the proposed STF-dq0 technique is demonstrated to be superior and more reliable than the standard dq0 technique especially when dealing with distorted and unbalanced source voltages. Low THD values complying with IEEE standard 519, synchronized operation of SAPF, minimized neutral current and power factor reaching almost unity, are the benefits granted by the proposed technique when it is applied in three-phase four-wire system.