An Improved Delayed Signal Cancelation for Three-Phase Grid Synchronization with DC Offset Immunity

Abstract

The presence of the DC components in the grid voltage adversely affects the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information. Several approaches were proposed to address the DC offset problem by incorporating an additional filtering stage to the synchronous reference frame phase-locked loop (SRF-PLL). Removing the DC offset using the modified delayed signal cancelation (MDSC) operator in the inner loop of the SRF-PLL shows a good DC offset elimination with a fast-dynamic response. However, neither a straightforward selection procedure for the MDSC parameters nor a general estimation technique for the grid information is provided. Hence, a generalization for the MDSC is proposed in this paper based on general mathematical expressions to cancel out the DC offset, while meanwhile estimating the grid parameters precisely and rapidly against any delay factor selection. Finally, comprehensive simulation and experimental results compared with other related PLLs are presented to demonstrate the effectiveness of the proposed work.

1. Introduction

The phase-locked loop (PLL) is a negative-feedback-closed-loop control system commonly used in grid synchronization and control of grid-tied power converters [1,2,3,4]. The wide usage of power converters is due to their ability to convert electrical power from one form to another, making it possible to use power from different sources and to power different devices with different requirements. PLLs are also used in sensorless control of electrical machines [5], power quality indices [6,7], and islanding detection [8].

Among all types of PLL, the most common type used in the three-phase applications is the conventional synchronous reference frame (SRF)-PLL with a proportional-integral (PI) controller as a loop filter due to its structural simplicity and ease of implementation [9,10]. In the conventional SRF-PLL depicted in Figure 1, the PI controller can only mitigate the phase error and estimate the grid parameters precisely under ideal conditions. However, it cannot completely block or attenuate the harmonics, the DC offset, and any possible grid noise.

The DC offset in the grid voltage may be generated because of grid faults [11], geomagnetic phenomena [12], the A/D conversion process [13], and the DC injection by distributed generation systems, specifically PV inverters [14], to name a few. In addition, the power quality problems related to the presence of the DC components in the grid voltage adversely affect the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information [15].

The bandwidth (BW) of the PLL must be restricted to a low value to attenuate the DC offset using the conventional SRF-PLL. This results in poor dynamic performance and may not be acceptable in most applications. For example, the requirement for settling time in common grid codes is less than two grids’ fundamental cycles [16,17].

Recently, several approaches have been proposed to incorporate an additional filtering stage, either in the inner or outer loop of the conventional SRF, to deal with the DC offset problem [17,18,19,20,21]. Besides the DC offset rejection, estimating the amplitude and the phase of the fundamental grid voltage components and compensating for the phase lead caused by those additional filters puts another challenge to be solved to synchronize with the grid perfectly.

In [18], the moving average filter (MAF) is used in the inner loop of the PLL, showing an excellent rejection capability against the harmonics. However, its dynamic response is slow, especially under the frequency drifts, which appear as ripples in the estimated frequency. Moreover, under large frequency drifts, the MAF performance becomes worse. Therefore, the estimation of the grid information is degraded.

In [19], a notch filter phase-locked loop (NF-PLL) is proposed for grid synchronization with DC offset rejection technique by replacing the in-loop MAF with a notch filter. This enables the PLL to block the DC offset contaminated with the grid voltages effectively at the cost of slowing down the response. Moreover, the NF-PLL performance becomes worse under large frequency drift, which can be solved by narrowing the bandwidth of the NF; however, this adversely affects the PLL’s performance.

Delayed signal cancellation (DSC) PLL that provides good DC offset filtering capability has been proposed in [20]. The dqDSC is implemented in the PLL inner loop and has only one decisive parameter: the delay factor. Selecting a specific delay factor to eliminate the DC offset, the dqDSC shows good rejection capability, but its dynamic response is slow. The slow dynamic response caused by the DSC operator can be improved by adding a phase lead compensator in the PLL’s inner loop, which may decrease the DC rejection capability of the PLL, specifically under grid frequency drift.

In contrast, the αβDSC-PLL, implemented in the PLL outer loop, shows a good DC offset rejection capability with a faster transient response than the dqDSC-PLL under the same delayed factor. However, the phase compensation method needed under frequency deviation complicates the PLL design [21].

In [22], a specific design parameter is suggested using modified delayed signal cancelation (MDSC) in the inner loop of the SRF-PLL with a specific delay factor. The MDSC based PLL shows good DC offset elimination with rapid response. The lead-in phase caused by the MDSC operator is compensated by computing the lead-in phase and then adding the same angle directly into the PLL output, which is not general for any delay factor selection. Moreover, it does not have a general voltage amplitude estimation technique under the arbitrary delay factor.

Therefore, this paper proposes a generalization to the MDSC-PLL. The proposed PLL is based on general mathematical relationships between the delay factor and the design parameter, eliminating the DC offset and extracting the grid voltage’s fundamental frequency positive sequence (FFPS) under any delay factor. Moreover, the proposed model has simple and general estimation techniques to estimate the grid voltage amplitude, frequency, and phase.

This paper is arranged as follows: Section 2 presents an overview of DSC and MDSC operators. Then, the proposed PLL with amplitude and phase compensation formulas is derived in Section 3. In Section 4, the mathematical model is derived, and the controller gains are designed. In Section 5, with two selections of the delay factor, the justification for the proposed model and its mathematical model against both compensation formulas are implemented mathematically and throughout the numerical simulation. In Section 6, experimental results compared with other related PLLs are presented to demonstrate the effectiveness of the proposed PLL. Finally, Section 7 concludes the paper’s findings.

2. The Modified Delayed Signal Cancellation Operator

The DC offset in the input of the synchronizing unit causes an oscillation in the estimated grid information. The DC component in the abc-reference frame has a zero-harmonic order; hence, it becomes a negative one in the dq-reference frame after using Park’s transformation. Therefore, the DC component appears as a sinusoidal wave in the dq-reference frame and possesses half-wave symmetry. A summation with the delayed versions in the dq-reference frame can cancel out the DC component, which illustrates the basic topology of the DSC operator. The DSC operator is commonly implemented in the inner loop of the PLL operating in the dq-reference frame. The general expression for the DSC operator in the s-domain can be described as:

$$\mathrm{D}\mathrm{S}\mathrm{C}(s)=\frac{1+e^{-\frac{T}{n}s}}{2},$$

(1)

where T is the fundamental voltage grid period, and n is an integer that specifies the delay factor.

In Equation (1), the DSC operator has only one design parameter, the n. This operator is used widely in many approaches since it has excellent rejection capabilities against the DC offset and harmonics, which depends on its selection; each n has a specific ability to deal with certain harmonics. However, it suffers from slow dynamic performance when used to reject the DC component. Thus, the DSC operator is modified into the MDSC operator, giving the DSC flexibility and improving its dynamic response [22]. The MDSC operator can be expressed in the s-domain as:

$$\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}(s)=\frac{1+e^{j\frac{2\pi }{n_s}}{e}^{-\frac{T}{n}s}}{2},$$

(2)

where n_s is a design parameter used to shift the frequency characteristics of the DSC, Figure 2 depicts the time-domain implementation of the MDSC operator. In contrast, the schematic diagram of the MDSC-PLL is illustrated in Figure 3 [22].

3. The Proposed Phase-Locked Loop

The MDSC-PLL features excellent dynamic performance and DC offset rejection with a shorter delay. However, it does not have an explicit general algorithm for selecting the MDSC operator’s parameters against any delay operator. Moreover, the utilized compensation criteria are based on calculating the phase lead under a specific delayed factor. Hence, the compensation in [22] is not general and hard to be adopted under an arbitrary delay factor. Moreover, no general voltage amplitude estimation is discussed in [22].

Therefore, to achieve perfect synchronization with an arbitrary delay factor, the MDSC-PLL is generalized in this paper. The proposed PLL is based on general mathematical relationships between the delay factor and the design parameter. The proposed PLL can eliminate the DC offset and extract the FFPS of the grid voltage precisely and rapidly while estimating the amplitude of the grid voltage and compensating the lead-in phase under any election of the delay factor.

To derive a general expression of the proposed PLL in the dq-reference frame under any selection of n, consider the grid voltage that contains some DC offset components:

$$\left[\begin{array}{c}{v}_a\\ v_b\\ v_c\end{array}\right]=V_m\left[\begin{array}{c}\sin \left(\theta \right)\\ \sin \left(\theta -\frac{2\pi }{3}\right)\\ \sin \left(\theta +\frac{2\pi }{3}\right)\end{array}\right]+\left[\begin{array}{c}{v}_a^{dc}\\ v_b^{dc}\\ v_c^{dc}\end{array}\right],$$

(3)

where: $\theta ={\omega }_{g}t+\mathrm{\varnothing }$, ${\omega }_g={\omega }_n+{\Delta \omega }_g$ and ${\omega }_n=2\pi f_n$. The subscript ‘$abc$’ defines the reference frame of the grid, which is called the natural reference frame, $V_m$ is the grid voltage amplitude of the FFPS component, $\theta$ is the grid phase angle of the FFPS component, ${\omega }_g$ is the grid angular frequency, ${\omega }_n$ is the nominal grid fundamental angular frequency, $f_n$ is the nominal grid fundamental frequency, and $\mathrm{\varnothing }$ is the grid voltage initial phase angle, $v_a^{dc}$, $v_b^{dc}$, and $v_c^{dc}$ are the DC components in the grid voltages.

Applying Park’s transformation to the grid voltage in Equation (3) yields:

$$\left[\begin{array}{c}{v}_d\\ v_q\end{array}\right]=\frac{2}{3}\left[\begin{array}{ccc}\sin \left(\widehat{\theta }\right)& \sin \left(\widehat{\theta }-\frac{2\pi }{3}\right)& \sin \left(\widehat{\theta }+\frac{2\pi }{3}\right)\\ \cos \left(\widehat{\theta }\right)& \cos \left(\widehat{\theta }-\frac{2\pi }{3}\right)& \cos \left(\widehat{\theta }+\frac{2\pi }{3}\right)\end{array}\right]\left[\begin{array}{c}{v}_a\\ v_b\\ v_c\end{array}\right],$$

(4)

where: $\widehat{\theta }={\widehat{\omega }}_{g}t+\mathrm{\varnothing }$ and ${\widehat{\omega }}_g={\omega }_n+\Delta {\widehat{\omega }}_g$, $\widehat{\theta }$ is the estimated phase angle, and ${\widehat{\omega }}_g$ is the estimated angular frequency, and $\Delta {\widehat{\omega }}_g$ is the estimated angular frequency variation.

After simplifying the terms in Equation (4) and using the trigonometric identities, the $d$ and $q$ components can be expressed generally in terms of harmonic order as follows:

$$v_{dq}^h=V_m\left(\cos \left(h_{dq}\omega t+\mathrm{\varnothing }\right)+j\sin \left(h_{dq}\omega t+\mathrm{\varnothing }\right)\right),$$

(5)

$$h_{dq}=h_{abc}-1,$$

(6)

Equation (6) represents the relationship between the harmonic order in the abc-reference frame $\left(h_{abc}\right)$ and its corresponding harmonic order in the dq-reference frame $\left(h_{dq}\right)$. According to this relationship, it is important to mention that the DC offset in the abc-reference frame becomes of order (−1) in the dq-reference frame. In contrast, the FFPS in the abc-reference frame becomes a DC quantity in the dq-reference frame. Therefore, the functionality of the proposed MDSC operator is to extract the FFPS and block the DC components in $abc$-reference frame while it is operating in the dq-reference frame at any delay factor.

From Figure 2, the output of the MDSC operator can be expressed as follows:

$${\stackrel{-}{v}}_q(t)=\frac{1}{2}\left(v_q\left(t\right)+v_q\left(t-\frac{T}{n}\right)\cos \left(\frac{2\pi }{n_s}\right)+v_d\left(t-\frac{T}{n}\right)\sin \left(\frac{2\pi }{n_s}\right)\right),$$

(7)

$${\stackrel{-}{v}}_d(t)=\frac{1}{2}\left(v_d\left(t\right)+v_d\left(t-\frac{T}{n}\right)\cos \left(\frac{2\pi }{n_s}\right)-v_q\left(t-\frac{T}{n}\right)\sin \left(\frac{2\pi }{n_s}\right)\right),$$

(8)

Taking into account the relationship between $d$-component and $q$-component as

$$v_q=j{v}_d,$$

(9)

Using Equations (7)–(9), the Laplace transform of the MDSC operator can be described as:

$$\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}(s)=\left[\frac{1+e^{-\frac{T}{n}s}{e}^{j\frac{2\pi }{n_s}}}{2}\right],$$

(10)

Substituting $s=jh\omega$ in Equation (10) yields the following frequency response of the MDSC:

$$\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}(s)=\left[\frac{1+e^{-j\frac{T}{n}h\omega }{e}^{j\frac{2\pi }{n_s}}}{2}\right],$$

(11)

Equation (11) can be rewritten in the following form:

$$\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}(jh\omega )=\left|\cos \left(\frac{\frac{2\pi }{n_s}-\frac{T}{n}h\omega }{2}\right)\right|\angle \frac{\frac{2\pi }{n_s}-\frac{T}{n}h\omega }{2},$$

(12)

From Equation (12), the cosine term is the gain of the MDSC operator, which corresponds to the $h^{th}$ harmonic component, while the angle term represents the phase delay of the MDSC operator of the same harmonic component. Generally, the MDSC operator’s gain that corresponded to that harmonic order must equal zero to block any specific harmonic. Since the gain is a cosine function, it can block multiple harmonics simultaneously, which is considered one of the main advantages of the MDSC operation. Therefore, equating the MDSC operator gain with zero leads to a general mathematical relationship between the delay factor $n$, $n_s$, and the harmonic order $h$ as follows:

$$\left|\cos \left(\frac{\frac{2\pi }{n_s}-\frac{T}{n}h\omega }{2}\right)\right|=0,$$

(13)

which equals zero if and only if:

$$\frac{\frac{2\pi }{n_s}-\frac{T}{n}h\omega }{2}=\pi \left(2k\pm \frac{1}{2}\right),$$

(14)

The frequency characteristics of the MDSC are the same as that in the DSC operator but shifted by ($n$/$n_{s}T$) with a BW of ($n/T)$. The notch frequencies are shifted along the frequency axis according to the required harmonics to be eliminated, which corresponds to a general formula between the operator’s parameters. The general formula describes the relationship between $n$, any harmonic order $h$, and $n_s$ derived from Equation (14) can be written as:

$$n_s=\frac{n}{\left(2k\pm \frac{1}{2}\right)n+h},$$

(15)

since $k$ has many choices, more than multiple values of $n$ and $n_s$ can satisfy Equation (15) for a particular value of $h$. Similarly, for many choices of $k$, multiple values of $h$ can be selected for a given value of $n$ and $n_s$. This means different MDSC operators can eliminate the same harmonic, while the same MDSC operator can attenuate a group of harmonics. However, in order to select the values for $n$ and $n_s$ corresponding to minimum phase delay, the design parameter $n_s$ is inversely proportional to the phase delay caused by the MDSC operator. Therefore, the maximum value of $ns$, which occurs when $k=0$, minimum phase delay will be achieved. Thus, substituting $k=0$ in Equation (15) yields:

$$n_s=\frac{n}{\pm \frac{1}{2}n+h},$$

(16)

From the harmonic rejection capabilities perspective, this paper’s primary concern is to cancel out the DC component injected in the natural reference frame, which turns out to be of order $h=-1$ in the dq-frame. This means that one of the notch frequencies must be shifted to (−50 Hz) along the frequency axis of the MDSC operator of BW greater than (50 Hz). Therefore, substituting this harmonic order in Equation (16) leads to:

$$n_s=\frac{n}{\pm \frac{1}{2}n-1},$$

(17)

It is important to illustrate the relationship between the delay factor and its corresponding proper design parameter value described in Equation (17). This relation affects the operator’s dynamic response and PLL performance. To achieve a rapid transient response for the proposed PLL against any step change in the input, the phase delay caused by the MDSC operator is inversely proportional to the design parameter $n_s$, but the design parameter $n_s$ is directly proportional to the delay factor $n.$ Therefore, by increasing the value of $n$, the value of $n_s$ will be increased accordingly, and hence the phase delay caused by the operator will be decreased, resulting in a fast transient response of the PLL.

Moreover, increasing the value of the delay factor will increase the BW, reducing the MDSC operator’s harmonic rejection capabilities of the MDSC operator. However, since the DC component is the target here, the effect of increasing the BW on the other harmonics will be ignored. Therefore, the only restriction on the BW of the operator is not to be 50 Hz. Equation (17) is used for selecting the value of $n_s$ against the amplitude and phase estimation technique.

The Amplitude and Phase Compensation

Extracting the fundamental frequency component is implemented at zero hertz in $dq$-reference frame, which can be calculated mathematically by substituting $h=0$ into Equation (11) as follows:

$$G_{\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}}\left(h=0\right)=\cos \left(\frac{\pi }{n_s}\right)e^{j\frac{\pi }{n_s}},$$

(18)

To calculate general compensation methods for the amplitude and the phase in terms of any delayed factor $n$, Equation (17) is substituted in Equation (18), which yields:

$$G_{\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}}=\left|\sin \left(\frac{\pi }{n}\right)\right|\angle \frac{\pi }{2}-\frac{\pi }{n},$$

(19)

The utilization of the MDSC operator will scale the amplitude by $\sin \left(\pi /n\right)$, which can be obtained from the extracted $d$-component of the MDSC operator since it has the amplitude information of the fundamental frequency component of the grid voltage. Thus, the amplitude of the extracted $d$-component must be compensated to estimate the actual amplitude of the grid voltage. The compensation technique can be implemented by dividing the extracted $d$-component of the MDSC operator with the compensation formula derived in the last equation, which can be re-defined as:

$$k_m=\sin \left(\frac{\pi }{n}\right),$$

(20)

where, $k_m$ is the compensation voltage gain of the proposed PLL. The amplitude estimation of the fundamental frequency component under any delay factor selection can be expressed as:

$$\widehat{V}=\frac{{\stackrel{-}{v}}_d}{k_m},$$

(21)

The estimated phase lead value caused by the MDSC operator under any selection of the delayed factor can be represented by:

$${\phi }_{\mathrm{l}\mathrm{e}\mathrm{a}\mathrm{d}}=\frac{\pi }{2}-\frac{\pi }{n},$$

(22)

So, in order to compensate for this phase lead, a phase lag will be directly added to the output of the voltage-controlled oscillator (VCO) of the proposed PLL, which can be described in terms of compensated phase ${\widehat{\theta }}_c$ as follows:

$$\phi =\frac{\pi }{n}-\frac{\pi }{2},$$

(23)

Equation (23) is the compensation formula for the phase error caused by the MDSC operator under any delay factor. Incorporating both derived formulas into the MDSC-PLL will configure the generalized compensated model depicted in Figure 4.

4. The Mathematical Model of the Proposed PLL

The proposed PLL’s mathematical model will be derived in this section to analyze the stability of the proposed PLL and derive a general design formula against the PI controller’s gains under any delay factor election. The mathematical derivation criteria in this paper follow the guideline of [23]. The extraction of the FFPS components in the dq-reference frame is utilized by applying Park’s transformation to the FFPS of the grid voltages as follows:

$$\left[\begin{array}{c}{v}_d\\ v_q\end{array}\right]=\frac{2V_m}{3}\left[\begin{array}{ccc}\sin \widehat{\theta }& \sin \left(\widehat{\theta }-\frac{2\pi }{3}\right)& \sin \left(\widehat{\theta }+\frac{2\pi }{3}\right)\\ \cos \widehat{\theta }& \cos \left(\widehat{\theta }-\frac{2\pi }{3}\right)& \cos \left(\widehat{\theta }+\frac{2\pi }{3}\right)\end{array}\right]\left[\begin{array}{c}\sin \widehat{\theta }\\ \sin \left(\widehat{\theta }-\frac{2\pi }{3}\right)\\ \sin \left(\widehat{\theta }+\frac{2\pi }{3}\right)\end{array}\right],$$

(24)

the FFPS of the grid voltage in the synchronous reference frame can be extracted using the trigonometric identities as follows:

$$v_d=V_m\cos \left(\theta -\widehat{\theta }\right),$$

(25)

$$v_q=V_m\sin \left(\theta -\widehat{\theta }\right),$$

(26)

The extracted fundamental components from the MDSC operator derived in Equations (25) and (26) are incorporated into the arctangent operation, which can be described as:

$${\tan }^{-1}\left(\frac{{\stackrel{-}{v}}_q\left(t\right)}{{\stackrel{-}{v}}_d\left(t\right)}\right)={\tan }^{-1}\left(\frac{v_q\left(t\right)+v_q\left(t-\frac{T}{n}\right)\cos \left(\frac{2\pi }{n_s}\right)+v_d\left(t-\frac{T}{n}\right)\sin \left(\frac{2\pi }{n_s}\right)}{v_d\left(t\right)+v_d\left(t-\frac{T}{n}\right)\cos \left(\frac{2\pi }{n_s}\right)-v_q\left(t-\frac{T}{n}\right)\sin \left(\frac{2\pi }{n_s}\right)}\right),$$

(27)

Substituting Equations (25) and (26) into Equation (27) leads to the following:

$${\tan }^{-1}\left(\frac{{\stackrel{-}{v}}_q\left(t\right)}{{\stackrel{-}{v}}_d\left(t\right)}\right)={\tan }^{-1}\left(\frac{\sin \delta +\sin \gamma \cos \frac{2\pi }{n_s}+\cos \gamma \sin \frac{2\pi }{n_s}}{\cos \delta +\cos \gamma \cos \frac{2\pi }{n_s}-\sin \gamma \sin \frac{2\pi }{n_s}}\right),$$

(28)

where: $\delta =\theta -\widehat{\theta }$ and $\gamma =\theta \left(t-\frac{T}{n}\right)-\widehat{\theta }\left(t-\frac{T}{n}\right)$.

Using trigonometric identities, Equation (28) can be simplified into:

$${\tan }^{-1}\left(\frac{{\stackrel{-}{v}}_q\left(t\right)}{{\stackrel{-}{v}}_d\left(t\right)}\right)={\tan }^{-1}\left(\tan \left(\frac{\delta +\gamma +\frac{2\pi }{n_s}}{2}\right)\right),$$

(29)

which can be written as:

$${\tan }^{-1}\left(\frac{{\stackrel{-}{v}}_q\left(t\right)}{{\stackrel{-}{v}}_d\left(t\right)}\right)=\frac{\theta -\widehat{\theta }+\theta \left(t-\frac{T}{n}\right)-\widehat{\theta }\left(t-\frac{T}{n}\right)}{2}+\frac{\pi }{n_s},$$

(30)

The arctangent function in Equation (30) extracts the phase error directly without any linearization procedure. Taking the Laplace transform of Equation (30) leads to the following:

$$\mathrm{M}\mathrm{D}\mathrm{S}\mathrm{C}\left(s\right)=\frac{1}{2}\left[1+e^{-\frac{T}{n}s}\right]\left[\Delta \theta \left(s\right)-\Delta \widehat{\theta }\left(s\right)\right],$$

(31)

The last equation represents the mathematical formula for the proposed PLL since it is valid under any selection of the delay factor $n$, depicted in Figure 5. The term $\pi /n_s$, in Figure 5, represents the DC offset value in the output phase of the proposed PLL. It is equal to the estimated phase formula derived earlier in Equation (22), which justifies the proposed phase compensation model. Moreover, to derive a gain formula against the PI controller in terms of delay factor, it is tackled by taking the open-loop transfer function of the mathematical model of the proposed PLL as follows:

$$G_{ol}=\frac{\Delta \widehat{\theta }\left(s\right)}{\left[\Delta \theta \left(s\right)-\Delta \widehat{\theta }\left(s\right)\right]}=V_m\left(\frac{1+e^{-\frac{T}{n}s}}{2}\right)\frac{K_{P}s+K_i}{s^2},$$

(32)

the delay term in Equation (32) is approximated using Padé approximation to simplify the design process:

$$e^{-\frac{T}{n}s}\approx \frac{1-\frac{T}{2n}s}{1+\frac{T}{2n}s},$$

(33)

Substituting Equation (33) into the open-loop transfer function Equation (32) yields:

$$G_{ol}=V_m\left(\frac{1}{\frac{T}{2n}s+1}\right)\frac{K_{P}s+K_i}{s^2},$$

(34)

Applying the symmetrical optimum design method [24], the PI controller parameters are obtained as follows:

$$K_P=\frac{1}{c\left(\frac{T}{2n}\right)},$$

(35)

$$K_i=\frac{1}{\left(c^3\right)\left({\left(\frac{T}{2n}\right)}^2\right)},$$

(36)

where c is a design constant that determines the phase margin (PM) of PLL, the PM of the PLL has the following formula:

$$\mathrm{P}\mathrm{M}={\tan }^{-1}\left(\frac{c^2-1}{2c}\right),$$

(37)

Equations (35) and (36) represent the formulas for the PI gains of the proposed model that corresponds to any selection of the delay factor $n$, while Equation (37) corresponds to the desired phase margin of the system, which is taken here as in many approaches for fair comparison as $\mathrm{P}\mathrm{M}={45}^{°}$ results in $c=\sqrt{2}+1$.

5. Numerical Simulations

5.1. The Validation of the Proposed PLL

Two delay factor values are selected and tested without generality loss to justify the proposed PLL capability in DC offset rejection while estimating the grid information under an arbitrary delay factor.

5.1.1. Case 1

The n =12, under this delay factor selection, the corresponding optimal value of $n_s$ can be obtained by substituting the delayed factor of $n$ in Equation (17), which leads to $n_s=-12/7$.

On the other hand, to compensate for the phase delay resulting from this selection, substituting the selected delay factor in the phase estimation formula derived in Equation (22) as follows: ${\phi }_{\mathrm{l}\mathrm{e}\mathrm{a}\mathrm{d}}=\frac{\pi }{2}-\frac{\pi }{12}=\frac{5\pi }{12}$ , so, the compensated value can be calculated as: $\phi =-5\pi /12$ and $k_m=\sin \left(\frac{\pi }{12}\right)$ . The bode diagram of the MDSC against this case is plotted and depicted in Figure 6a. The BW of the operator, in this case, can be calculated using the relationship mentioned earlier, which results in (600 Hz) with a notch frequency located at (−50 Hz). The bode diagram shows that the magnitude of the MDSC operator with $n=12$ at 0 Hz is –11.7401 dB, which is equivalent to the same compensated value calculated mathematically. The estimated values against the phase and the BW are the same as the calculated values, which justifies the validation of the proposed model.

The general mathematical model derived earlier has been tested with the original model with a delay factor of $n=12$ for both models under a $\left(+{20}^{°}\right)$ phase jump in the grid voltage. Considering $c=1+\sqrt{2}$ corresponded to $\mathrm{P}\mathrm{M}={45}^{°}$. The PI gains, in this case, are calculated from Equations (35) and (36) results in $K_P=497$ and $K_i=102337.65$. The transient behavior of the phase error during the test for both models is depicted in Figure 6b. It can be observed that the mathematical model can estimate the dynamic behavior of the proposed PLL accurately.

5.1.2. Case 2

Under n = 16, $n_s=-16/9$ leads to: $k_v=\sin \left(\frac{\pi }{16}\right)$ and $\phi =-7\pi /16$. The Bode plot of the operator for this case is depicted in Figure 7a. It shows the same results obtained mathematically using the compensation formulas. Once again, the proposed model has been tested with its mathematical model with $n=16$ when the grid undergoes a $\left(+{20}^{°}\right)$ phase jump. The PI gains, in this case, are $K_P=662.74$ and $K_i=181933.$ The simulated transient behavior of the phase error is depicted in Figure 7b, which justifies the accuracy of the mathematical model.

5.2. Comparisons with Related Methods

To validate its performance and applicability, the proposed PLL is compared with comparisons with the dqDSC2-PLL and NF-PLL, shown in Figure 8. The PI controller gains of the dqDSC2-PLL and the NF-PLL are the same as in [21].

Table 1. The controller parameters.

Parameters	dqDSC-PLL	NF-PLL	Proposed-PLL
$\mathrm{Delay}\mathrm{factor}n$	2	-	8
$\mathrm{Proportional}\mathrm{gain}{k}_P$	82.84	92	331.37
$\mathrm{Integral}\mathrm{gain}{k}_i$	2842.7	3507.1	45483

summarizes the control parameters of the PLLs under all test cases.

5.2.1. Test 1

The grid voltage is contaminated with the DC offset $\left(v_{a,dc}=0.2\mathrm{p}\mathrm{u},v_{b,dc}=0.1\mathrm{p}\mathrm{u},v_{c,dc}=-0.2\mathrm{p}\mathrm{u}\right),$ meanwhile, the grid voltage undergoes a $\left(+{20}^{°}\right)$ phase jump. Figure 9 shows the simulation results for the phase error (Figure 9a) and the estimated frequency (Figure 9b) for all PLLs during this test. It can be observed that although all PLLs provide a good DC offset rejection capability under phase jump, the proposed PLL has the fastest transient response with a settling time of 12.18 ms. In contrast, the dqDSC2-PLL and NF-PLL have a settling time of 73.44 ms and 64 ms, respectively.

5.2.2. Test 2

The grid voltage is contaminated with the DC offset $\left(v_{adc}=0.2\mathrm{p}\mathrm{u},v_{b,dc}=0.1\mathrm{p}\mathrm{u},v_{c,dc}=-0.2\mathrm{p}\mathrm{u}\right)$, meanwhile, the grid voltage undergoes $\left(+5\right)$ Hz frequency step change. Figure 10 shows the simulation results for the phase error and the estimated frequency for all PLLs during this test, respectively. It can be observed that the NF-PLL cannot block the DC offset under this case, which causes an oscillation in the estimated frequency and the estimated phase angle. Simultaneously, the dqDSC2-PLL has a good DC offset rejection capability, but with a slow transient response of about 59.03 ms (2.96 grid cycles). On the other hand, the proposed -PLL shows an excellent rejection capability against the DC offset with precise and rapid frequency estimation, with a settling time of around 15.31 ms.

6. Experimental Validation

A three-phase inverter connected to a passive load through an LC filter is used to mimic a three-phase grid. Voltage sensors are used to sense the voltages and the compared PLLs are executed in parallel using a field programmable gate array (FPGA). For the proposed PLL, n is reduced to 4, which leads $K_P=165.68$ and $K_i=11371.$ The control parameters for the other PLLs are the same as in Table 1, and the hardware setup rating is listed in

Table 2. The controller parameters.

Parameters	Value
Rated Power	200 watt
Input DC voltage	64 V
Grid frequency	50 Hz
Rated phase current	4 A
Filter inductance	1.5 mH
Filter capacitance	2 μF
Switching frequency	10 kHz

, while Figure 11 shows its photos.

The results are captured using Rigol digital oscilloscope and are shown in Figure 12. Figure 12a shows the grid voltages under $+{25}^{°}$ while the DC offset is added at the same time to the phase voltages as $\left(v_{a,dc}=0.2\mathrm{p}\mathrm{u},v_{b,dc}=0.1\mathrm{p}\mathrm{u},v_{c,dc}=-0.2\mathrm{p}\mathrm{u}\right)$. Figure 12b shows the estimated phase error, while Figure 12c shows the estimated grid frequency. Figure 12d shows the grid voltage under $+6$ frequency jump with DC offset, while its phase error response is shown in Figure 12e, and the frequency response is shown in Figure 12f. The experimental results show that the proposed PLL is at least three times faster than the other PLLs.

7. Conclusions

In this paper, the MDSC-PLL operating in dq reference frame is generalized for rejecting the DC offset contaminated with the grid voltage under any delay factor selection. The extension is based on a general mathematical relationship between a delay factor and a design parameter. It was shown that with the increase in the delay factor value, the dynamic response of the proposed PLL would increase at the cost of increasing the bandwidth. On the other hand, the proposed PLL was armed with compensation methods to estimate grid voltage amplitude and phase accurately to complete the grid parameters’ estimation. The compensation methods were derived based on general formulas and tested with the original model under an arbitrary delay factor. The proposed PLL is simulated under abnormal grid conditions and a comparative analysis is done with comparisons with other PLLs. Based on the results, the proposed PLL achieves grid synchronization in less than one grid cycle, making it at least two times faster than the other related PLLs. The results show that the proposed PLL has an excellent rejection capability against DC offset and accurate estimation for the grid parameters under any delay factor selection with a fast settling time.