Design and Verification of a Charge Pump in Local Oscillator for 5G Applications

A charge pump (CP) that has low current mismatch to reduce the locking time of the PhaseLocked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design.


Introduction
A phase-locked loop (PLL)-based frequency synthesizer is a vital component in communication systems [1,2]. To support the high data-rate transmission in 5G systems, the stringent requirements of being both fast settling with low power consumption must be satisfied. Owing to its wide locking range and low phase offset, the charge pump (CP) PLL is widely used in practice [3][4][5]. However, the current mismatch in charge pump eventually leads to static phase offsets and reference spurs, which is a main issue in PLL design. Many approaches have been proposed to reduce the mismatch between the injected current and removed current. The work reported in [6] used the active feedback circuit based operational power amplifier (OPA) to increase output resistance and reduce current mismatch. However, with an extra OPA circuit, the power consumption would be increased. Report [7] proposed a method in which the control words are used to calibrate the current mismatch. The complexity of the whole CP was increased vastly. These methods greatly increase the complexity of charge pumping. A self-tracking CP was proposed in [8], but the technique was limited by PVT (Process Voltage Temperature). To achieve the possible largest frequency range, ideally, the CP output voltage should be in the range of 0 to the supply voltage to maximize the use of the oscillator tuning range. Being fast settling with no data loss during frequency locking is required for the high data-rate transmission in 5G applications. The fast-locking capability is particularly critical for systems requiring a frequency-hopping operation. The main idea of reducing the settling time is to widen (narrow) the loop bandwidth in locking (locked state). Several strategies are employed to adjust bandwidth-dependent parameters/components, such as the CP current/low pass filter (LPF). Reference [9] straightly used two sets of CP and switches to adjust the current and resistance values of LPF. Reference [10] combined the programmable divider with sets of CP to compensate for phase error. Though the above methods could improve the locking speed, more transistors are needed, and the design complexity is increased. 2 of 10 In this work, a phase-locked loop charge pump, which has low current mismatch and reduced locking time, is proposed. The current mismatch is reduced to less than 1% for a voltage headroom from 0.4 V to 4.6 V. A phase error compensation module is also employed in the design. The locking time is reduced by 18.4% with low complexity and circuit cost.

Design of Low Current Mismatch Charge Pump with Broad Voltage Headroom
To support high data-rate 5G application, the settling time is always expected to be reduced as much as possible. Modulating the bandwidth to accelerate the locking process is the main strategy. As shown in Figure 1a, the bandwidth is hard to be controlled when the parameters and structures of CP, voltage-controlled oscillator (VCO), LPF and divider are fixed. As the CP current is positively related to the bandwidth, an adjustable charge pump is proposed to reduce the settling time as shown in Figure 1b. The proposed CP should be able to maintain a low current mismatch while having a broad voltage headroom. It could also be modulated by the phase error compensation module to reduce the settling time.
Electronics 2021, 10, x FOR PEER REVIEW 2 of 10 for phase error. Though the above methods could improve the locking speed, more transistors are needed, and the design complexity is increased. In this work, a phase-locked loop charge pump, which has low current mismatch and reduced locking time, is proposed. The current mismatch is reduced to less than 1% for a voltage headroom from 0.4 V to 4.6 V. A phase error compensation module is also employed in the design. The locking time is reduced by 18.4% with low complexity and circuit cost.

Design of Low Current Mismatch Charge Pump with Broad Voltage Headroom
To support high data-rate 5G application, the settling time is always expected to be reduced as much as possible. Modulating the bandwidth to accelerate the locking process is the main strategy. As shown in Figure 1a, the bandwidth is hard to be controlled when the parameters and structures of CP, voltage-controlled oscillator (VCO), LPF and divider are fixed. As the CP current is positively related to the bandwidth, an adjustable charge pump is proposed to reduce the settling time as shown in Figure 1b. The proposed CP should be able to maintain a low current mismatch while having a broad voltage headroom. It could also be modulated by the phase error compensation module to reduce the settling time. Compared with the traditional OPA-based CP in Figure 2a, the current sink and current source have been eliminated in the proposed design Figure 2b. In the locking mode, static power consumption is saved. Moreover, in the proposed design, with the help of OPA, charge sharing issues are no longer significant. The charging signal "UP" and discharging signal "DN", which are the output signals of the phase frequency detector, are at high and low voltage levels, respectively. When the loop is locked, Switches S1, S2 and S3 are switched off while S4 is switched on. For the virtual-short and Compared with the traditional OPA-based CP in Figure 2a, the current sink and current source have been eliminated in the proposed design Figure 2b. In the locking mode, static power consumption is saved. Moreover, in the proposed design, with the help of OPA, charge sharing issues are no longer significant. The charging signal "UP" and discharging signal "DN", which are the output signals of the phase frequency detector, are at high and low voltage levels, respectively. When the loop is locked, Switches S1, S2 and S3 are switched off while S4 is switched on. For the virtual-short and virtual-off features, there are no current flows through R1. Therefore, the output voltage (V OUT ) of CP can be expressed as the following: When the voltage of VC is set to half of VCC, the charging and discharging currents have the same magnitude.
Compared with the traditional OPA-based CP shown in Figure 2a, the primary power consumption is reduced and dependent on the OPA in the locking mode. The control voltage range is extended without considering the current mismatch caused by the PMOS and NMOS.   The output voltage of CP is maintained and influenced only by the leakage current as shown in Figure 2c. When the phase and frequency of signal "Fdiv" are faster and higher than that of signal "Fref", respectively, both signals UP and DN are set to the low level. Then, S3 and S4 are switched off; S1 and S2 are switched on as shown in Figure 2d with a black line. The discharging current and time-dependent output voltage can be obtained as the following: On the other hand, as shown in Figure 2d with a red line, the charging current and time-dependent output voltage can be obtained as follows: When the voltage of VC is set to half of VCC, the charging and discharging currents have the same magnitude.
Compared with the traditional OPA-based CP shown in Figure 2a, the primary power consumption is reduced and dependent on the OPA in the locking mode. The control voltage range is extended without considering the current mismatch caused by the PMOS and NMOS.

Design of Simplified Charge Pump for Fast Locking PLL
As discussed above, the primary approach for reducing the locking time relies on adjusting the bandwidth during the locking process and at the locked state. However, as shown in Figure 1a, when the structures of LPF, VCO gain and CP current are fixed, it is hard to modulate the bandwidth. The LPF has passive devices which are hard to switch and that occupy more area. The VCO design is independent of the bandwidth. A current control module is needed for the design as shown in Figure 1. When the structure and parameters of the LPF are fixed, the bandwidth of the PLL mainly depends on the current of CP. According to Equations (2) and (4), the bandwidth can be varied with the DC voltage, VC. Then, TDC and common-mode voltage selection modules are added to reduce the settling time.
TDC (Time to Digital Converter) is used to capture the phase information in practical design [10][11][12][13]. As shown in Figure 3, DFF (D flip-flop) is used as the delay cell, which has delayed time T to quantize the phase error.

Design of Simplified Charge Pump for Fast Locking PLL
As discussed above, the primary approach for reducing the locking time relies on adjusting the bandwidth during the locking process and at the locked state. However, as shown in Figure 1a, when the structures of LPF, VCO gain and CP current are fixed, it is hard to modulate the bandwidth. The LPF has passive devices which are hard to switch and that occupy more area. The VCO design is independent of the bandwidth. A current control module is needed for the design as shown in Figure 1. When the structure and parameters of the LPF are fixed, the bandwidth of the PLL mainly depends on the current of CP. According to Equations (2) and (4), the bandwidth can be varied with the DC voltage, VC. Then, TDC and common-mode voltage selection modules are added to reduce the settling time.
TDC (Time to Digital Converter) is used to capture the phase information in practical design [10][11][12][13]. As shown in Figure 3, DFF (D flip-flop) is used as the delay cell, which has delayed time T to quantize the phase error. The positions of the rising edge and falling edge indicate the size of the phase error and polarity, as shown in Figure 4. The binary string '001' or '011' indicates that signal "Fdiv" is faster than signal "Fref". On the other hand, the binary string '100' or '110' indicates that signal "Fref" is faster than signal "Fdiv". The rest of the binary strings are not assigned to contribute to the whole loop. The binary strings are decoded as different DC voltages, which are assigned to common-mode voltage VC as shown in Figure 4.  The decoded common-mode voltages are used to adjust the bandwidth of the loop by changing the current of the CP as shown in Figure 3. When the phase error between "Fref" and "Fdiv" is less than 2T, the loop enters the fast-locking process. When "Fdiv" is faster than "Fref" and the phase error falls in the range of (T, 2T), the common-mode voltage VC is assigned with 0.3 VDD. The discharging current can be obtained as follows:  The positions of the rising edge and falling edge indicate the size of the phase error and polarity, as shown in Figure 4. The binary string '001' or '011' indicates that signal "Fdiv" is faster than signal "Fref". On the other hand, the binary string '100' or '110' indicates that signal "Fref" is faster than signal "Fdiv". The rest of the binary strings are not assigned to contribute to the whole loop. The binary strings are decoded as different DC voltages, which are assigned to common-mode voltage VC as shown in Figure 4.
As discussed above, the primary approach for reducing the locking time relies on adjusting the bandwidth during the locking process and at the locked state. However, as shown in Figure 1a, when the structures of LPF, VCO gain and CP current are fixed, it is hard to modulate the bandwidth. The LPF has passive devices which are hard to switch and that occupy more area. The VCO design is independent of the bandwidth. A current control module is needed for the design as shown in Figure 1. When the structure and parameters of the LPF are fixed, the bandwidth of the PLL mainly depends on the current of CP. According to Equations (2) and (4), the bandwidth can be varied with the DC voltage, VC. Then, TDC and common-mode voltage selection modules are added to reduce the settling time.
TDC (Time to Digital Converter) is used to capture the phase information in practical design [10][11][12][13]. As shown in Figure 3, DFF (D flip-flop) is used as the delay cell, which has delayed time T to quantize the phase error. The positions of the rising edge and falling edge indicate the size of the phase error and polarity, as shown in Figure 4. The binary string '001' or '011' indicates that signal "Fdiv" is faster than signal "Fref". On the other hand, the binary string '100' or '110' indicates that signal "Fref" is faster than signal "Fdiv". The rest of the binary strings are not assigned to contribute to the whole loop. The binary strings are decoded as different DC voltages, which are assigned to common-mode voltage VC as shown in Figure 4.  The decoded common-mode voltages are used to adjust the bandwidth of the loop by changing the current of the CP as shown in Figure 3. When the phase error between "Fref" and "Fdiv" is less than 2T, the loop enters the fast-locking process. When "Fdiv" is faster than "Fref" and the phase error falls in the range of (T, 2T), the common-mode voltage VC is assigned with 0.3 VDD. The discharging current can be obtained as follows:  The decoded common-mode voltages are used to adjust the bandwidth of the loop by changing the current of the CP as shown in Figure 3. When the phase error between "Fref" and "Fdiv" is less than 2T, the loop enters the fast-locking process. When "Fdiv" is faster than "Fref" and the phase error falls in the range of (T, 2T), the common-mode voltage VC is assigned with 0.3 VDD. The discharging current can be obtained as follows: Electronics 2021, 10, 1009

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The bandwidth is widened by the enlarged discharging current I DN and the settling time can be reduced. By varying the voltage of VC, the current of CP is increased or decreased to accelerate the locking process.
When the number of delay cells in TDC increases, the resolution of TDC can be improved, but a larger power consumption and chip area are required. In the present design, only three delay cells are utilized to demonstrate the theory of reducing locking time. If the delay time is set to small, TDC works only at the part of the near-locking process. If the delay time is set to a large value, the TDC works only at the beginning of the near-locking process. Then, there is a trade-off between the power consumption, the unit delay time of TDC, and the number of delay cells. All of these parameters can be adjusted according to the applications. The delay time is set to 7 ns in the present design when the period time is 100 ns.

Simulation and Experimental Results
Compared with the traditional CP structure, there is no current mismatch between the injected current and removed current in the locked phase in the proposed design. Only the leakage current affects the stability of the control voltage of the VCO. When the common voltage of OPA is varied with the phase error, the variation of the leakage current is as shown in Figure 5a. Though the signal VC is set to the range of (1.5 V, 3.5 V) in this design, the leakage current is acceptable in a broad output voltage headroom of (0.4 V, 4.6 V). The leakage current is reduced to less than 400 nA in range, but rises dramatically when VC is out of range.
The bandwidth is widened by the enlarged discharging current IDN and the settlin time can be reduced. By varying the voltage of VC, the current of CP is increased o decreased to accelerate the locking process.
When the number of delay cells in TDC increases, the resolution of TDC can b improved, but a larger power consumption and chip area are required. In the presen design, only three delay cells are utilized to demonstrate the theory of reducing lockin time. If the delay time is set to small, TDC works only at the part of the near-lockin process. If the delay time is set to a large value, the TDC works only at the beginning o the near-locking process. Then, there is a trade-off between the power consumption, th unit delay time of TDC, and the number of delay cells. All of these parameters can b adjusted according to the applications. The delay time is set to 7 ns in the present desig when the period time is 100 ns.

Simulation and Experimental Results
Compared with the traditional CP structure, there is no current mismatch between the injected current and removed current in the locked phase in the proposed design. Onl the leakage current affects the stability of the control voltage of the VCO. When th common voltage of OPA is varied with the phase error, the variation of the leakage curren is as shown in Figure 5a. Though the signal VC is set to the range of (1.5 V, 3.5 V) in thi design, the leakage current is acceptable in a broad output voltage headroom of (0.4 V, 4. V). The leakage current is reduced to less than 400 nA in range, but rises dramaticall when VC is out of range. As shown in Figure 6, the current mismatch is below 1% (500 nA) for a broad output voltage headroom of 84% of the supply voltage. As shown in Figure 7, the distribution of the leakage current is little affected by temperature.  As shown in Figure 6, the current mismatch is below 1% (500 nA) for a broad output voltage headroom of 84% of the supply voltage. As shown in Figure 7, the distribution of the leakage current is little affected by temperature. As shown in Figure 6, the current mismatch is below 1% (500 nA) for a broad output voltage headroom of 84% of the supply voltage. As shown in Figure 7, the distribution of the leakage current is little affected by temperature.  The leakage current and output voltage range are the major factors in the CP design. The output voltage range always varies from 66.6% to 83.3% (Table 1). An 84% output voltage range was achieved in this design. When the source and sink currents are eliminated, the output voltage range is enlarged. Then, the leakage current in the source and sink currents are also eliminated. Compared with other works, the leakage current in this work is below 1%, which is quite acceptable. The whole area of the PLL core is 0.55 mm × 0.6 mm, as shown in Figure 8.  The leakage current and output voltage range are the major factors in the CP design. The output voltage range always varies from 66.6% to 83.3% (Table 1). An 84% output voltage range was achieved in this design. When the source and sink currents are eliminated, the output voltage range is enlarged. Then, the leakage current in the source and sink currents are also eliminated. Compared with other works, the leakage current in this work is below 1%, which is quite acceptable. The whole area of the PLL core is 0.55 mm × 0.6 mm, as shown in Figure 8.
Inspired by the phase error compensation technique, a 3-bit TDC is constructed. It switches the common voltage VC to accelerate the locking process, as shown in Figure 9a. According to Figure 9b, the magnitude of VC is assigned by the decoded binary string 'Q0Q1Q2 . The control voltage of the VCO is calibrated by the common mode voltage VC to limit the phase error of the PFD to less than T. During the fast-locking mode, the phase error is monitored and reduced through compensation.  Inspired by the phase error compensation technique, a 3-bit TDC is constructed. It switches the common voltage VC to accelerate the locking process, as shown in Figure 9a. According to Figure 9b, the magnitude of VC is assigned by the decoded binary string 'Q0Q1Q2′. The control voltage of the VCO is calibrated by the common mode voltage VC to limit the phase error of the PFD to less than T. During the fast-locking mode, the phase error is monitored and reduced through compensation.  Inspired by the phase error compensation technique, a 3-bit TDC is constructed. It switches the common voltage VC to accelerate the locking process, as shown in Figure 9a. According to Figure 9b, the magnitude of VC is assigned by the decoded binary string 'Q0Q1Q2′. The control voltage of the VCO is calibrated by the common mode voltage VC to limit the phase error of the PFD to less than T. During the fast-locking mode, the phase error is monitored and reduced through compensation.   Figure 10 were obtained from the schematic simulations. Compared with the traditional CP without phase error compensation, the optimized CP of the present design reduces the phase error of the PFD, leading to a decrease in the settling time from 89.6 μs to 73.1 μs. In the present design, only a 3-bit TDC was used to quantize and encode the phase error. With an increase in the bit number of the TDC, the delay time T decreases, and the locking capability can be further improved.

Conclusions
In this work, a PLL charge pump with a low current mismatch for reducing locking time is proposed. The current mismatch caused by leakage current is below 1% for a broad output voltage headroom of 84% of the supply voltage. Based on an OPA, with the technique of phase error compensation, reduction of the settling time by 18.4% is achieved.    Figure 10 shows the comparison of the simulated settling time between the optimized CP in the present design and the traditional CP without phase error compensation under different supply voltages. The results presented in Figure 10 were obtained from the schematic simulations. Compared with the traditional CP without phase error compensation, the optimized CP of the present design reduces the phase error of the PFD, leading to a decrease in the settling time from 89.6 µs to 73.1 µs. In the present design, only a 3-bit TDC was used to quantize and encode the phase error. With an increase in the bit number of the TDC, the delay time T decreases, and the locking capability can be further improved.   Figure 10 were obtained from the schematic simulations. Compared with the traditional CP without phase error compensation, the optimized CP of the present design reduces the phase error of the PFD, leading to a decrease in the settling time from 89.6 μs to 73.1 μs. In the present design, only a 3-bit TDC was used to quantize and encode the phase error. With an increase in the bit number of the TDC, the delay time T decreases, and the locking capability can be further improved.

Conclusions
In this work, a PLL charge pump with a low current mismatch for reducing locking time is proposed. The current mismatch caused by leakage current is below 1% for a broad output voltage headroom of 84% of the supply voltage. Based on an OPA, with the technique of phase error compensation, reduction of the settling time by 18.4% is achieved.

Conclusions
In this work, a PLL charge pump with a low current mismatch for reducing locking time is proposed. The current mismatch caused by leakage current is below 1% for a broad output voltage headroom of 84% of the supply voltage. Based on an OPA, with the technique of phase error compensation, reduction of the settling time by 18.4% is achieved.

Conflicts of Interest:
The authors declare no conflict of interest.