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Open AccessArticle

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

1
Department of Electrical engineering, Islamic Azad University, Mahshahr Branch, Mahshahr 6351977439, Iran
2
Department of Electrical engineering, Shahid Chamran University of Ahvaz, Ahvaz 6135783151, Iran
3
Center for Integrated Systems Engineering and Advanced Technologies, Faculty of Engineering and Built Environment, National University of Malaysia, Bangi 43600, Malaysia
4
Institute of Microengineering and Nanoelectronics, National University of Malaysia, Bangi 43600, Malaysia
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(11), 1285; https://doi.org/10.3390/electronics8111285
Received: 12 September 2019 / Revised: 15 October 2019 / Accepted: 23 October 2019 / Published: 5 November 2019
(This article belongs to the Special Issue Low-Voltage Integrated Circuits Design and Application)
An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved. View Full-Text
Keywords: delta-sigma modulation; multirating technique; multi-stage noise-shaping (MASH); time-to-digital converter (TDC); voltage-controlled oscillator (VCO) delta-sigma modulation; multirating technique; multi-stage noise-shaping (MASH); time-to-digital converter (TDC); voltage-controlled oscillator (VCO)
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Mouri Zadeh Khaki, A.; Farshidi, E.; Hamid MD Ali, S.; Othman, M. An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique. Electronics 2019, 8, 1285.

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