Search Results (60)

This study systematically compared spray drying (SD) and freeze drying (FD) for microencapsulating Idesia polycarpa oil using a soy protein isolate/maltodextrin (SPI/MD) wall system. SD produced predominantly spherical and compact microcapsules with higher solubility (51.33%), encapsulation efficiency (81.9%), and superior oxidative stability (oxidation induction period, 6.05 h), together with improved thermal resistance, indicating its suitability for applications requiring enhanced stability and aroma retention. In contrast, FD yielded irregular and porous microcapsules with significantly higher emulsifying activity (29.12 m² g⁻¹, p < 0.05) but lower solubility and encapsulation efficiency. Integrated physicochemical characterization-including scanning electron microscopy (SEM), Fourier transform infrared spectroscopy (FTIR), particle size and polydispersity index (PDI), ζ-potential, differential scanning calorimetry (DSC), oxidative stability index (OSI) measurements, and volatile profiling via odor activity value (OAV) analysis—revealed clear process-dependent structure–function relationships. The denser SPI/MD matrix formed during SD restricted lipid molecular mobility and oxygen diffusion, thereby suppressing lipid oxidation and promoting the retention of key lipid-derived odorants. Conversely, the porous structure generated by FD facilitated interfacial functionality but increased molecular diffusion pathways. Overall, this work demonstrates that SPI/MD-based microencapsulation functions as a molecular stabilization platform for highly unsaturated plant oils and provides mechanistic guidance for selecting drying strategies to tailor Idesia polycarpa oil microcapsules for specific food applications. Full article

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ($P_{sat}$) of 20.2 dBm, and a maximum large-signal gain ($G_{max}$) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. Full article

In this work, a layout-level design methodology is presented for Low-Noise Amplifiers (LNAs), targeting a wide frequency spectrum from RF to millimeter-wave (mmWave) bands, and implemented using a 22 nmFDSOI CMOS process. A nested inductor structure is introduced at RF frequencies to reduce silicon footprint, with magnetic crosstalk effects characterized through electromagnetic (EM) simulations using Ansys^® RaptorX, Release 2024 R2, ANSYS, Inc. and integrated into the design process. Single-ended LNA architectures are employed for RF bands, while at mmWave frequencies, a differential topology is adopted to enhance linearity and enable simultaneous input and output impedance matching. An EM-based verification flow is applied across all designs to ensure RF/mmWave design flow compatibility, simulation accuracy, and enhanced performance. The proposed designs are evaluated using key metrics including input/output matching, reverse isolation, forward gain, noise figure, linearity ($I{P}_1,I{P}_3$), stability factor, power consumption, and total chip area to quantify the efficiency of the proposed methodology. The simulation results demonstrate that nested inductors are highly effective for area reduction in RF LNAs, while differential topologies are more suitable for mmWave designs, providing a unified framework for area-efficient and high performance LNA implementation. Full article

A compact 8–15 GHz Doherty power amplifier (DPA) is proposed and fabricated in 22 nm FD-SOI CMOS. The proposed DPA relies on a quadrature-hybrid splitter and combiner to replace the bulky $\lambda$/4 impedance inverters at the input and the output of the conventional DPA enabling load modulation over a large fractional bandwidth (FBW = 61%) with efficient and compact integration. The proposed DPA achieves a peak gain of 19.6 dB; ≥17 dB across 8–15 GHz, 18 dBm P1dB, 19.5 dBm $P_{sat}$, and a peak PAE of 21% at 10 GHz, while sustaining 17% PAE at 6 dB back-off. The proposed DPA enables a modulation BW up to 200 MHz for a 256-QAM single carrier (SC) signal with a peak-to-average power ratio (PAPR) of 6 dB. Under this setting, the average output power (Pavg) is measured at 12.5 dBm with an RMS error vector magnitude (EVM) of $-24.1$ dB and an average PAE of 15%. Within the scope of CMOS power amplifiers in 22 nm FD-SOI, we found no published example that jointly demonstrates 8–15 GHz coverage and sustained PAE at 6 dB back-off using a quadrature hybrid. Full article

This paper presents a 0–360° phase shifter in 28 nm FD-SOI CMOS technology, suitable for radar applications and mm-wave wireless communication systems, which adopt high-efficiency transmitter architectures. It exploits a novel switching vector modulator based on a double-balanced Gilbert cell, which guarantees high-resolution phase control while exhibiting inherently high robustness against process and temperature variations. The phase control is performed by merely changing the currents in the Gilbert cells using digitally controlled current generators. The proposed phase shifter operates at 39 GHz and provides RMS phase and gain errors of 2.7–4.7° and 0.3–0.5 dB, respectively, while drawing 13 mA from a 1 V supply voltage. Full article

This paper presents a radiation-hardened 4-bit flash analog-to-digital converter (ADC) implemented in a 22 nm fully depleted silicon-on-insulator (FD-SOI) process for high-reliability applications in radiation environments. To improve single-event upsets (SEU) tolerance, the design introduces a compact fault-tolerant logic scheme based on Dual Modular Redundancy (DMR), offering reliability comparable to Triple Modular Redundancy (TMR) while using two storage nodes instead of three, and a simple XOR-based check in place of a majority voter. A distributed sampling architecture mitigates SEU vulnerabilities in the input path, while thin-oxide devices are used in analog-critical circuits to enhance total ionizing dose (TID) resilience. Post-layout simulations demonstrate SEU detection within 200 ps and correction within ~600 ps. The ADC achieves an active area of 0.089 mm², power consumption below 30 µW, and provides a scalable solution for radiation-tolerant data acquisition in aerospace and other high-reliability systems. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

Unmanned aerial vehicles (UAVs) are promising and powerful aerial platforms that can execute a variety of complex tasks. However, the increasing complexity of tasks and number of UAV nodes pose significant challenges for UAV sensing networks, such as limiting the spectral resources and increasing device complexity. A potential solution is to implement full-duplex (FD) technology in UAV sensor network transceivers. Although appropriate self-interference (SI) cancellation techniques have been employed in the digital domain, the amplitude of the signal of interest (SoI) is relatively small and can be obscured by SI, especially over longer distances. Moreover, the introduction of phase offsets when filtering measurement signals can lead to signal distortion, resulting in estimation errors in the measurement results. To address these issues, this paper presents a joint transmit (TX) and receive (RX) beamforming algorithm based on the penalty dual decomposition (PDD) algorithm, which considers the constraints of transmission power, reception power, and residual SI power. The simulation analyses demonstrate that with a limited number of antennas, the proposed joint TX-RX beamforming algorithm can effectively suppress SI by up to 140 dB, yielding high-precision measurements in UAV sensor networks without compromising the accuracy of the control signals. Compared with that of the traditional frequency-division duplex (FDD) mode, the measurement accuracy is not decreased; compared with those of the time-division duplex (TDD) mode, the distance and speed measurement accuracies of the UAVs are increased by 10 m and 1.5 m/s, respectively, in the FD mode because there is no interruption of the tracking loop and no continuous retracking in the FD mode. Full article

The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters. Full article

In this paper, a sub-1dB Low Noise Amplifier (LNA) with several gain modes, including amplification and attenuation modes required for the fifth and fourth generations (5G/4G) of mobile network applications, is proposed. Its current consumption is adaptive for every gain mode and varies to lower currents for lower amplifications due to the importance of current consumption for mobile network applications. The proposed LNA features an innovative architecture with a three-core input structure supporting multi-gain modes, achieving high gain and ultra-low noise performance. Additionally, the design integrates a cascade switching mechanism to ensure fast transitions between the gain modes and maintain operational stability. A reconfigurable input structure is introduced to support multiple input stages, enabling the proposed LNA to be compatible with both 5G and 4G applications. The proposed design demonstrates the implementation of seven distinct gain modes with a maximum current consumption of 11.68 mA, achieving proper input matching in each gain mode. The LNA delivers a maximum gain of 20.4 dB with a noise figure of 0.73 dB. Moreover, the most stringent mode switching condition achieved, the ON time, is as short as 1.295 µs, and the gain mode transition speed is an impressive 0.874 µs, ensuring extremely fast mode transitions. The proposed LNA occupies an area of 700 µm × 500 µm and is fabricated using a 65 nm FD-SOI process. Full article

Millimeter-wave (mm-Wave) phased array systems need to meet the transmitter (Tx) equivalent isotropic radiated power (EIRP) requirement, and that depends mainly on the design of two key sub-components: (1) the antenna array and (2) the Tx power amplifier (PA) in the front-end-modules (FEMs). Simulations using an electromagnetic (EM) solver carried out in Cadence AWR with AXIEM suggest that for two uniform square patch antenna arrays at 24 GHz, the 4 element array has ~6 dB lower antenna gain and twice the half power beam width (HPBW) compared to the 16 element array. We also present measurements and post-layout parasitic-extracted (PEX) EM simulation data taken on two broadband mm-Wave PAs designed in our lab that cover the key portions of the fifth-generation (5G) FR2-band (i.e., 24.25–52.6 GHz) that lies between the super-high-frequency (SHF, i.e., 3–30 GHz) band and the extremely-high-frequency (EHF, i.e., 30–300 GHz) band: one designed in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS process, and the other in an advanced 40 nm Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) process. The FD-SOI PA achieves saturated output power (P_OUT,SAT) of ~14 dBm and peak power-added efficiency (PAE) of ~20% with ~14 dB of gain and 3 dB bandwidth (BW) from ~19.1 to 46.5 GHz in measurement, while the GaN PA achieves measured P_OUT,SAT of ~24 dBm and peak PAE of ~20% with ~20 dB gain and 3 dB BW from ~19.9 to 35.2 GHz. The PAs’ measured data are in good agreement with the PEX EM simulated data, and 3rd Watt-level GaN PA design data are also presented, but with simulated PEX EM data only. Assuming each antenna element will be driven by one FEM and each phased array targets the same 65 dBm EIRP, millimeter wave (mm-Wave) antenna arrays using the Watt-level GaN PAs and FEMs are expected to achieve roughly 2× wider HPBW with 4× reduction in the array size compared with the arrays using Si FEMs, which shall alleviate the thorny mm-Wave line-of-sight (LOS)-blocking problems significantly. Full article

In this paper, the degradation mechanism of the RF performance of 22 nm fully depleted (FD) silicon-on-insulator nMOSFETs at different total ionizing dose levels has been investigated. The RF figures of merit (the cut-off frequency f_T, maximum oscillation frequency f_max) show significant degradation of approximately 14.1% and 6.8%, respectively. The variation of the small-signal parameters (output conductance (g_ds), transconductance (g_m), reflection coefficient (|Γ_in|), and capacitance (C_gg)) at different TID levels has been discussed. TID-induced trapped charges in the gate oxide and buried oxide increase the vertical channel field, which leads to more complex degradation of small-signal parameters across a wide frequency range. Full article

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of $128\times 128$, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%. Full article