# An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

^{1}

^{2}

^{*}

## Abstract

**:**

^{2}. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.

## 1. Introduction

## 2. Adaptive Receivers for IoT Applications

#### 2.1. Motivation

#### 2.2. State of the Art Adaptive Receiver

#### 2.3. Proposed Approach

_{TX}reaches a receiver P

_{RX}, with various channel path length, attenuation and delay. At the receiver side, the environment conditions of the channel is estimated thanks to the Link Quality Estimator (LQE). Different LQE can be exploited (RSSI, BER, etc.). After processing, the required performances are selected and the tuning information are send back to the analog and RF blocks which scale their performances and power.

## 3. Proposed Channel Aware Receiver

#### 3.1. Context of Application

- -
- IEEE 802.15.4 ZigBee standard addressed (ISM Worldwide band at 2.4 GHz);
- -
- Indoor propagation channels without the presence of adjacent blocker;
- -
- Peer-to-peer network arrangements;
- -
- Random and uniform nodes locations distribution in the area;
- -
- Nodes communicate with their nearest neighbor(s);
- -
- Signal suffering from average path-loss attenuation only.

#### 3.2. Probability Distribution of the Received Power

#### 3.3. Approximation of the Sensitivity and Power Consumption of the Receiver

#### 3.4. Optimized Reconfiguration Thresholds

- -
- The low performance mode has to be designed with a power consumption of 2.2 mW. It will be on this state for 76% of its lifetime.
- -
- The medium mode has to be designed with a 5.8 mW of power consumption it will be active for 23% of its lifetime.
- -
- The highest mode is the worst case design, essential to guarantee the QoS but active only 1% of the receiver’s lifetime.

#### 3.5. Design Specifications

## 4. FD-SOI ULP LNA Design for IoT Applications

#### 4.1. LNA Topology

_{LNA}, the input impedance Zin

_{LNA}and the Noise Figure NF

_{LNA}of this architecture are given in Equations (3)–(5) respectively.

_{m1}, g

_{m2}). The input matching is considered as acceptable—i.e., real part of Zin between 25 Ω and 75 Ω and imaginary part of Zin close to 0 which gives a S11 under −10 dB. The conditions on (g

_{m1}, g

_{m2}) which fit the requirements of Table 3 in terms of noise figure (≥7 dB) and voltage gain (≥15 dB) are also illustrated.

_{m1}and g

_{m2}respecting the conditions ①, ②, ③, and ④ are determined:

- -
- g
_{m1}= 2.5 mS; - -
- g
_{m2}= 5 mS.

_{m1}, g

_{m2}) for the minimum power consumption. Active transistors of the LNA (M1 and M2) have minimum gate length to achieve a maximum bandwidth at a minimum power consumption.

#### 4.2. Body Biasing

- -
- Vgs ≥ Vt;
- -
- Vds ≥ Vgs−Vt.

_{1}, W

_{2}, and I

_{bias}) reached for each power supply respecting the design specifications (Gv

_{LNA}= 15 dB, NF

_{LNA}≤ 7 dB, and S11 ≤ −10 dB). The dots represent the solutions without any back gate biasing. The minimum of power consumption in that case is reached for Vdd = 0.8 V. Beyond this power supply, there is no solution for a correct saturation of the transistors. The power consumption of the LNA at this operating point is 380 µW. This design solution gives a FoM of 25.3 with is over the theoretical FoM aimed in Section 4. Even without using the body biasing of the FD-SOI technology, this technology enables good design performance making it one of the best FoM of State of the Art LNA.

- -
- BG1 = 2 V;
- -
- BG2 = 2 V; and
- -
- Vdd = 0.6 V.

- -
- S11 = −10.5 dB;
- -
- Gv = 17.5 dB;
- -
- NF = 6.9 dB; and
- -
- Pdc = 300 µW.

#### 4.3. PVT Degradation Evaluation

## 5. Integrated Circuit (IC) Implementation and Measurement Results

#### 5.1. ULP LNA Mesurement Results

^{2}and the LNA core is only 0.0015 mm

^{2}. The ULP LNA is followed by a buffer added only for test facilities (output matching). The S-parameters and characteristics of this buffer are de-embedded from the proposed measurement results.

^{2}.

#### 5.2. Gain on the Battery Lifetime with the Proposed LNA

## 6. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

## References

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**Figure 1.**Repartition of the power consumption in a wireless sensor node [2].

**Figure 5.**(

**a**) Selection of the receiver operating mode during the synchronization preamble and (

**b**) Illustration of intra frame 3-levels reconfiguration receiver.

**Figure 6.**Probability distribution function (PDF) of the received power signal at the input of the receiver [10].

**Figure 8.**Details of the thresholds of the 3-modes receiver sensitivity [10].

**Figure 9.**Best gain on the battery lifetime with two sensitivity thresholds (T1 and T2) for a three modes receiver.

**Figure 13.**Behavior of the circuit for several (g

_{m1}, g

_{m2}): (

**a**) Imaginary part of Zin; (

**b**) Real part of Zin; (

**c**) Noise Figure in dB and (

**d**) Voltage gain in dB.

**Figure 14.**Fully Depleted Silicon-On-Insulator (FD-SOI) technology: (

**a**) Cross-section and (

**b**) Vth versus back gate voltage for a NMOS Low Threshold Voltage (LVT) transistor.

**Figure 16.**Performance of the ULP LNA under 0.6 V power supply versus several back gate voltages BG1 and BG2: (

**a**) voltage gain in dB; (

**b**) noise figure in dB; (

**c**) input matching in dB; and (

**d**) power consumption in W.

**Figure 17.**Monte Carlo simulations performed for 1000 occurrences: (

**a**) on voltage gain of the LNA and (

**b**) on noise figure.

**Figure 20.**Comparison of the proposed LNA with the State Of the Art LNAs: (

**a**) Figure of Merit I (FoM I) versus the power consumption and (

**b**) FoM II versus the power consumption.

Modulation | Frequency | Channel Bandwidth | Data Rate | Number of Nodes | Signal to Noise Ratio (SNR_{min}) | Bit Error Rate (BER) | Packet Error Rate (PER) |
---|---|---|---|---|---|---|---|

OQPSK | 2.4 GHz (ISM) | 5 MHz | 250 kbits/s | 2^{64} | 10 dB | 10^{−6} | 1% |

Mode | Low Performance Mode | Medium Performance Mode | High Performance Mode |
---|---|---|---|

Sensitivity (dBm) | −75 | −85 | −90 |

Usage time (%) | 76 | 23 | 1 |

Power consumption (mW) | 2.2 | 5.8 | 10 |

^{1}Calculation details available in [10].

Mode | Low Performance Mode |
---|---|

Sensitivity (dBm) | −75 |

Usage time (%) | 76 |

NF_{RX} (dB) | 22 |

NF_{LNA} (dB) | 7 |

Gv_{LNA} (dB) | 15 |

Pdc_{RX} (mW) | 2.2 |

Pdc_{LNA} (mW) | 0.5 |

**Table 4.**Degradation of the receiver sensitivity due to Process Voltage Temperature (PVT) variations on the LNA.

Performance | 3-σ min | 3-σ max |
---|---|---|

NF_{LNA} (dB) | 7.2 | 6.5 |

G_{LNA} (dB) | 16 | 18.8 |

Sensitivity (dBm) | −75.3 | −76.8 |

Ref. | Gv (dB) | 3 dB-BW (GHz) | NF (dB) | IIP3 (dBm) | Pdc (mW) | Supply (V) | Tech. | Area (mm^{2}) | FoM 1 | FoM 2 |
---|---|---|---|---|---|---|---|---|---|---|

T.W. | 16.8 | 0.45–6 | 7.3 | −16 | 0.3 | 0.6 | FDSOI 28 nm | 0.0015 | 29.3 | 53.7 |

[20] | 20 | 0.1–2.7 | 4 | −12 | 1.32 | 1.2 | CMOS 0.13 µm | 0.007 | 22.3 | 41.4 |

[21] | 14.7 | 2.1–2.5 | 4.8 | 2 | 0.6 | 1.8 | CMOS 0.18 µm | 0.39 | 7 | 19.2 |

[22] | 12.6 | 0.1–7 | 6.5 | −8 | 0.75 | 0.5 | CMOS 90 nm | 0.23 | 21.1 | 17.8 |

[17] | 10.6 ^{1} | 0.1–1 | 4 | −10.2 | 0.72 | 1.2 | CMOS 0.13 µm | 0.26 | 8.9 | 0.3 |

[23] | 9.9 ^{1} | 0.1–2.2 | 5.5 | −11.5 | 0.4 | 1 | CMOS 0.1 µm | 0.0052 | 16.7 | 39.4 |

[24] | 9.7 | 2–2.8 | 4.4 | −4 | 0.7 | 1.2 | CMOS 90 nm | 0.91 | 7.9 | 0.8 |

^{1}Gv(dB) = 20.log(S21(mag)/(S11(mag) + 1).

FoM LNA | Aimed: 23 | Measured: 29.3 |
---|---|---|

Gain on the battery lifetime | 5.1 | 6.7 |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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**MDPI and ACS Style**

Zaini-Desevedavy, J.; Hameau, F.; Taris, T.; Morche, D.; Audebert, P.
An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis. *J. Low Power Electron. Appl.* **2018**, *8*, 10.
https://doi.org/10.3390/jlpea8020010

**AMA Style**

Zaini-Desevedavy J, Hameau F, Taris T, Morche D, Audebert P.
An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis. *Journal of Low Power Electronics and Applications*. 2018; 8(2):10.
https://doi.org/10.3390/jlpea8020010

**Chicago/Turabian Style**

Zaini-Desevedavy, Jennifer, Frédéric Hameau, Thierry Taris, Dominique Morche, and Patrick Audebert.
2018. "An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis" *Journal of Low Power Electronics and Applications* 8, no. 2: 10.
https://doi.org/10.3390/jlpea8020010