A 60-GHz Current Combining Class-AB Power Amplifier in 22 nm FD-SOI CMOS

Abstract

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ($P_{sat}$) of 20.2 dBm, and a maximum large-signal gain ($G_{max}$) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes.

1. Introduction

The growing demand for multi-gigabit wireless connectivity has accelerated the development of millimeter-wave (mm-wave) communication systems for 5G enhanced mobile broadband (eMBB), high-speed backhaul, and short-range links [1,2]. Among available mm-wave bands, the unlicensed 60 GHz spectrum stands out for its wide contiguous bandwidth, enabling multi-gigabit data rates and low-latency transmission [3,4]. The high carrier frequency also supports antenna–RF front-end (RFFE) co-integration on a single silicon chip, significantly reducing system size, cost, and power consumption. Such compact, energy-efficient integration is advantageous for both consumer devices and network infrastructure [5]. However, since the power amplifier (PA) dominates power consumption in front-end modules (FEMs), achieving high-efficiency mm-wave PA design remains a key challenge for low-power 5G systems.

Although the 60 GHz band lies outside the 3GPP FR2 allocations [6], it is increasingly recognized as a valuable complementary band for ultra-high-throughput and dense wireless environments. Modern mm-wave systems employ high-order modulation schemes (e.g., 64-QAM) to boost spectral efficiency [7], but their high peak-to-average power ratio (PAPR) demands highly linear and efficient PAs even under significant output back-off (PBO). Efficiency losses in this regime directly increase power consumption and thermal stress, making energy-efficient linear amplification essential to meet stringent EVM and 5G performance targets [8].

Various techniques have been proposed to enhance mm-wave PA performance, such as stacked-FET topologies for higher output power [9] and transformer-based combiners for compact power combining [10,11]. However, these often add layout complexity and insertion loss. Broadband matching networks can extend frequency range [12,13] but typically degrade peak efficiency due to additional passive elements. Furthermore, deeply-scaled CMOS technologies face limited breakdown voltage, reliability concerns (HCI, BTI), and low passive quality factors, all of which hinder efficient, linear operation at 60 GHz. Fully-depleted silicon-on-insulator (FD-SOI) CMOS offers distinct advantages for mm-wave PA design [14]. With $f_t/f_{max}= 350/320$ GHz and an accessible back-gate terminal for threshold-voltage tuning, FD-SOI enables dynamic bias optimization to improve the gain–linearity–efficiency trade-off without extra circuitry [12,15].

This work presents a two-stage, deep class-AB 60 GHz PA implemented in 22 nm FD-SOI CMOS. The design employs a current-combining architecture to boost output power and leverages front-/back-gate biasing for enhanced linearity and optimized PBO efficiency. Post-layout simulations demonstrate competitive peak power-added efficiency ($PAE$), saturated output power ($P_{sat}$), large-signal gain ($G_p$), and $IMD3$ compared to state-of-the-art 60 GHz CMOS PAs [10,16].

The remainder of this paper is organized as follows: Section 2 and Section 3 describe the transistor-level optimizations and overall PA architecture, Section 4 presents simulation results, Section 5 discusses scalability to other mm-wave bands, and Section 6 concludes the work.

2. Design Methodology

2.1. Active Device

A key factor in realizing the expected performance is the accuracy of the active device’s small-signal model. In particular, properly accounting for layout-dependent parasitics—such as gate-drain capacitances, interconnect resistances, and substrate coupling—is essential, since these elements strongly influence gain, efficiency, and stability.

Figure 1 presents the simplified small-signal representation of the active device, which incorporates these parasitic effects to enable more reliable prediction of the PA’s performance across different layout styles and bias conditions. Parasitic effects associated with the substrate and back-gate network were neglected, a simplification that limits the model’s accuracy in the sub-THz spectrum and may overestimate its influence on key RF metrics, such as $f_T$ and $f_{max}$. Small-signal parameters are extracted from a unit SLVTN device with gate width 1 × 20 μm and minimum length of 20 nm. Simulations were carried out using the foundry-provided BSIM-IMG model, in combination with the cold-FET extraction method, as described in [17].

Extrinsic resistances are extracted by setting $V_{DS}=0 \mathrm{V}$ and sweeping gate bias for devices with different finger widths, allowing evaluation of their dependence on the number of unit-device fingers. Extrinsic inductances and shunt capacitances were omitted from the model of Figure 1, as their contribution to the small-signal response remains negligible up to 100 GHz.

Figure 2 shows that the gate resistance ($r_g$) decreases as the gate finger width is reduced, while the source and drain resistances ($r_d, r_s$) exhibit only slight variations. This reduction in gate resistance is particularly important, because it directly impacts the maximum oscillation frequency ($f_{max}$). Since $f_{max}$ is highly sensitive to extrinsic resistances, because the impact of $W_f$ in $g_m/g_{ds}$ is limited, accurate extraction of the extrinsic resistances is crucial for predicting and optimizing device performance.

By extracting the extrinsic elements (see Figure 2), the intrinsic device parameters can be determined with high accuracy across all gate bias conditions ($V_{DS}=0.8 \mathrm{V}$) and for different finger counts, as described in [17].

This provides a comprehensive picture of the device behavior for a fixed total gate width, as shown in Figure 3. The accuracy of the proposed small-signal model against the foundry-based reference model, through S-parameter plots on the Smith chart is validated through Figure 4. Extracted simulation results of the extrinsic resistances also highlight the strong dependence of $f_{max}$ on layout choices, emphasizing the need for careful geometry optimization to minimize parasitics and fully exploit the intrinsic capabilities of the transistor.

Despite the large-signal operation of the device, small-signal modeling is of great importance, since it enables accurate characterization of the amplifier’s gain and stability, which are essential for proper biasing, matching network design, and overall performance optimization.

2.1.1. Layout Optimization

In multi-finger transistor layouts, the contacted-poly-pitch (CPP) strongly affects the extrinsic drain and source resistances ($r_d/r_s$) and, in turn, the RF figures of merit. A relaxed CPP corresponds to a larger source/drain contact area at the silicon/silicide interface [18], which leads to lower drain/source extrinsic resistances and, consequently, to an improvement in the maximum oscillation frequency. Simulations comparing 1 × CPP and 2 × CPP unit devices were conducted to extract device parameters. The results indicate a reduction of approximately 1–1.2$\Omega$ in the drain/source extrinsic resistances, while the intrinsic parasitic capacitances of the model exhibit a decrease of at least 1–2$fF$, as summarized in

Table 1. Gate, Source and Drain extrinsic resistances for different contacted-poly-pitch (CPP), for a 64—finger, 1 × 20 μm total-width SLVTN device.

Layout Style	${\mathit{r}}_{\mathit{g}}\left[\mathsf{\Omega }\right]$	${\mathit{r}}_{\mathit{s}}\left[\mathsf{\Omega }\right]$	${\mathit{r}}_{\mathit{d}}\left[\mathsf{\Omega }\right]$
1 × CPP	22.1	4.6	5.1
2 × CPP	21.3	3.3	4.0

and

Table 2. Intrinsic transistor capacitances for different contacted-poly-pitch (CPP), for a 64-finger, 1 × 20 μm total width SLVTN device, under $V_{GS}\approx 0.5 \mathrm{V}$ biasing conditions (peak-$f_T/f_{MAX}$).

Layout Style	${\mathit{C}}_{\mathit{g}\mathit{s}}\left[\mathit{f}\mathit{F}\right]$	${\mathit{C}}_{\mathit{g}\mathit{d}}\left[\mathit{f}\mathit{F}\right]$	${\mathit{C}}_{\mathit{d}\mathit{s}}\left[\mathit{f}\mathit{F}\right]$
1 × CPP	11.2	5.6	12.7
2 × CPP	10.9	4.3	10

.

Due to the difficulty in accounting for additional substrate and back-gate parasitic capacitances and resistances in the simplified model of Figure 1, the dependence of $W_f/n_f$ on $f_{max}$ is not clearly captured, particularly at larger gate finger widths (see Figure 5). To assess the importance of this deviation, we quantified its magnitude across the relevant operating conditions. In particular, $f_{max}$ deviates by approximately 7.7%, which is sufficiently small to leave the original schematic design decisions unchanged. Nevertheless, the prediction of the optimum finger width ($W_{f_{opt}}$) remains feasible, as the 64-finger configuration exhibits a lower $f_{max}$ compared to devices with fewer fingers, i.e., 40 fingers or so. This observation is confirmed by BSIM-IMG foundry-based model simulations, which indicate an optimum configuration of 40 fingers ($W_{f_{opt}}\approx 0.5$ μm) for the unit device ($W_{tot}\approx$ 1 × 20 μm), yielding the highest maximum oscillation frequency ($f_{max}$). Because the maximum oscillation frequency ($f_{max}$) of the unit transistor is highly layout-dependent, careful layout optimization is essential to prevent severe performance degradation of the proposed PA compared to schematic-level simulations. An increased number of fingers, approaching the optimum value of 40 fingers, improves $f_{max}$ of the device; however, it also increases the layout–aspect ratio, which may introduce additional interconnect losses.

Apart from optimizing the finger width of the device, the total gate width must also be determined to meet the required PA specifications, including output power, gain, and efficiency. This consideration leads to the selection of a 4 × 20 μm transistor array, instead of a single 1 × 80 μm device, offering an improved trade-off among output capability, linearity, and matching requirements, as will be analyzed in the following subsection.

To achieve a proper layout of the 4 × 20 μm transistor, two basic layout configurations—with 8-finger- and 40-finger-unit transistors—were evaluated and compared. Full RCC parasitic extraction was performed at the transistor level, while EM simulations were used to capture interconnect parasitics (see Figure 6). For improved process tolerance and device matching, a 2 × 2 transistor array was implemented for both finger configurations [16]. This way, higher $f_{max}$ can be achieved compared to 1 × 80 μm devices, due to the lower drain-source resistance ($r_{ds}$), despite lower gate resistance. A zipper-style layout topology was adopted [19], with careful attention to minimizing gate–drain overlap and ensuring compliance with electromigration and reliability constraints.

To minimize the extrinsic gate–drain capacitance ($C_{gd}$) without introducing gate–drain overlap, the drain is connected at the center of the transistor array and routed up to the top Cu metal layer (OI), with appropriate sizing to account for electromigration limitations. As for the gate network, each transistor employs a double-sided gate connection on M1 metal, with the gate node further routed on the opposite side of each drain line and lifted up to the C3 metal layer. Finally, the source network is routed along the outer edge of the transistor array, extending from the M1 metal layer up to the OI metal, to ensure a robust source and bulk reference connection. The gate node is then routed beneath this source network, which unavoidably increases the extrinsic gate–source capacitance ($C_{gs}$), resulting in a small degradation in maximum oscillation frequency ($f_{max}$), compared to round-table topology configuration of devices [11].

Apart from layout optimization, which reduces device and interconnect parasitics, this design also employs a neutralization technique to enhance transistor gain and stability [10]. The unintended negative feedback path created by parasitics restricts power gain and reverse isolation, and can even lead to instability. Although the 40-finger configuration initially demonstrates higher $f_{max}$ (see Figure 7) and power gain, the extended gate/drain interconnects necessitate longer routing to the neutralization capacitors. The required neutralization capacitance ($C_{neu}$) remains nearly the same across different finger configurations, since $C_{gd}$ shows only minor variation in finger count. This introduces additional insertion losses (~0.8 dB) compared to the more compact 8-finger configuration, ultimately reducing the performance advantage and leaving only a marginal difference between the two layouts.

A degradation of approximately 0.7 dB and 1.2 dB is observed for the 8- and 40- finger configurations, respectively, primarily due to the increased drain/source resistance introduced by longer interconnect lines in the narrower-finger transistor arrays (see

Table 3. MAG/MSG power gain at 60 GHz for a 4 × 20 μm SLVTN transistor with 8- and 40-finger configurations, evaluated before and after RCC + EM parasitic extraction at the peak $f_{max}$ bias point.

Approach	$\mathbf{Peak} {\mathit{f}}_{\mathit{m}\mathit{a}\mathit{x}}$ $\left[\mathbf{G}\mathbf{H}\mathbf{z}\right]$ $({\mathit{n}}_{\mathit{f}}=8$)	$\mathbf{Peak} {\mathit{f}}_{\mathit{m}\mathit{a}\mathit{x}}$ $\left[\mathbf{G}\mathbf{H}\mathbf{z}\right]$ $({\mathit{n}}_{\mathit{f}}=40$)	$\mathit{M}\mathit{A}\mathit{G}/\mathit{M}\mathit{S}\mathit{G}\left[\mathbf{d}\mathbf{B}\right]$ $({\mathit{n}}_{\mathit{f}}=8$)	$\mathit{M}\mathit{A}\mathit{G}/\mathit{M}\mathit{S}\mathit{G}\left[\mathbf{d}\mathbf{B}\right]$ $({\mathit{n}}_{\mathit{f}}=40$)
BSIM-IMG (pre-layout)	253	297	13.1	14.8
RCC + EM extraction 1	227	256	12.4	13.6

¹ BSIM-IMG foundry model is used for unit finger devices, not SSEC model.

). This variability (corresponding to a ~16% reduction in $f_{max}$ and >1 dB power gain loss), combined with the excess area penalty, makes the 40-finger layout a less compelling solution [11]. Moreover, the reduced gate finger width (of 0.5 μm versus 2.5 µm) further amplifies sensitivity to process variations, leading to larger corner-dependent performance spreads. Indeed, this layout style fails to retain the advantages of smaller $W_{f_{opt}}$, because of increased interconnect parasitics and higher gate resistance ($r_g$). Therefore, alternative design strategies must be investigated to mitigate interconnect effects while maintaining the benefits of small optimum gate finger widths for maximum $f_{max}$.

For these reasons, the 8-finger configuration with the zipper-layout transistor array topology was preferred, offering the most favorable trade-off in terms of performance, area efficiency, and power consumption.

2.1.2. Device Sizing

Having examined the trade-offs of multi-finger transistor array designs in the proposed PA, this chapter evaluates the influence of total gate width on device performance. Figure 8 presents the load-pull optimum points for gate widths between 60 μm and 120 μm, evaluated at the 1 dB compression point of the neutralized CS differential amplifier. The optimum load points for maximum output power at 1 dB compression are shown in Figure 8a, requiring purely resistive terminations ranging from 12.5 Ω (~16 dBm) to 30 Ω (~13 dBm). In contrast, when terminated for optimum PAE at 1 dB compression, the load impedance includes a substantial inductive component, shifting closer to a 50 Ω match.

All simulations were carried out under deep class-AB biasing ($V_{GS}=0.3 \mathrm{V}$) of the neutralized CS power core to maximize drain efficiency, with proper neutralization applied for each gate width to maintain stability (see Section 2.1.3). From these results, a total gate width of 80 μm (4 × 20 μm) was chosen as optimal, achieving more than 15 dBm output power, without significant efficiency degradation (~28%).

2.1.3. Neutralization Capacitors

Neutralization of the core devices is crucial for ensuring stability and improving the power gain of the power cell.

As shown in Figure 9, a value of $16 fF$ was chosen to maximize the amplifier’s stability factor, with dimensions optimized to minimize interconnect lengths. While larger capacitor values enhance stability, excessive neutralization can introduce a positive feedback path, lowering the stability factor and potentially degrading performance. To maintain stable operation despite process, voltage, and temperature (PVT) variations, the design must include sufficient safety margin. Simulations indicate a capacitance variation of approximately 13% for foundry APMOM capacitors, after EM extraction and corner analysis. Careful sizing of the neutralization capacitor near $16 fF$ ensures that performance is maintained, while accommodating expected fabrication and operating variations.

Monte Carlo simulations, depicted in Figure 10, further show the resulting variation in the amplifier’s stability factor and power gain, confirming that the design remains robust under statistical process fluctuations for $C_{neu}=16 fF$ and $V_{GS}=0.3 V$. Including the inherent loss of on-chip passive matching networks in simulations can further enhance the amplifier stage’s stability during the design phase.

Although differential-mode stability is improved, common-mode signals can degrade stability due to mismatches in the differential paths, as the neutralization capacitor increases the reverse feedback capacitance [20]. To address this, the interstage matching network incorporates a high-resistance path that prevents common-mode currents from flowing into the gates of the output-stage transistors. Consequently, the output stage is biased through $R_G\approx 4.9 \mathrm{k}\Omega$ resistors at the gates of the differential pair, rather than via the center tap of the interstage transformer that provides a low-impedance node at high-frequencies.

2.2. Linearity Optimization

To assess and optimize the linearity of the power stage, we begin by characterizing the device’s small-signal and nonlinear behavior through the first-order transconductance ($G_{m,1}$), as estimated using the SSEC method described in Section 2.1. From this foundation, the third-order transconductance ($G_{m,3}$) is extracted, which is directly associated with third-order intermodulation distortion ($IMD3$).

$$I_{ds,3}={\displaystyle \frac{2}{15\pi }}Re\sum _{i=1}^N{\displaystyle \frac{K_i{\left(A^2-{\left(V_{GS}-V_i\right)}^2\right)}^{5/2 }}{A^3}}$$

(1)

By combining these simulated results, the analytical prediction of the third-order harmonic current [21] can be carried out using (1). This approach provides a framework for evaluating the PA’s linearity behavior across different front-gate bias conditions and enables a direct comparison between the prediction stage and two-tone large-signal simulations, thereby identifying the bias “sweet spot” where linearity is maximized.

Simulation results based on (1) indicate a sweet spot near $V_{GS}=0.3 \mathrm{V}$ front-gate bias, corresponding to deep class-AB operation (see Figure 11), with a shift towards higher output power when the device is biased around $V_{GS}=0.2 \mathrm{V}$ in class-C operation (decrease in $V_{GS}$). However, at lower output power, class-C biasing results in higher third-order intermodulation distortion ($IMD3$), as the device operates closer to the turn-off region. The predicted behavior of the sweet spot is validated through two-tone large-signal simulations, which show good agreement with the analytical model, as depicted in Figure 12.

In addition to maximizing linearity, biasing at this sweet- pot enhances the efficiency of the PA, achieving an optimal balance between output power, linearity and power consumption. Additionally, the FD-SOI technology provides an additional biasing option through the back gate, which can be independently biased up to 2 V. This back-gate voltage ($V_{BG}$) modulates the device threshold voltage ($V_{TH}$), thereby influencing the drain current and the resulting class of operation. Access to the back-gate terminal enables both compensation for process-induced variations in $V_{TH}$ and dynamic adjustment of the PA’s class of operation.

Two-tone simulations were also performed under adjustable back-gate biasing, as depicted in Figure 13. The results show that increasing $V_{BG}$ at lower front-gate bias can effectively shift the sweet spot to lower output power, without incurring additional power consumption in the active devices.

Specifically, applying a small positive back-gate voltage of approximately 0.8 V reduces $IMD3$ to below −57 dBc, when the front gate is biased at 0.2 V with an output power of 2.5 dBm (see Figure 14), compared to $IMD3$ exceeding −40 dBc at the same output power, without back-gate bias and with the front-gate biased at 0.3 V. Similarly, class-C operation ($V_{GS}=0.1 \mathrm{V}$) at lower output power is enhanced by increasing the back-gate bias, while at higher output powers near 5 dBm, $IMD3$ remains largely unaffected compared to the case with zero back-gate bias.

Finally, a full front-gate bias exploration was carried out under a continuous-wave (CW) input signal at 60 GHz to evaluate the PA’s large-signal response across the entire bias range, as depicted in Figure 15. Biasing near the optimum linearity point in deep class-AB operation ($V_{GS}\approx 0.3 \mathrm{V}$,$I_q\approx 4 \mathrm{m}\mathrm{A}$) provides the highest PAE and output power at the 1-dB compression point, without a significant increase in power consumption, making it an attractive operating point for mm-Wave PAs.

The above simulated results reveal the combined effects of front- and back-gate biasing on both $IMD3$ and efficiency, enabling precise identification of the optimal operating point. Furthermore, the results show that the sweet spot for linearity and efficiency can be shifted and finely tuned through back-gate voltage control, offering designers a practical mechanism to balance output power, linearity and energy efficiency in high-frequency operation.

2.3. Cascode Topology

In addition to the neutralized CS devices, cascode transistors were adopted as the main amplifying core to provide higher gain—particularly important, since the PA is biased at the optimum linearity point (deep class-AB), where the intrinsic gain is reduced. It also offers improved isolation ($s_{12}$) and the ability to operate with a higher optimum load (higher voltage swing) compared to common-source (CS) neutralized devices. These characteristics make the cascode structure particularly well suited for achieving both high linearity and output power in compact, mm-Wave PA designs.

The cascode devices were sized identically to the CS transistors, to meet the required 15 dBm output power margin, while maintaining optimum linearity at a front-gate bias of $V_{bias}\approx 1.2-1.3 \mathrm{V}$. This ensures the CS transistors remain within the DC reliability limit of 0.9 V across drain-source. This biasing scheme and the higher gain preserves the same quiescent current but improved PAE, without degrading linearity or saturated power.

The capacitance at the cascode gate node is used to improve amplifier stability by mitigating reverse-feedback paths introduced through the cascode transistor. It also balances the stability versus $P_{out}/PAE$ trade-off, since moving the gate node to an ideal AC ground increases voltage swing at the output. The improvement in output power and PAE is evident in Figure 16 at the schematic (pre-layout) level, where load-pull simulations were performed across different gate-bias capacitances, while also monitoring the stability of the cascode PA. Moreover, near the $60 fF$ optimum point, the cascode amplifier exhibits an increased optimum load impedance of approximately $\left(35+j56\right) \Omega$, which is far more practical to realize with passive networks compared to CS amplifier’s optimum impedance ($Z_{opt}\approx 20 \Omega$).

The intrinsic interconnect parasitics of the cascode devices are critical for both efficiency and impedance matching at the amplifier’s input and output. To account for these effects, all device interconnects were EM simulated, as shown in Figure 17, and incorporated into the modeling to enable accurate prediction of the mm-Wave PA’s performance. Due to additional interconnect/matching-network losses, the implemented gate capacitance was finally increased to $120 fF$, shifting the optimum load to $\left(35+j56\right) \Omega$.

A full large-signal comparison is performed between the optimum termination points of the neutralized CS amplifier described in Section 2.2 and the neutralized cascode topology discussed here. The addition of cascode devices results in approximately 3 dB higher gain and reduced DC power consumption near the compression point ($I{P}_{1dB}$). The results demonstrate clear improvements in output power, linearity, and efficiency provided by the cascode structure, particularly under the optimum linearity bias point.

To further validate these observations, two-tone simulations were also conducted under zero back-gate bias ($V_{BG}=0 \mathrm{V}$), serving as a reference for assessing the linearity benefits of the cascode over the CS implementation, as illustrated in Figure 18b. The higher gain shifts the second sweet spot to higher output power, while simultaneously suppressing third-order $IMD3$ products to below −50 dBc.

3. Overall 60 GHz Power Amplifier Architecture

The complete PA design integrates cascaded driver and power stages with inter-stage and output matching networks. A dual-path architecture is adopted to enhance output power while mitigating device loading, thereby improving efficiency and reliability. The two paths are combined through a transformer-based network, ensuring proper impedance transformation and high combining efficiency. This is particularly critical for low-power eMBB handheld applications, where both area and power budgets are tightly constrained. Within each path, two unit-core power stages (Figure 17) are paralleled through compact transmission-line current combiners, ensuring amplitude/phase balance with minimal insertion loss, albeit at the cost of a reduced optimal load impedance to be matched. This configuration nearly doubles the output power per path, without compromising the efficiency of the amplification stages, and simplifies the combining structure while still ensuring efficient impedance transformation and robust output power delivery at 60 GHz. The design focuses on narrowband matching around 60 GHz (3-dB bandwidth $\approx$10 GHz), achieving high efficiency and compact implementation without the additive losses and complexity of broadband solutions. The full PA architecture, including all layout-based passive networks, is shown in Figure 19.

3.1. Power- and Driver-Stage Layout

The PA’s driver and power stages are shown in Figure 20, implementing the topology shown in Figure 17b. As detailed in Section 2, careful grounding of the bulk and transistor source nodes is implemented, via M1 and C3 metal ground planes. Additionally, the source node is routed to the topmost Al layer (LB) with a dedicated trace to minimize extrinsic parasitic resistance, preventing unwanted degeneration of the PA core. The driver stage follows a similar layout, requiring only a single gain cell versus two in the power stage. All capacitors (neutralization and gate bias) are alternative-polarity MOM (APMOM) devices from the foundry, with additional M1–C3 fingers acting as shields on either side.

3.2. Passive Design

The power stage incorporates the designed OMN and balun-based power combiner, which merges the dual-path outputs, while providing the required impedance transformation to the $C_{pad}//50 \Omega$ complex load. Baluns are implemented on each path for impedance transformation, and the paths are combined via transmission-line current combiner. The dual-path stage exhibits an optimum load impedance of $\left(35+j56\right) \Omega$ for maximum PAE at the 1 dB compression point (~41%, Figure 18a).

Post-layout EM simulations indicate that the OMN maintains approximately 72% combining efficiency (−1.4 dB insertion loss) while delivering near-optimal terminations (see Figure 21b). The simulated input impedances at each port of the combiner across 50–70 GHz lie well within the 17–20 dBm load-pull contours corresponding to $O{P}_{1dB}$, confirming proper matching over the targeted frequency range. Harmonic balance simulations further show that the combined paths nearly double the output power, with only 1.4 dB gain degradation and a minor PAE reduction to ~28%, as expected from the insertion losses of the combiner, validating the effectiveness of the dual-path current-combining architecture. The output power improvement is near 1.6 dB with this OMN topology.

To boost the overall power gain, the driver stage is interfaced with the output stage via the inter-stage matching network (Figure 19). The driver design is critical to preserve the PA’s PAE and linearity. Employing a unit PA (Figure 20b) in the driver ensures linear operation near its 1 dB compression point, as the power stage’s $I{P}_{1dB}$($\approx$10 dBm) is significantly lower than the driver’s $O{P}_{1dB }$($\approx$12 dBm). A 2:1 transformer is used between the stages (Figure 22a) to provide the necessary impedance transformation from the driver’s optimum load ($36+j90$ Ω) to the input of the power stage ($Z_{in}\approx 6 - j50$ Ω), while maintaining amplitude/phase balance and minimizing insertion loss. This guarantees efficient power transfer across the entire 50–70 GHz band.

Load-pull results for the driver stage (Figure 22b) show that the inter-stage matching network cannot achieve impedance transformation exactly at the driver’s optimum PAE point. This approach would necessitate a very low inductance for the primary turns, which in turn requires a smaller diameter. However, the reduced diameter increases insertion loss due to unwanted capacitive coupling between adjacent turns [11]. Therefore, the inter-stage matching network follows the 30–31% PAE contour across most of the band, eventually dropping driver’s stage PAE to around 20%, due to the transformer’s insertion loss of 1.7–1.8 dB—higher than that of the OMN, since the 2-turn design is required. Owing to the high gain of the dual-stage architecture, the reduced efficiency at the driver output has only a minor influence on the overall PAE of the complete PA. The transmission-line (TL)-based interstage matching network [22] achieves proper load transformation, but still incurs approximately 2 dB insertion loss, even when designed to present the optimal load to each stage. This result, consistent with other TL-based IMN implementations, indicates that such alternative topologies do not provide a superior trade-off between insertion loss and load optimality.

The driver’s stage linearity was evaluated by plotting both single and 2-tone carrier output power response against across the operational range. From Figure 23, the linearity of the driver stage can be clearly observed, and the optimal linearity is verified, confirming that the stage operates as intended under the tested conditions.

Finally, the input matching network, shown in Figure 19, adopts a layout similar to that of the OMN, and is designed to transform the 50 Ω source impedance into the conjugate input impedance of the driver stage, thereby ensuring both stability and low input reflection. In addition to the transformer-based matching elements, a dedicated 2-turn inductor is incorporated to compensate for the parasitic capacitances at the driver input node, effectively restoring resonance and improving impedance alignment. The complete input matching network introduces only 1.4 dB of insertion loss, resulting in a slight reduction of the overall power gain, without affecting the symmetry of each gain path.

4. Simulation Results

The proposed PA was implemented in 22 nm FD-SOI CMOS technology, occupying an area of 0.45 × 0.18 mm², excluding pads, and consuming only 95 mW under a 1.8 V supply. S-parameter and large-signal simulations of the complete PA architecture (Figure 19) were carried out with full electromagnetic (EM) modeling of all interconnects and passive networks (at $60 °\mathrm{C}$). Additionally, two-tone simulations were performed to validate the linearity enhancement of the design, and envelope analysis was conducted to assess its performance under complex modulation schemes.

4.1. Small-Signal and Large-Signal Continuous-Wave (CW) Simulation

Figure 24 shows the simulated S-parameters of the proposed PA. The $s_{21}$ parameter indicates a 3 dB gain bandwidth of 11 GHz. Input matching is well achieved, with $s_{11}$ remaining below –10 dB from 55 GHz to 65 GHz.

The aggressive neutralization results in $s_{22}$ approaching the edge of the Smith chart. The reverse isolation $s_{12}$ is lower than −40 dB across the frequency range of operation. The stability factor calculated from the simulated S-parameters is presented in Figure 25, proving the unconditional stability of the proposed PA across the entire frequency range.

Under large-signal conditions, the PA is characterized in two primary operating modes. In high-gain mode (H), both stages are biased at the optimal linearity point via the front gates, achieving deep class AB operation and a peak gain of 19.6 dB. In high-linearity mode (L), an additional 0.8 V back-gate bias is applied while the front-gate voltage is reduced, trading power gain for improved linearity.

Figure 26 presents the measured large-signal performance of the proposed PA under a 60 GHz continuous-wave (CW) excitation at 60 °C. The amplifier achieves a saturated output power of 20.2 dBm, with the total DC current increasing to approximately 200 mA as the input power increases. In high-gain mode (H), the PA exhibits a 1 dB compression point (OP1dB) of 18.2 dBm, while in high-linearity mode (L), the linearity is enhanced, shifting the OP1dB to 19.7 dBm at 60 GHz. The peak power-added efficiency (PAE) is 28.4% in high-gain mode and 27.3% in high-linearity mode, both occurring near the saturation region of the amplifier. The high-linearity (L) configuration further reduces the DC power consumption by at least 38 mW (see Figure 27), and shifts the 1 dB compression point to 19.7 dBm, thereby extending the amplifier’s linear region. These results highlight the PA’s capability to trade gain for linearity, while maintaining high efficiency and lower DC power consumption.

Figure 28 illustrates the simulated large-signal performance of the PA across frequency. The maximum saturated output power occurs near 60 GHz, remaining above 19 dBm over a broad 50–67 GHz range, corresponding to a 1 dB saturated output power bandwidth exceeding 15 GHz. In contrast, the power-added efficiency (PAE) exhibits a narrower frequency response, with a pronounced drop outside the 60 GHz center frequency, indicating a more frequency-selective efficiency behavior.

Before analyzing linearity and modulated signal performance, it is essential to evaluate the robustness of the proposed PA under process, voltage, and temperature (PVT) variations. Figure 29 summarizes the impact of supply voltage and temperature on key performance metrics through a heat-map representation, with results averaged across all process corners. This analysis highlights the sensitivity of the PA to bias and thermal conditions, allowing us to identify regions of stable operation where output power, efficiency, and linearity are preserved. Such an evaluation ensures that the PA maintains reliable performance across realistic operating environments and provides design insight into trade-offs between supply scaling, thermal effects, and efficiency.

In addition to PVT analysis, Monte Carlo simulations were performed to evaluate the stability of the PA across device mismatch. The stability factor ${\mu }_u$ at 60 GHz was monitored over 1000 Monte Carlo runs, showing a 95% pass rate above the unconditional stability threshold (${\mu }_u>1$). The few marginal cases observed can be fully eliminated, achieving a 100% pass rate, by proper tuning of the gate-bias capacitance ($C_G$). This demonstrates that the proposed design maintains robust stability under statistical variations. Large-signal performance metrics were further evaluated under best, mean, and worst-case PVT conditions, using Monte Carlo statistical analysis. The results, summarized in

Table 4. Summary of large-signal performance metrics under Monte Carlo simulation across best, mean, and worst-case PVT conditions.

Metric	Worst	Mean	Best
$P_{sat}$ [dBm]	19.8	20.2	20.5
$O{P}_{1dB}$ [dBm]	14.2	17.9	19.5
$PA{E}_{max}$ [%]	25.9	28.4	30.9
$PA{E}_{1dB}$ [%]	11.3	23.7	29.8
Peak Gain [dB]	16.1	20.4	26.8
$P_{DC}@I{P}_{1dB}$ [mW]	338	228	155

, show that key figures of merit such as $P_{sat}$, $PA{E}_{max}$ and maximum power gain, exhibit limited statistical spread across corners. This confirms the robustness of the proposed PA design and highlights its resilience against process, voltage, and temperature variations.

It is worth noting that the 1-dB compression-related metric ($O{P}_{1dB}$, ${PAE}_{1dB}$ and ${P_{DC}}_{1dB}$) show higher sensitivity to process variation compared to saturated performance figures. This is primarily due to shifts in the operating point, such as threshold voltage ($V_T$) variations across process corners. However, the impact can be effectively mitigated in practice: by dynamically tuning the back-gate bias ($V_{BG}$), the amplifier can be steered back to its optimum bias point. A simple implementation using an on-chip DAC to adjust $V_{BG}$ in real-time would ensure stable and predictable linearity metrics across PVT conditions.

4.2. Two-Tone Large-Signal Simulation

Two-tone simulations were carried out to evaluate the linearity of the proposed PA under optimum linearity bias conditions. A frequency spacing of 20 MHz was applied, and the results show that the third-order intermodulation distortion ($IMD3$) products remain below −30 dBc for a wide output power range up to approximately 14 dBm.

The extracted third-order intercept point (IP3) is approximately 7 dB higher than the simulated 1-dB compression point ($II{P}_3 \approx 2.4 \mathrm{d}\mathrm{B}\mathrm{m}$). This reduced spacing is primarily attributed to additional deviations introduced by the multistage amplifier architecture, as well as to the limited harmonic content considered in the theoretical derivation, where only nonlinear terms up to the third order are assumed. In practical implementations, higher-order nonlinearities, interstage loading effects, and residual harmonic interactions slightly alter the relative positions of IP3 and IP1dB [23]. Nevertheless, the observed ~7 dB separation, as shown in Figure 30b, still indicates near-optimal linearity performance. This is consistent with the driver- and output-stage linearity optimizations discussed in Section 2.2, where front-gate biasing is employed to balance gain, compression behavior, and distortion in deep class-AB operation.

4.3. Simulated EVM Performance

Envelope analysis was performed to evaluate the large-signal linearity of the proposed PA under OFDM signals, following the IEEE 802.11ad standard [24], without back-gate biasing. The simulated results include error vector magnitude (EVM), spectrum emission, and compliance with spectral masks, as shown in Figure 31, Figure 32 and Figure 33. Average output power and peak-to-average power ratio (PAPR) were calculated for three modulation formats: SQPSK, 16-QAM, and 64-QAM. Constellation diagrams at specific output power levels are also shown to illustrate the signal quality and linearity performance.

The results show that EVM improves at specific output power levels as a result of the linearity enhancements discussed earlier, with notable reductions in EVM observed in the 8–15 dBm output power range. Within this output power range, the power-added efficiency remains above 20%, while the EVM stays well below the limits specified by the IEEE 802.11ad standard, ensuring efficient and reliable signal transmission for all the complex modulated schemes, as shown above. Modulated signals with higher PAPR, such as 64-QAM, exhibit more pronounced instantaneous peaks compared to lower-order schemes, like SQPSK or 16-QAM. As a result, for 64-QAM, the PA must operate with more back-off (<14 dBm) to maintain signal fidelity, which leads to a slight reduction in power-added efficiency (PAE ~20%) near the output power levels corresponding to the EVM limit (7.94% or −22 dB). This highlights the trade-off between maintaining low EVM and achieving high PAE for high-PAPR signals, emphasizing the importance of linearity optimization in multi-level modulation systems. Figure 34 presents the constellation diagrams of the proposed PA at an output power of 13 dBm, demonstrating accurate transmission and correct symbol recognition.

4.4. Adaptive Back-Gate Biasing

Finally, we investigate the impact of the PA’s operating mode on system performance by adjusting the back-gate voltage to switch between high-gain (H) and high-linearity (L) mode. Figure 35 illustrates the measured Error Vector Magnitude (EVM), power-added efficiency (PAE), and gain for a 64-QAM modulated signal under each mode. The results indicate that the operating mode significantly influences the linearity and efficiency of the PA, with corresponding variations in EVM and gain. Notably, in high-linearity mode, EVM decreases further within the 8–15 dBm output power range, as anticipated, while the efficiency remains nearly unchanged. This analysis highlights the trade-offs between efficiency and signal fidelity when the PA is dynamically reconfigured.

5. Discussion

While simulations provide valuable insight into the expected performance of the proposed PA, actual measurements are critical to validate these predictions and assess real-world applicability. Factors such as device non-idealities, parasitic capacitances and inductances, thermal effects, biasing variations, and packaging impacts can significantly influence PA behavior in ways that simulations may not fully capture. For instance, non-linearity arising from transistor mismatch or layout parasitics can degrade linearity, while thermal effects can reduce efficiency and shift operating points. Therefore, performing comprehensive measurements ensures reliable evaluation of linearity, power-added efficiency (PAE), gain, and overall system performance under realistic operating conditions, including modulated signals with high peak-to-average power ratios (PAPRs).

To further highlight the effectiveness of the proposed PA, its measured performance is benchmarked against previously reported PAs operating in similar frequency ranges and modulation schemes (

Table 5. Comparison of the proposed PA with state-of-the-art PAs.

	This Work *		[9]	[10]		[11]		[16]
Tech. (nm)	22		22	22		40		22
Mode	H	L	H	H	L	H	L	H	L
Stages	2-stage, cascode		1-stage, stacked FET	2-stage, cascode		2-stage, CS		2-stage, cascode
Output Network/Power Combining	2-way Current combining with TLine’s and balun		Balun, no combiner	Stacked transformer current combiner		2-way transformer voltage combiner		Current combining with TLine and balun
Freq. (GHz)	60		48-62	64		60		60
VDC per Tr. (V)	0.9		0.8	1.0		1.0		0.9
$P_{sat}$$(dBm$)	20.2		15	21		17.4		18.6
$\mathrm{Gain} (dB$)	19.6	16.1	10.6	31	20.5	21.2	17.0	30	22
$PA{E}_{MAX}$ (%)	28.4	27.3	11.8	28.7	28.2	28.5	30.3	20.5	19.6
$O{P}_{1dB}$$(dBm$)	18.2	19.7	12.6	15.3	19.5	14	13.8	14.1	15.7
$PA{E}_{1dB}$ (%)	26.6	23.8	<5	~15	>25	16.3	21.6	~5	~10
$P_{DC}$$(mW$)	396.8	360.2	-	~250	>300	153	106	396	369
$\mathrm{Area} (m{m}^2$)	0.45 × 0.18		0.05	0.0355		0.074		0.07
ITRS FOM **$( {\displaystyle \frac{W}{GH{z}^2}}$)	10,483		134	181,768		7,302		53,431

* Only simulation results at 60 GHz. ** $ITRS FOM \equiv Gain·P_{sat }\left(\mathrm{W}\right)·PAE(\%)·f^2\left(\mathrm{G}\mathrm{H}{\mathrm{z}}^2\right).$

). This benchmarking enables a fair and quantitative assessment of key performance metrics, including PAE, linearity (EVM and ACPR), output power, and gain. By relying on measured data from existing works rather than simulations, this comparison provides a more rigorous and credible evaluation, allowing clear identification of improvements, trade-offs, and the practical advantages of the proposed design. Overall, the discussion underscores the fact that while simulations are useful for design exploration, measured results are indispensable for validating performance, guiding optimization, and ensuring the PA meets stringent requirements for modern high-frequency communication systems.

6. Conclusions

In this work, a highly-linear, class-AB 60 GHz PA is proposed and simulated in a 22 nm FD-SOI process, demonstrating high efficiency and linearity across multiple operating modes. By adjusting the back-gate voltage, the PA seamlessly switches between high-gain (H) and high-linearity (L) modes, achieving a saturated output power of 20.2 dBm. Optimum linearity biasing ensures low IMD3 products and compliance with EVM specifications for high-PAPR modulation schemes. In high-gain mode, the PA delivers a power-added efficiency (PAE) of up to 28% with a gain of 19.7 dB, while in high-linearity mode, the EVM for a 64-QAM signal improves to 2–3% within the 8–15 dBm output power range, with efficiency remaining nearly constant. Statistical simulations further validate the design margins and robustness. The main contributions of this work are threefold: (i) the design of a highly linear class-AB 60 GHz PA in a 22 nm FD-SOI process, (ii) the usage of additional back-gate biasing to enable seamless switching between high-gain and high-linearity operating modes, and (iii) the demonstration of high efficiency and linearity performance under high-PAPR modulation schemes. These features make the proposed PA well suited for mm-wave wireless transceivers requiring adaptive performance trade-offs, such as 5G and beyond communication systems, where both energy efficiency and signal fidelity are critical.