A Thermally Stable Quasi-CMOS Bipolar Logic

: Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technologies of choice for digital sys-tems, were abandoned and superseded by CMOS. In this paper it is shown that now, when truly complementary pairs of bipolar transistors can be made, properly biased bipolar gates similar to CMOS gates are feasible, can be thermally stable and find practical applications.


!. Introduction
Bipolar technologies such as TTL, TTL-S, ECL, once the technologies of choice for digital systems, were totally abandoned and superseded by CMOS. The reasons are well known: large area of vertical bipolar transistors in comparison with MOS devices, larger device count in bipolar logic gates and larger power consumption. These properties made bipolar technologies mentioned above unsuitable for VLSI circuits. CMOS-like complementary bipolar logic gates similar to CMOS logic gates ( Figure 1) have been proposed long ago (1976, [1]) but never used. They will be called CBIP in this paper. In traditional bipolar technologies, in which TTL or ECL gates were made, good NPN vertical bipolar transistors were available but PNP transistors had different physical structures and much worse parameters. They were not complementary to their NPN counterparts. Moreover, vertical transistors were strongly asymmetric, with heavily doped emitter, much lower doping in the collector and different areas of emitter-base and collector-base junctions. Such transistors have relatively high voltage drop between emitter and collector when switched "on" in a digital gate. As a result, both "0" and "1" voltage levels would be degraded ("0" voltage level higher than 0 and "1" voltage level lower than supply voltage) if asymmetric transistors were used in a CMOS-like digital gate. In 2011 a new structure of a lateral bipolar transistor on SOI, technologically compatible with PD-SOI (Partially Depleted Silicon on Insulator) CMOS circuits, has been demonstrated [2]. Such transistors are small and symmetric, complementary pairs of NPN and PNP devices can be made. Later in a series of papers [3][4][5][6][7] these transistors were investigated both theoretically and experimentally, including experimental characterization of inverters, SRAM cell flip-flops and ring oscillators. It was suggested that CMOS-like bipolar logic, i.e. logic gates made of complementary pairs of NPN and PNP transistors, could be useful both for very fast circuits and very low power circuits. Later another SOIbased technology, in which complementary pairs of symmetric NPN and PNP transistors as well as MOS devices can be made, has been demonstrated [9,10]. One more bipolar device concept -symmetric lateral doping-free bipolar transistor -has been proposed [11] and investigated [12,13]. In spite of these very promising works CMOS-like bipolar logic is still not used in digital integrated circuits.
There is a fundamental difference between CMOS logic gates and similar CBIP logic gates: the input current. In MOS transistors the input (gate) current is equal to zero (except gate leakage that is negligible in state-of-the-art very small devices) while in bipolar transistors the input (base) current in the "on" state is not negligible. When the output of a CBIP gate is connected to the input of another CBIP gate, the current drawn by this input from the output of the previous gate (as shown in Figure 2) distorts the voltage transfer curve of the previous gate. The input (base) currents in CBIP gates depend exponentially on the input (baseemitter) voltages and rise exponentially with temperature. This thermal effect is highly undesirable and makes CBIP-based logic circuits practically useless at elevated temperatures. In this paper a simple solution mitigating this effect is proposed in Section 2. In Section 3 the properties of CBIP gates performing NOT, NOR and NAND logic functions are discussed in the context of the solution of the thermal problem proposed in Section 2. Examples of CBIP-based logic circuits are also shown. Section 4 discusses the results shown in previous Sections and suggests possible applications of CBIP circuits. Transistor models used in simulations are given in Appendix. These models roughly correspond to the experimental characteristics of NPN devices discussed in [2, Fig.9]. To simplify interpretation of the simulation results, in most cases it is assumed that the models of NPN and PNP devices are identical.

Thermal stability of CBIP gates
Let us consider a CBIP inverter biased as in Figure 3. It is assumed that the voltage level of logic "1" equals the supply voltage VCC.  If the supply voltage is reduced to 0.65 V, the transfer characteristic is still acceptable, and the input current is reduced to nanoamperes -see Figure 5. However, reduction of the supply voltage does not solve the problem of the input current because this current strongly increases with temperature. Figure 6 shows the transfer characteristic and input current at 400K. The input current increases from 3 nA to 600 nA. To mitigate this thermal effect, a solution borrowed from analog domain can be used. Figure 7 shows this solution. The supply voltage for the CBIP inverter Q2-Q3 equals the base-emitter voltage of transistor Q1. This voltage also defines the logic level "1". With "1" (i.e. Vsupply) at the input of the inverter transistors Q1 and Q2 make the current mirror. If both are identical and their temperatures are identical, both collector currents are the same (neglecting base currents). If the collector current of Q1 (determined by the VCC voltage and resistance R) does not depend on temperature, the collector current of Q2 also does not depend on temperature. The input current of the inverter will be hFE -times lower. It will depend somewhat on temperature because hFE is temperature-dependent, but this dependence is rather weak, not exponential.
It is worth noting that Q1 and Q2 need not be identical. If they aren't, the collector current of Q2 will be proportional to the collector current of Q1. If the collector current of Q1 does not depend on temperature, the collector current of Q2 will not depend as well. If the logic level at the input of the inverter is "0", current mirror is composed of transistors Q1 and Q3 -see Figure 8. The base-emitter voltages of Q1 and Q3 are identical. In the general case Q1 (an NPN device) and Q3 (a PNP device) will not be identical but since the collector current of Q1 is temperature-independent, thermal stability of the inverter will be maintained. To demonstrate this, simulations shown in Figure 9 and Figure  10 were carried out with NPN model different from PNP model -see Appendix. The input current characteristics are no longer symmetric but the input current at 400K is almost the same as at 300K.   The thermal stabilization idea shown in Figures 7 and 8 can be extended to logic blocks with any number of CBIP inverters and other gates, as shown in Figure 11. By varying R one can vary the sum of all currents consumed by the logic gates in this block, i.e. the overall current consumption. Of course, thermal stabilization of the whole block requires the same temperature of Q1 and all the transistors in the logic block. Figure 11. Thermally stabilized logic block.
Note that increase of the temperature from 300K to 400K results in reduction of the supply voltage, which is also the "1" voltage level, from 650 mV to 465 mV (Figures 9 and  10). This is not a problem in a digital circuit if the supply voltage and the "1" voltage level are the same for all CBIP gates in the circuit, as in Figure 11. Examples are shown in the next Section.

NAND and NOR gates
The schematic diagrams of NAND and NOR gates are shown in Figure 12.

AND and OR gates
By adding inverters at outputs of NAND and NOR gates we obtain AND and OR gates ( Figure 14).

The effects of load
All transfer characteristics shown above (Figures 4,5,6,9,10,13 and 15) were obtained for gates without any load connected to their outputs. Figure 16 shows inverters with resistive load (a) and load in the form of input of another inverter (b). The maximum current that can be drawn from output of any gate will never exceed the current supplied from VCC: = ( − )/ . In practice this means that the load resistance RL must be much larger than R. However, even resistive load that meets this requirement will shift the transfer characteristics of the gate. This is shown in Figure 17a. If the output of a CBIP gate is connected to the input of another CBIP gate, as in Figure 16b, the transfer characteristic of the first gate is strongly distorted, as shown in Figure 17b. However, the transfer characteristic from the input to the output of the second gate is correct. In the next subsection it is demonstrated that logic blocks with CBIP gates work correctly despite distortion shown in Figure 17b.

Two examples
The first example demonstrates operation of a simple logic block (C17 ISCAS benchmark) implemented with CBIP gates. The logic diagram of C17 benchmark is shown in Figure 18. The block is thermally stabilized in the way shown in Figure 11.  It has been demonstrated [4,6] that delay of a CBIP inverter can vary by many orders of magnitude by varying its supply voltage. The performance of CBIP-based thermally stabilized digital circuits can be adjusted by the voltage VCC and/or resistance R. The second example demonstrates this feature by replacing resistor R by a NMOS transistor, whose gate voltage is controlled by a voltage source VREG (Figure 20). By varying this voltage the supply voltage and the frequency of oscillation of the ring oscillator are varied.   Figure 21 shows how the CBIP ring oscillator can be used as a voltage-controlled oscillator. The shortest oscillation period at VREG=1.5V equals 0.28 ns, the longest period at VREG=0.95V is approximately 125 ns. This simulation demonstrates flexibility of CBIPbased logic circuits: the same circuit can be used either as a high performance circuit or as a low power circuit by changing the VCC voltage and/or the resistance R (Figures 7 and 8). If the resistance R is replaced by an active voltage-controlled device, as in Figure 20, the performance and power consumption can be easily controlled in a working circuit and adjusted as needed for a given task.

Discussion and conclusions
The results of the simulations show that CBIP gates thermally stabilized as shown in Figures 7 and 8 can be used to build fully functional digital circuits working well in a broad range of temperatures. A unique feature of CBIP-based digital circuits is that the same circuit can be used either as a ultra-low power circuit or as a high performance circuit, and power vs. performance tradeoff can be easily controlled in a working circuit.
But the question is: who needs CBIP gates? It is rather obvious that CBIP-based digital circuits will not replace the most advanced FinFet or Nanosheet-based CMOS circuits. However, they can be technologically compatible with more traditional CMOS circuits. The symmetric lateral bipolar transistors on PD-SOI substrates [2][3][4][5][6][7] and CBIP gates using them could be used as additional components of PD-SOI CMOS circuits, for example in I/O buffers, or even as either high performance or ultra-low power digital blocks. The doping-free symmetric lateral bipolar transistors [11][12][13] could become a valuable addition to FD-SOI (Fully Depleted Silicon on Insulator) CMOS circuits, where channel area of MOS devices is not intentionally doped.
It is worth noting that bipolar transistors are very useful in analog circuits. In mixedsignal circuits the symmetric lateral bipolar transistors could be used e.g. in low noise amplifiers as well as in RF amplifiers. This topic is, however, beyond the scope of this paper.
Below are listed device models in Berkeley Spice format used in the simulations reported above.