A Surface-Potential-Based Analytical I - V Model of Full-Depletion Single-Gate SOI MOSFETs

: A surface-potential-based analytical I - V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal’s experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and e ﬃ ciency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10 − 7 V scale, and computation e ﬃ ciency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal’s experimental data. High computation accuracy and e ﬃ ciency suggest that this analytical I - V model displays great promise for SOI device optimizations and circuit simulations.


Introduction
Silicon integrated circuits (ICs) have become increasingly dense because the feature size of MOSFETs based on silicon-on-insulator (SOI) structure has not been a constraint in the sub-nanometer scale and both performance and cost improve as the feature size decreases. Up to now, there has still been considerable interest in optimizing properties of SOI MOSFETs [1][2][3] due to the widespread applications of SOI MOSFETs, such as sensors [4], memories [5], millimeter-wave circuits [6], and so on. Therefore, both device property optimization and IC design in the different fields imply that an analytical I-V model for accurately predicting I-V characteristics of SOI MOSFETs is imperative.
Recently, several analytical I-V models for bulk MOSFETs have been reported in the literatures [7][8][9][10][11] based on threshold voltage [7], inversion charge [8], and surface potential [9][10][11]. These models are demonstrated on the condition that the devices work in the partial-depletion (PD) mode, i.e., back-channel potential can be assumed to equate to zero or channel potential. However, these models cannot be applied into full-depletion (FD) single-gate (SG) SOI MOSFETs without any adjustment, due to the strong back-to-surface (B-S) potential coupling effect introduced by the ultrathin-body and buried oxide (BOX) in the FD SG SOI MOSFETs. Such a coupling effect increases the calculation complexity. In the meantime, some models [12][13][14][15] of multiple-gate SOI MOSFETs have been proposed, and some models of FD SG SOI MOSFETs [16][17][18][19][20] incorporating the B-S potential coupling effect are derived. Ravariu et al. [16] and Pandey et al. [17] developed threshold models for long-and short-channel FD SG SOI MOSFETs, respectively, by numerically solving a complicated equation about the position of the minimum back-channel potential. M. Miura-Mattausch et al. [18] also proposed an analytical I-V model of FD SG SOI MOSFETs based on a completely potential-based description solving the Poisson's equation iteratively together with additional equations. Here, numerical computation reduced the calculation efficiency. W. Wu et al. [19] and Y. S. Yu et al. [20] gave surface-potential-based analytical I-V models in which smoothing functions are employed. In addition. J. Huang et al. [21] described a DC model of FD poly-Si TFTs based on the assumption of B-S potential relation. Because of computation complexity, they gave up deriving B-S potential relation, leading to low computation accuracy.
In this paper, we propose a surface-potential-based analytical I-V model of FD SG SOI MOSFETs. An explicit solution of surface potential in FD SG SOI MOSFETs is solved from the 1-D Poisson's equation and derivation of B-S potential coupling relation. This surface potential calculation scheme has high computation accuracy and efficiency, which is verified by numerical techniques. Subsequently, based on the surface potential, we present the drain current analytically and validate it with Khandelwal's experimental data [22]. Finally, combining with simulation results of this model, we discuss the effects of the different parameters on the electrical properties of FD SG SOI MOSFETs in detail.

Surface Potential Explicit Calculation Scheme
For FD SG SOI MOSFETs, a crystalline silicon (c-Si) film is deposited on a BOX film, as shown in Figure 1. The x-axis is perpendicular to the plane of gate, the carrier transport occurs along the y-axis, and the z-axis is set parallel to the structural confinement direction. In addition, t ox and t si are gate oxide and silicon body thicknesses, respectively. Following the gradual channel approximation and neglecting the whole concentration, we can simply write the Poisson's equation as: Here, ϕ is the electrostatic potential as a function of the variable x, the free charge density is demonstrated where V t is the thermal voltage (kT/q), k is the Boltzmann constant, T is the absolute temperature, q is the magnitude of electronic charge, ε si is the dielectric permittivity of silicon, n 0 is expressed as n 0 = N a exp −2V f p /V t , V ch is the channel potential, V fp is the quasi-Femi potential, and the doping concentration is symbolled by N a . According to Figure 1, there are three boundary conditions for (1), i.e., ϕ s is the surface potential with ϕ s = ϕ(t si ), ϕ b is the back-channel potential with ϕ b = ϕ(0), and (dϕ/dx) x=0 = 0.
complicated equation about the position of the minimum back-channel potential. M. Miura-Mattausch et al. [18] also proposed an analytical I-V model of FD SG SOI MOSFETs based on a completely potential-based description solving the Poisson's equation iteratively together with additional equations. Here, numerical computation reduced the calculation efficiency. W. Wu et al. [19] and Y. S. Yu et al. [20] gave surface-potential-based analytical I-V models in which smoothing functions are employed. In addition. J. Huang et al. [21] described a DC model of FD poly-Si TFTs based on the assumption of B-S potential relation. Because of computation complexity, they gave up deriving B-S potential relation, leading to low computation accuracy.
In this paper, we propose a surface-potential-based analytical I-V model of FD SG SOI MOSFETs. An explicit solution of surface potential in FD SG SOI MOSFETs is solved from the 1-D Poisson's equation and derivation of B-S potential coupling relation. This surface potential calculation scheme has high computation accuracy and efficiency, which is verified by numerical techniques. Subsequently, based on the surface potential, we present the drain current analytically and validate it with Khandelwal's experimental data [22]. Finally, combining with simulation results of this model, we discuss the effects of the different parameters on the electrical properties of FD SG SOI MOSFETs in detail.

Surface Potential Explicit Calculation Scheme
For FD SG SOI MOSFETs, a crystalline silicon (c-Si) film is deposited on a BOX film, as shown in Figure 1. The x-axis is perpendicular to the plane of gate, the carrier transport occurs along the y-axis, and the z-axis is set parallel to the structural confinement direction. In addition, tox and tsi are gate oxide and silicon body thicknesses, respectively. Following the gradual channel approximation and neglecting the whole concentration, we can simply write the Poisson's equation as: Here, φ is the electrostatic potential as a function of the variable x, the free charge density is demonstrated as − ⁄ where Vt is the thermal voltage (kT/q), k is the Boltzmann constant, T is the absolute temperature, q is the magnitude of electronic charge, εsi is the dielectric permittivity of silicon, n0 is expressed as = −2 ⁄ , Vch is the channel potential, Vfp is the quasi-Femi potential, and the doping concentration is symbolled by Na. According to Figure 1, there are three boundary conditions for (1), i.e., φs is the surface potential with φs = φ(tsi), φb is the back-channel potential with φb = φ(0), and (dφ/dx)x=0 = 0. It is noted that the c-Si film thickness of SOI MOSFETs comes into a sub-nanometer (<100 nm) scale so that the devices work in the FD mode rather than the PD mode of the bulk MOSFETs. From device structure aspect, the sub-nanometer film on BOX results in the strong back-to-surface (B-S) potential coupling effect, implied by the boundary condition φb = φ(0) for (1). Here, φb cannot be set as a constant equating to Vch, actually it is a function as φs according to φs = φ(tsi). This function is the B-S potential coupling relation, which is to be derived as follows.  It is noted that the c-Si film thickness of SOI MOSFETs comes into a sub-nanometer (<100 nm) scale so that the devices work in the FD mode rather than the PD mode of the bulk MOSFETs. From device structure aspect, the sub-nanometer film on BOX results in the strong back-to-surface (B-S) potential coupling effect, implied by the boundary condition ϕ b = ϕ(0) for (1). Here, ϕ b cannot be set as a constant equating to V ch , actually it is a function as ϕ s according to ϕ s = ϕ(t si ). This function is the B-S potential coupling relation, which is to be derived as follows. For FD SG SOI MOSFETs, the channel layer is usually in the lightly or moderately doped case, i.e., free charge density is far larger than N a , yielding: We can observe that the mathematical form of (1) is relatively complicated because of the inclusion of an exponent term and a constant term in the right-hand side (RSH) of the equation, so that a solution of ϕ cannot be solved generally up to now. However, (2) retains the clear physical meaning and becomes the simplification of (1) to help us analytically derive the B-S potential coupling relation. We integrated (2) twice to obtain this relation as: Here, L D is the Debye length with L D = (ε si V t /2qn 0 ) 1/2 .
Using the Gauss's law, the relation d (1), we can obtain the implicit function of ϕ s as: If ϕ b is set as a constant with ϕ b = V ch , then (4) degenerates to be only suitable for PD MOSFETs, i.e., In the PD mode, we can solve (5) only to get ϕ s . However, in the FD mode, we should analytically solve the equation set of (3) and (4) to get the expressions of ϕ s and ϕ b . Obviously, there is much more computation complexity in the FD mode compared with the PD mode. Substituting (3) into (4), we can solve an explicit solution of ϕ b as: where β is symbolled as β = , r is the nature parameter with r = ε si t ox ε ox t si , and W 0 is the Lambert W function [23], which is the solution of W 0 (x)exp[W 0 (x)] = x. Furthermore, substituting (6) into (4), we can derive the explicit solution of ϕ s as: Here, λ is the bulk factor with λ = 2qε si n 0 /V t C 2 ox , D can be considered as the impact fact describing the B-S potential coupling effect in FD SG SOI MOSFETs with D = sin 2 β + N a cos 2 βln(sec 2 β)/4n 0 L 2 D β 2 , and ω is the Schroder series [24] used to improve the accuracy of the explicit solution of ϕ s with ω = −(y/y )/(1 − 0.5yy /y /y ). Here, , and y' and y" are the first and the second derivatives of y versus ϕ s , respectively.
We compare ϕ s of our scheme with that of the numerical method and show the results in Figures 2  and 3. We observe that good agreements are obtained and computational efficiency of (7) is seven times that of the numerical method, as shown in Figure 2. Moreover, we analyze the absolute errors of ϕ s in the different cases compared with the numerical results of (4) in Figure 3. First of all, the maximum errors of ϕ s between (7) and the numerical results are less than 10 -7 V. Then, the models of PD MOSFETs, i.e., (5), cannot be adopted into FD SOI MOSFETs and errors are up to 0.01V, because ϕ b cannot be set as a constant in the FD mode. Lastly, in the process of computing ϕ s , N a should not be ignored even if in the lightly or moderately doped case, or else large errors woule be introduced into the models. the maximum errors of φs between (7) and the numerical results are less than 10 -7 V. Then, the models of PD MOSFETs, i.e., (5), cannot be adopted into FD SOI MOSFETs and errors are up to 0.01V, because φb cannot be set as a constant in the FD mode. Lastly, in the process of computing φs, Na should not be ignored even if in the lightly or moderately doped case, or else large errors woule be introduced into the models.   the maximum errors of φs between (7) and the numerical results are less than 10 -7 V. Then, the models of PD MOSFETs, i.e., (5), cannot be adopted into FD SOI MOSFETs and errors are up to 0.01V, because φb cannot be set as a constant in the FD mode. Lastly, in the process of computing φs, Na should not be ignored even if in the lightly or moderately doped case, or else large errors woule be introduced into the models.

Analytical I-V Model
Considering the single-gate structure of the devices, the charge-sheet model (CSM) [25] derived by Brews can be adopted to derive the drain current including the drift and diffusion components, i.e., I ds1 and I ds2 , respectively. Based on the CSM and the solution of ϕ s , we get the drain current I ds as: Here, ϕ ss and ϕ sd are solutions of ϕ s corresponding to V ch = 0 and V ch = V ds , respectively, and Q i is the free charge density per unit area, which can be derived by using the Gauss's law at the interface between oxide and channel layers, yielding: In (8), µ is a typical set of universal effective charge mobility [26], including acoustical phonon [27] and surface roughness [28] scattering of the inversion layer carriers influenced from the normal field, i.e., where µ 0 is the maximum extracted value of the mobility at a given doping concentration, and θ 1 and θ 2 are degeneration parameters introduced by phonon scattering and surface-roughness scattering due to V gs . Substituting (9) and (10) into (8), we can analytically solve the expression of I ds as: Furthermore, we match the results of (11) with Khandelwal's experimental data [22] required from ultrathin-body SOI MOSFETs in the cases of long-and short-channels. In [22], the ultrathin-body SOI MOSFETs were manufactured, with a silicon body thickness of 8 nm and gate oxide thickness of 1.2 nm, respectively. For long-channel devices, the length of channel is 11 µm. For short-channel devices, the length of channel is 30 nm. The parameters used in the simulations are listed in Table 1. As shown in Figures 7-10, we can observe that such a model can give a consistent solution for both transfer and output characteristics. It is noted that, for short-channel devices, channel-length modulation (CLM) is considered by using "effective drain-source voltage" [29] in our I-V model, i.e., In (12), the parameter a is a transition factor deciding shift from the drain-to-source voltage V ds to the effective drain-source voltage V dseff , and V dsat is an extracted saturation voltage parameter. In the process of the calculation, we can substitute V dseff for V ch in (6) and (7) to make the model include CLM, which is equivalent with pinch-off behavior or velocity saturation. In Figures 7 and 8, we compare the model with Khandelwal's experimental data [22] for I ds -V gs and I ds -V ds characteristics in the long-channel device with 11 µm, which does not have a significant presence of channel-length modulation (CLM) in its characteristics. The excellent agreement between the model and the experimental data validates the core drain current model for long-channel devices. In Figures 9 and 10, our model is evaluated for short-channel effects by comparing I ds -V gs and I ds -V ds characteristics against Khandelwal's experimental data [22] for a short-channel device with L = 30 nm, which also demonstrate good model accuracy. The presence of CLM is apparent from Khandelwal's experimental data [22] of output conductance ( Figure 10) in this device. The reason why our proposed model can still capture these phenomena quite well is that we introduce "effective drain-source voltage" to describe CLM. According to the transfer characteristics shown in Figures 7 and 9, we can observe that short channel effects lead to subthreshold property degradation and a larger leakage current. According to output characteristics shown in Figures 8 and 10, we can observe that short channel effects result in obvious CLM or velocity saturation.

Value in Figures 4 and 5
Value in Figures 6  and 7 Value in Figure 8 Value in Figure 9 Value in Figure  10 Na (cm −3 ) 1 × 10 12 1.08 × 10 11 1 × 10 13 1 × 10 13 1 × 10 12 , 1 × 10 14 , 1 × 10 16 tox (nm) 1.     introduce "effective drain-source voltage" to describe CLM. According to the transfer characteristics shown in Figures 4 and 6, we can observe that short channel effects lead to subthreshold property degradation and a larger leakage current. According to output characteristics shown in Figures 5  and 7, we can observe that short channel effects result in obvious CLM or velocity saturation.

Discussion
In this section, we give some discussions about surface potential and drain current properties influenced by the structure parameters and the doping concentration of full-depletion single-gate SOI MOSFETs, including tox, tsi, and Na. The parameters used in the simulations are listed in Table 1. We analyze the effect from the single variable by using our model as follows. 1. The thickness tox of dielectric between gate and channel rightly determines the ability of

Discussion
In this section, we give some discussions about surface potential and drain current properties influenced by the structure parameters and the doping concentration of full-depletion single-gate SOI MOSFETs, including t ox , t si , and N a . The parameters used in the simulations are listed in Table 1. We analyze the effect from the single variable by using our model as follows.

1.
The thickness t ox of dielectric between gate and channel rightly determines the ability of inducing charges, particularly for the strong inversion region, as shown in Figure 4. We can observe that ϕ s increases as t ox decreases. Thin t ox leads to larger C ox , and then, according to the Gauss's law, many more free charges are introduced in the strong inversion region. It means that larger ϕ s and I ds can be obtained in the channel.

2.
The thickness t si of the channel film can influence ϕ b but not ϕ s . According to Figure 5, t si is larger and ϕ b becomes larger. It is implied by the simplified Poisson's equation (1) only including the doping concentration. Simultaneously, I ds is affected by t si lightly, because the free charges in the inversion layers are confined to a very thin layer with the order of 10-100Å [30]. That is also shown in Figure 5, graphed by our model.

3.
Finally, we can observe from Figure 6 that ϕ s , ϕ b , and I ds are in positive correlation with the doping concentration N a , because N a directly decides the value of the free charge density.

Conclusions
In this paper, we provided a surface-potential-based analytical I-V model for full-depletion single-gate silicon-on-insulator MOSFETs with lightly or moderately doped channels. Based on deriving analytically the back-to-surface potential coupling relation, we solved the explicit solution of the implicit surface potential function by using the Lambert W function, and matched this solution with the numerical iteration method. Considering single-gate structure and ultrathin channel film, the drain current was derived analytically on the basis of the charge sheet model, and good agreements with experimental data were obtained. Finally, we gave the discussions about influences of the structure parameters and the doping concentration on the electrostatic properties of the devices. As a result, accurate simulation results demonstrate that our model can predict electrostatic properties of full-depletion single-gate silicon-on-insulator MOSFETs.