Evidence of Limitations of the Transconductance-to-Drain-Current Method ( g m / I d ) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors

: The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three ﬁgures of merit used for the method, and we conclude for the ﬁrst time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramiﬁcations on the ﬁeld of process modeling, simulation and circuit design.


Introduction
The transconductance-to-drain-current method (widely known also as the g m /I d method) is a broadly used tool for calculating CMOS transistor dimensions starting from specifications at the analog circuit (or system) level. Its broad usage and effectiveness are because it provides a unified sizing procedure for CMOS transistors for analog low-power and radiofrequency applications (from the strong to weak inversion regions). It has proven to be a method that is accurate and technology independent. It uses the curve of the transconductance (g m ) over the bias drain current (I d ) ratio g m /I d relationship (also named transconductor efficiency) versus the normalized bias current I d /(W/L) (W and L are the transistor width and length respectively). The set of curves g m /I d generated for a particular technology are continuous for the various regions of operation. The method has been well explained and detailed in [1][2][3].
Past studies have demonstrated the effectiveness of this sizing methodology. It is accurate, is technology-independent and can be applied to more advanced CMOS technology, allowing the designer to implement current-independent sizing designs. The method is also adapted and can be used for a short channel length of L = 180 nm [4,5] and below [6]. Additionally, it is essential to emphasize that in the literature, it has been reported that many circuit designs based on the g m /I d design flow have achieved the desired specifications (it has been verified by simulations and measurements). All used design flows have the common factor of being based on width-independent parameters that we describe in the next section, and which are the core characteristics of the method that we assessed in this study.
Currently, technology downscaling is a consolidated process in the semiconductor industry that has triggered considerable interest regarding addressing novel analog circuit design methods. That is motivated by reported studies that have argued regarding the difficult or non-viability of scaling CMOS technologies to analog designs (for instance in [7]). However, the Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-on-Insulator (UTBB FD-SOI) has been reported as a promising technology to continue the scaling of silicon metal-oxide semiconductor field-effect transistors [8]. In this framework, the question that arises is whether the g m /I d method is still useful in the case of UTBB FD-SOI 28 nm industrial technology. Alternatively, better stated: is the method complete and does it have the capability to handle changes in technology that involve extreme downscaling? This manuscript aims to address this question and provide early conclusions and suggestions for the circuit designers' community.
In the recent reference [9] (Appendix 3) is explored the layout dependence of the g m /I d design method for the 65 nm-CMOS technology. The mentioned conclusion is that designers must decide on a suitable number of finger width and number of fingers to assume the g m /I d design method to be the right design approach. Our work reinforces such considerations about layout dependent effects on the device under study. As the deep-scaled FD-SOI devices usage becomes widespread to continue CMOS scaling, our work heads up to designers who indeed will find an inconsistent result between the performance of their built circuits by means of the transconductance-to-drain-current theoretical approach and the performance obtained by simulations using the technology model-card given by the vendor (or foundry), that is assumed to be reliable. The ramifications of this work are important.

Compound Transistor Principle for the g m /I d Method
The g m /I d method (Section 2 of [3]) is based on the assumption that the curve of g m /I d versus I N (normalized bias current I N = I d /(W/L)) is independent of the MOS transistor size (or formally speaking, the W/L factor) and drain current biasing. The main conclusion, among others, is that g m /I d depends on g m /g ds which is width-independent. Let us provide better insight into this relation by explaining the superposition principle. For this we reproduced the compound transistor scheme that is used as the key hypothesis to support the method ( Figure 1). To explain the DC characteristics of the arrangements shown in Figure 1, for all cases, we used the same V G , V D , V BPn , W and L values for UTBB FD-SOI transistors (assumed to be ideal and without mismatched geometry). Therefore, case (b) is a compound of transistors of case (a), whereas case (c) is a single one but has a doubled width, W. For parallel transistors, case (b) can be treated as one merged transistor with a width of 2 W. Because the SOI transistor equations predict a bias current value that is proportional to W (ref. [10,11] and also because the PDK model of our technology uses charge-surface potentials, where the threshold voltage V TH does not depend on W), it is easy to conclude that all transistor cases are biased on the same g m /I d (see the detailed explanation in [5]). Therefore, on the basis of the previous geometrical argumentation of the compound transistor scheme when using the g m /I d method, and because of the transistor width (W) proportionality of some of their features, the following assumptions, which are the core figures of merit of the g m /I d method, are stated: 1. The unity gain frequency f T = 1 2π g m /C gg is expected to be independent of W, where C gg = C gs + C gb + C gd is the total gate capacitance [5]. 2. The intrinsic gain, g m /g ds is expected to be independent of W [5]. 3. g m /g bs is expected to be independent of W [5].
Of course, for these last statements to hold, we need to ensure that the parallel compound transistor principle applies.

Methodology for Preliminary Assessment of the g m /I d Method
In this letter, rather than studying an overwhelming number of examples, we investigated UTBB FD-SOI 28 nm low-voltage-threshold nfet commercial technology, and the simulations were performed using Spectre [12] (using the tool Cadence [12]) with the vendor-provided PSP model-card that also uses intrinsec parasitic capacitances). This technology has a minimum transistor size of 30 nm gate length (L) and 80 nm gate width (W). First, utilizing simulations, we reviewed the compound transistor principle validity. We selected L = 180 nm for the study presented here because this gate channel length has been used and reported to be effective for CMOS circuits designs using the g m /I d method in many studies (for instance in [5]). Consequently, we maintained this transistor channel length value in our study for the sake of completeness and to better compare with other results. Subsequently, to verify if the figures of merit maintain their width-independence properties, as mentioned above, we obtained the following figures of merit via simulations to graph them versus W: f T = 1 2π g m /C gg , g m /g ds and g m /g bs . This was performed on one transistor with a fixed length and given bias voltages, by sweeping the gate-width using the following values: In the remaining parts of the manuscript, we discuss the simulations in the considered case of this study to assess the feasibility of this method. We mention in advance that no promising results were found.

Verification of the Compound Transistor Principle
The first test was to simulate the scenario of compound FD-SOI transistors biased at the same g m /I d , as depicted in Figure 1. For each case, we simulated a transistor size of W = 80 nm and L = 180 nm with V G = 0.5 V, V D = 1 V and V BPn = 0 V (for case (c) we use used a double width). The simulated bias current result is as follows: I 1 = 8.4328 µA, I 2 = 16.866 µA and I 3 = 16.4079 µA. However, for M 1 the resulting simulations showed: g m /I d = 13.8311 V −1 , for M 2 1 and M 2 2 the obtained result was g m /I d = 13.8311 V −1 and for M 3 we obtained g m /I d = 13.8331 V −1 .
Moreover, for M 1 we obtained g m = 116.636 µΩ −1 . For M 2 1 and M 2 2 we obtained g m = 116.636 µΩ −1 and for M 3 was g m = 226.973 µΩ −1 . We observed that there was a weak or reduced numerical difference between the I 2 value and I 3 (i.e., I 2 = 2I 1 but I 2 − I 3 = 0.458 µA).
We found that this result was not strong enough to argue that the presumption on which the original g m /I d method is based is no longer valid. Hence, we continued exploring the behavior of the three figures of merit to obtain more explicit evidence.

Results and Discussion
In this section, we describe three singles benchmark tests used to ensure the applicability of the g m /I d method. In particular, we were interested in verifying the width-independence of the figures of merit mentioned above. Simulations were rigorously verified and we analyzed the static behavior without the back-bias effect (we set V BPn = 0) to closely mimic the n-type CMOS transistor conditions and geometries that have been reported for using the g m /I d method. We then describe the following studies: 1. Figure 2 For discussion, we first mention the critical finding of the width-dependence shown in the figures. Parameters f t and g m /g bs , showed reduced variations, that were below 10%. However, it could not be ensured that the design methodology used for the circuit design was affected. Formally, it is not possible to guarantee robustness concerning such a slight variation in the numerical scheme that links transistors features and circuit-level performance during the design stage. From our point of view, this is a factor to be taken into account in the integrated circuit design flow. Another exciting result arise, which indicated that more detailed studies are required. In ref. [13], the authors showed f T independence from the gate finger width in 28 nm FD-SOI devices. Conversely, in our study, we showed the effects of the gate fingers in Figure 4. It is our opinion that the technology has not achieved maturity, and variations in the device built physical processes lead to controversial results.
The most significant proof of the width-dependence of the figure of merit g m /g ds is depicted in Figure 3, which showed an estimated variation above 70% and in Figure 4 (with gate fingers), with an estimated variation above 70% for the variation range of the considered W. The width-dependence effect is reduced when using reduced L values, employing L min .
On the other hand, from Figure 4 we observe certain plateau (or tendency to be a constant value) of the g m /g ds and g m /g bs parameters at the center of the figure, where the W/n f values lie into the range 0.1 µm and 0.15 µm. It witnesses the possible g m /I d method independence concerning layout configuration, more specifically regarding the finger width but not with W as primarily assumed.
By means of singles-case studies, we show that the method should be reformulated to take into account several effects that are currently not captured by the g m /I d method, principally the g m /g ds figure of merit.
Going back to Figure 1, we conclude that a device of 2W/L is not equivalent to two parallel devices of W/L ratio. It becomes more pronounced at deep sub-micron and very wide devices. Since by modifying W the extrinsic capacities values change, all extrinsic capacities have to be included in the gm/Id method. Therefore, the method may become a not treatable and challenging one, losing its desired "hand analysis" capability.

Example: Simple Design Case
To have a better insight into the problem treated in this work, we study the circuit shown in Figure 5: a common-source amplifier. Let see how its intrinsic-gain (i.e., gain without load, a figure of merit) changes due to W modifications at the same g m /I d biasing. The small-signal model predicts that the intrinsec-gain is equal to g m /g ds , and according with that Section 2 establishes, the g m /g ds parameter is a W-invariant for the g m /I d method.
We start the design using simulations with W = 720 nm (case 1 in Table 1).The size is then reduced by a factor of 3, two times, as well as the bias current, looking for a design with reduced current consumption without modifying the intrinsic-gain that is assumed to guaranteed by using the same g m /I d biasing (hypothesis explained in Section 2). Nevertheless, please observe that in Table 1 the g m /I d biasing remains quasi-invariant for the three cases, but the simulated intrinsic-gain not. It changed around 23% between cases 1 and 3. From the design point of view, it is not a slight variation.
Therefore, the intrinsic-gain is not W-invariant, and the g m /I d method could conduct to an erroneous design using the UTBB FD-SOI 28 nm low-voltage-threshold technology.  Table 1, (b) simulated intrinsec-gain for the design case 1 (AC response). The theoretical intrinsec-gain is equal to g m /g ds . Table 1. Case study: common-source amplifier, L = 80 nm, Figure 5.

Conclusions
This work showed numerically that the g m /I d method requires more generality and systematization before being applied to UTBB FD-SOI 28 nm devices and more scaled technologies.
Regarding the UTBB FD-SOI understanding and usage advances for analog design, in particular, for high-frequency applications, the g m /I d method should be handled carefully because the observed inaccurate predictions. These could be due to the extrinsic capacitances, parasitic resistances or side effects and these must be taken into account regarding the physical effects of fabrication process and in terms of the device's dynamic such as velocity saturation. There appears to be a large number of degrees of freedom and side effects in this technology that can not be ignored anymore (particularly finger partition and size), and the g m /I d method (intended for hand analysis) requires much more generalization. This would lead the g m /I d method unpractical or unmanageable so that advanced and optimal designs based on UTBB FD-SOI 28 nm low-voltage-threshold nfet must be performed by means of TCAD without assistance of reduced approaches like the g m /I d method.
This study is the starting point to address more issues regarding the g m /I d method due to these unexpected findings.