Simple and Accurate Model for the Propagation Delay in MCML Gates

Abstract

In this article, we develop a simple and accurate model for evaluating the propagation delay in MOS Current-Mode Logic (MCML) gates. The model describes the behavior of MCML gates in a linear fashion despite the circuits themselves being non-linear. Indeed, we demonstrate that a linear model can be used, provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model is validated through simulations of MCML universal gates designed using modern nanometer processes. The model forecasts simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm Fully-Depleted Silicon-On-Insulator (FD-SOI), respectively.

1. Introduction

Since the origin of the bipolar Current Mode Logic (CML) and later MOS Current-Mode Logic (MCML), having simple and accurate models of such logic gates has been a matter of interest, particularly with the aim of facilitating an efficient design from the very first steps.

Regarding the propagation delay (PD), the first works in the literature modeled this parameter as a linear combination of circuit time constants, whose weights were determined by sensitivity analysis [1,2,3]. Despite being accurate, the approach is not practical nor useful since the PD estimation in a CML inverter (i.e., the simplest gate) requires the extraction of more than 25 parameters through a large number of simulations. The number of parameters can be reduced, as reported in [4], but the proposed technique is not so effective and can be applied after simulations only.

At the beginning of the 1990s, in [5] the authors proposed a model based on the average branch current but, despite being simple, it was not sufficiently accurate. In the same year, the authors in [6] suggested a different methodology that has proved too complex and impractical. A few years later, some approaches based on the linearization of device models were introduced [7,8,9]. However, either they were difficult to use, especially in the preliminary phase of the pencil-and-paper design, as in [8], or they returned too high errors, thus losing their attractiveness to provide a model for simulation, as in [8,9]. Since the late 1990s and up to recent years, several digital gate models have been developed based on the small-signal representation of the transistor with an improved modeling of its parasitic capacitors, suitable for large signal swings. Such models covered both CML [10,11,12] and MCML gates [13,14,15,16]; they were proficiently used to optimize the design of standard CML and MCML gates [17,18,19,20], and, recently, were also used for advanced gates developed for very low-voltage environments [21,22,23,24].

MCML gates have been popular, and due to their very low switching noise, inherent robustness, and speed, they continue to be used in applications ranging from very high-speed embedded systems [25,26,27,28,29] to mixed-signal processing [30,31,32,33,34,35,36,37]. In this scenario, digital gate models with a good trade-off between simplicity and accuracy still remain a fundamental design tool for the designer.

Up to now, the aforementioned models of MCML gates, which rely on the small-signal representation of the transistor, are accurate for inverter gates, since the latter are inherently modeled with single-pole behavior [10,11,12,13,14,15,16]. On the other hand, current-mode gates with two inputs are more accurately modeled with a two-pole network. Thus, in this paper, we develop and validate a very simple model for the estimation of the PD in two-input MCML gates through the accurate representation with an equivalent two-pole network.

This paper is structured as follows. In Section 2, we review the propagation delay of an MCML inverter and discuss how a simple linear delay model can well describe the behavior of a nonlinear gate. In Section 3, we analyze the propagation delay of an MCML universal gate, propose a simple and effective linear model and present how to determine its equivalent small-signal parameters to well describe the nonlinear behavior of the gate. In Section 4, we validate the proposed linearized models by comparing the theoretical results with simulations of MCML inverters and universal gates designed using two nanometer CMOS processes (a 65-nm standard CMOS and a 28-nm FD-SOI). Finally, in Section 5, conclusions are drawn.

2. Review of the MCML Inverter Delay Model

The MCML inverter is shown in Figure 1. It is made up of a source coupled differential pair, M1–M2, biased by the constant current, $I_o$, provided by M0, and two PMOS devices, MP1–MP2, biased in the triode region, that act as a resistive load. $C_{o1}$ and $C_{o2}$ are the equivalent output capacitors and include both the self loading effect and the external load. The differential pair operates in a non-linear fashion by switching current $I_o$ either to MP1 or to MP2, depending on the differential input $v_X=v_{X1}-v_{X2}$.

When $v_X>0$, denoted as a high or ‘H’ state, current $I_o$ flows through MP1 and makes $v_{o1}=V_{DD}-\Delta V_o$, $v_{o2}=V_{DD}$ and $v_o=v_{o1}-v_{o2}=-\Delta V_o$, where $\Delta V_o$ is the logic swing that depends on $I_o$ and on the equivalent resistance of MP1. Conversely, when $v_X<0$, denoted as low or ‘L’ state, we obtain $v_o=\Delta V_o$. As we shall discuss below, although the logic gate is strongly nonlinear, we can still use a linear model provided that for each small-signal parameter we use, its average value was calculated between the two different logic states of the logic gate.

2.1. Propagation Delay

During the commutation, M1 and M2 can be considered as switches that connect the constant current $I_o$ to one output node and disconnect it from the other. Hence, we have a charging branch and a discharging one, respectively. Since the circuit is symmetrical, we can analyze one of the two commutations and apply the results to the other case. Hence, if we consider $v_X$ commuting from the ‘L’ to the ‘H’ state, assuming a linear model, we can describe the two branches as in Figure 2, where $g_{dp1}$ and $g_{dp2}$ are the equivalent drain-source conductances of MP1 and MP2, respectively (we neglect the resistive contribution observed at the drain terminals of M1 and M2 because one of the two transistors is off and the other is in a common-gate configuration with a high drain impedance).

Therefore, we can write for the time-domain evolution

$$\begin{array}{cc}\hfill v_{o1}\left(t\right)& =-\frac{I_o}{g_{dp}}\left[1-exp\left(-\frac{t}{{\tau }_o}\right)\right]\hfill \end{array}$$

(1a)

$$\begin{array}{cc}\hfill v_{o2}\left(t\right)& =-\frac{I_o}{g_{dp}}exp\left(-\frac{t}{{\tau }_o}\right)\hfill \end{array}$$

(1b)

where $g_{dp}=g_{dp1}=g_{dp2}$, $C_o=C_{o1}=C_{o2}$, due to the symmetrical property of the inverter, ${\tau }_o=C_o/g_{dp}$ and $\Delta V_o=I_o/g_{dp}$ under the linear model assumption.

Considering both the input commutations, the differential output voltage, $v_o$, results

$$v_o\left(t\right)=\pm \frac{I_o}{g_{dp}}\left[1-2exp\left(-\frac{t}{{\tau }_o}\right)\right]$$

(2)

The PD is the time interval between the time the input crosses the 50% of the logic swing until the time the output crosses the same voltage level (50%). Assuming an ideal input step, the PD is found by solving $v_o\left(t_{PD}\right)=0$, that is the well-known

$$t_{PD}={\tau }_{o}ln\left(2\right)$$

(3)

2.2. Evaluating the Parameters of the Delay Model

The limits of the model in (3) are in the ideal input step and in the linearity assumptions. The input step, however, can be considered as ideal if the logic gate is driven by a logic gate of a similar size. Indeed, as demonstrated in [38,39] and shown in Figure 3, if we assume the input signal as a linear ramp with rise time, T, as long as $T\sim {\tau }_o$, the error between the actual PD and the value estimated by (3) remains lower than 20%. Conversely, (3) fails to predict the PD if the rise time of the input step is significant (i.e., $T\gg {\tau }_o$), as in the case of a large logic gate driven by a minimum size one. However, this case is generally avoided in practical design; in the vast majority of cases, we can assume the input step as ideal.

Relationship (3) requires evaluating the time constant, ${\tau }_o=C_o/g_{dp}$, where $C_o$ and $g_{dp}$ should be small-signal parameters. In our case, the inverter is a nonlinear circuit and works with large signal variations; thus, we need to specify how $C_o$ and $g_{dp}$ are to be evaluated. In the past, the linearization technique in [40] was adopted to evaluate resistive or capacitive contributions from the large-signal models of the devices [11,12,13,14]. However, the approach required the knowledge of current-to-voltage or charge-to-voltage analytical equations, which are hardly manageable in modern nanometer CMOS processes. To overcome this issue and to make the model as simple as possibile, we have chosen to use the average of the small-signal values computed over the two bias conditions of the logic gate, that is, the ‘H’ state and the ‘L’ state. Hence, we write

$$\begin{array}{cc}\hfill C_o& =\frac{C_{o1}^{\left(\mathrm{H}\right)}+C_{o2}^{\left(\mathrm{L}\right)}}{2}=\frac{C_{o2}^{\left(\mathrm{H}\right)}+C_{o1}^{\left(\mathrm{L}\right)}}{2}\hfill \end{array}$$

(4a)

$$\begin{array}{cc}\hfill g_{dp}& =\frac{g_{dp1}^{\left(\mathrm{H}\right)}+g_{dp2}^{\left(\mathrm{L}\right)}}{2}=\frac{g_{dp2}^{\left(\mathrm{H}\right)}+g_{dp1}^{\left(\mathrm{L}\right)}}{2}\hfill \end{array}$$

(4b)

Observe that, since the logic gate is symmetrical, $C_{o1}^{\left(\mathrm{H}\right)}=C_{o2}^{\left(\mathrm{H}\right)}$ and $C_{o1}^{\left(\mathrm{L}\right)}=C_{o2}^{\left(\mathrm{L}\right)}$.

As we shall validate in Section 4, these simplifications are very powerful and effective since they allow a nonlinear system to be treated as if it were linear, provided that its equivalent small-signal parameters are evaluated by their average in the two logic states.

3. MCML Universal Gate Delay Model

The MCML universal gate is shown in Figure 4. It is made up of two cascaded source-coupled differential pairs. The lower differential pair, M1–M2, processes the input $v_X=v_{X1}-v_{X2}$, and the upper differential pair, M3–M4, processes the input $v_Y=v_{Y1}-v_{Y2}$. PMOS devices, MP1–MP2, are biased in the triode region and act as a resistive load. Transistor M0 provides the constant current, $I_o$, that biases the logic gate.

The conventional MCML universal gate is designed without transistor M5, that is, with the drain terminal of M2 directly connected to the output node, $V_{o2}$. This results in a highly unbalanced and asymmetrical logic gate. In this improved topology in Figure 4, transistor M5 is used to better balance the logic gate so that M1–M2 are subject to the same drain-source voltage. This makes the circuit more symmetrical and enhances the logic gate’s performance in high-speed applications, as reported in [15]. In the figure, $C_{o1}$ and $C_{o2}$ are the equivalent output capacitors and include both the self loading effect and the external load. $C_{a1}$ and $C_{a2}$ are the equivalent capacitors in the internal nodes of the universal gate. In general, since the universal gate is not perfectly symmetrical, we have $C_{o1}\ne C_{o2}$ and $C_{a1}\ne C_{a2}$.

With a proper combination of its inputs and output, the logic gate can realize any two-input OR/NOR/AND/NAND logic function. Independently of the logic function, in our discussion we say that M1–M2 (M3–M4) is in the ‘H’ state when $v_X>0$ ($v_Y>0$). Conversely, M1–M2 (M3–M4) is in the ‘L’ state when $v_X<0$ ($v_Y<0$).

The MCML universal gate has 12 possible transitions but, as reported in

Table 1. Transitions of the MCML universal gate.

Transition	${\mathit{v}}_{\mathit{X}}$	${\mathit{v}}_{\mathit{Y}}$	${\mathit{v}}_{\mathit{o}}$	Transition	${\mathit{v}}_{\mathit{X}}$	${\mathit{v}}_{\mathit{Y}}$	${\mathit{v}}_{\mathit{o}}$
T1 (LL → LH)	L	↑	H	T7 (HH → HL)	H	↓	↑
T2 (LH → LL)	L	↓	H	T8 (HL → HH)	H	↑	↓
T3 (LL → HL)	↑	L	H	T9 (HH → LH)	↓	H	↑
T4 (HL → LL)	↓	L	H	T10 (LH → HH)	↑	H	↓
T5 (LH → HL)	↑	↓	H	T11 (HH → LL)	↓	↓	↑
T6 (HL → LH)	↓	↑	H	T12 (LL → HH)	↑	↑	↓

, only 6 of them (T7–T12) commute the output either in the rising edge (↑) or in the falling edge (↓).

In transitions T7/T8, transistor M1 remains on and M2 remains off. The commutation affects the upper differential pair, only, and the circuit behaves as a MCML inverter with a single equivalent pole at the output nodes. These transitions are not critical because, due to the single-pole behavior, they are the fastest of the universal gate.

In transitions T9/T10, transistor M4 remains off and M3 remains on. It is now the lower differential pair that switches the bias current $I_o$ to one of the output nodes. In the process, transistors M3 and M5 act as common-gate stages. These transitions are critical since they are slower than T7/T8 because the common-gate stage introduces an extra pole.

In transitions T11/T12, no current flows through transistor M4. Indeed, when $V_{Y2}$ is low, current $I_o$ reaches MP1 through transistors M1 and M3. Conversely, when $V_{Y2}$ is high, current $I_o$ reaches MP2 through transistors M2 and M5. Since these transitions are very similar to those in T9/T10, we shall limit our analysis to these last two cases only.

3.1. Simplified Analysis of Transitions T9/T10

During transitions T9/T10, the MCML universal gate is represented as in Figure 5. Transistors M1 and M2 are considered as switches that connect the constant current $I_o$ to the charging branch and disconnect it from the other, namely the discharging branch.

For a preliminary analysis, we assume the circuit to be symmetrical so that the results found for one of the two transitions can easily be applied to the other. We shall discuss below how the results change in the asymmetrical logic gate. Moreover, we assume also a linear model so that the branches of the universal gate are represented as in Figure 6, where $C_a=C_{a1}=C_{a2}$, $C_o=C_{o1}=C_{o2}$, $g_m=g_{m3}=g_{m5}$, and $g_{dp}=g_{dp1}=g_{dp2}$ is the equivalent drain-source conductance of PMOS transistors (we neglect the resistive contribution observed at the drain terminals of M3 and M5 because both are in common-gate configurations with high drain impedances). The charging branch of Figure 5 is modeled by Figure 6a, where current $I_o$ is a step input. The discharging branch is modeled by Figure 6b, where the initial conditions depend on the voltage swings $\Delta V_a=I_o/g_m$ and $\Delta V_o=I_o/g_{dp}$, set by the steady-state before commutation.

In the Laplace domain, we have for the charging branch

$$\begin{array}{cc}\hfill V_{a,c}\left(s\right)& =-\frac{1}{s\left(1+s{\tau }_a\right)}\frac{I_o}{g_m}\hfill \end{array}$$

(5a)

$$\begin{array}{cc}\hfill V_{o,c}\left(s\right)& =-\frac{1}{s\left(1+s{\tau }_a\right)\left(1+s{\tau }_o\right)}\frac{I_o}{g_{dp}}\hfill \end{array}$$

(5b)

and, for the discharging branch

$$\begin{array}{cc}\hfill V_{a,d}\left(s\right)& =-\frac{{\tau }_a}{1+s{\tau }_a}\frac{I_o}{g_m}\hfill \end{array}$$

(6a)

$$\begin{array}{cc}\hfill V_{o,d}\left(s\right)& =-\frac{s{\tau }_a{\tau }_o+{\tau }_a+{\tau }_o}{\left(1+s{\tau }_a\right)\left(1+s{\tau }_o\right)}\frac{I_o}{g_{dp}}\hfill \end{array}$$

(6b)

${\tau }_a=C_a/g_m$ and ${\tau }_o=C_o/g_{dp}$ being the time constants related to the inner node and the output one.

At the output nodes, the corresponding time-domain equations are

$$\begin{array}{cc}\hfill v_{o,c}\left(t\right)& =-\frac{I_o}{g_{dp}}\left[1+\frac{exp\left(-\frac{t}{{\tau }_a}\right)}{{\tau }_o/{\tau }_a-1}+\frac{exp\left(-\frac{t}{{\tau }_o}\right)}{{\tau }_a/{\tau }_o-1}\right]\hfill \end{array}$$

(7a)

$$\begin{array}{cc}\hfill v_{o,d}\left(t\right)& =-\frac{I_o}{g_{dp}}\left[-\frac{exp\left(-\frac{t}{{\tau }_a}\right)}{{\tau }_o/{\tau }_a-1}-\frac{exp\left(-\frac{t}{{\tau }_o}\right)}{{\tau }_a/{\tau }_o-1}\right]\hfill \end{array}$$

(7b)

so that the differential output results

$$v_o\left(t\right)=\pm \left[v_{o,d}\left(t\right)-v_{o,c}\left(t\right)\right]=\pm \frac{I_o}{g_{dp}}\left[1+\frac{2exp\left(-\frac{t}{{\tau }_a}\right)}{{\tau }_o/{\tau }_a-1}+\frac{2exp\left(-\frac{t}{{\tau }_o}\right)}{{\tau }_a/{\tau }_o-1}\right]$$

(8)

where the ‘+’ sign holds for transition T9 and the ‘−’ sign for transition T10.

3.2. Propagation Delay

The PD is obtained by solving $v_o\left(t_{PD}\right)=0$ but no closed form solution exists for this equation. To find an approximate solution, assuming ${\tau }_o>{\tau }_a$, we normalize the variables as

$$\left\{\begin{array}{cc}\hfill y& =\pm v_o{g}_{dp}/I_o\hfill \\ \hfill x& =t/{\tau }_a\hfill \\ \hfill k& ={\tau }_o/{\tau }_a>1\hfill \end{array}\right.$$

(9)

and rewrite (8) as

$$y\left(x\right)=1+\frac{2exp\left(-x\right)}{k-1}+\frac{2exp\left(-x/k\right)}{1/k-1}$$

(10)

Using Matlab, we find the normalized propagation delay by solving $y\left(x_{PD}\right)=0$ for different values of $k>1$. The plot of $x_{PD}$ versus k is shown in Figure 7 and reveals a quasi-linear behavior. A fitting procedure led to the empirical solution

$$x_{PD}=0.690\times k+1.090\approx kln\left(2\right)+ln\left(3\right)$$

(11)

where the error of the last expression is less than 5.7%.

Using (9) to denormalize k and $x_{PD}$ leads to

$$t_{PD}={\tau }_{o}ln\left(2\right)+{\tau }_{a}ln\left(3\right)$$

(12)

Observe that, if ${\tau }_a>{\tau }_o$ then (12) turns into $t_{PD}={\tau }_{a}ln\left(2\right)+{\tau }_{o}ln\left(3\right)$.

3.3. Effect of the Asymmetry

The presence of transistor M4 in Figure 4 implies $C_{o1}\ne C_{o2}$ and $C_{a1}\ne C_{a2}$. This means that the time constants of the left branch differ from the corresponding time constants of the right branch.

To analyze how the circuit behaves with asymmetrical time constants, we evaluate the signals at the output nodes considering ${\tau }_{a1}\ne {\tau }_{a2}$ and ${\tau }_{o1}\ne {\tau }_{o2}$. During transition T10, the output signals are

$$\begin{array}{cc}\hfill v_{o1}\left(t\right)& =-\frac{I_o}{g_{dp}}\left[1+\frac{exp\left(-\frac{t}{{\tau }_{a1}}\right)}{{\tau }_{o1}/{\tau }_{a1}-1}+\frac{exp\left(-\frac{t}{{\tau }_{o1}}\right)}{{\tau }_{a1}/{\tau }_{o1}-1}\right]\hfill \end{array}$$

(13a)

$$\begin{array}{cc}\hfill v_{o2}\left(t\right)& =-\frac{I_o}{g_{dp}}\left[-\frac{exp\left(-\frac{t}{{\tau }_{a2}}\right)}{{\tau }_{o2}/{\tau }_{a2}-1}-\frac{exp\left(-\frac{t}{{\tau }_{o2}}\right)}{{\tau }_{a2}/{\tau }_{o2}-1}\right]\hfill \end{array}$$

(13b)

Observe that the output signals during transition T9 can be obtained by simply exchanging the subscript 1 with 2 in (13). Subtracting (13a) to (13b), we obtain the output voltage as

$$v_o\left(t\right)=\pm \frac{I_o}{g_{dp}}\left[1+H_a\left(t\right)+H_o\left(t\right)\right]$$

(14)

where the ‘+’ sign holds for transition T9, the ‘−’ sign for transition T10 and where

$$\begin{array}{cc}\hfill H_a\left(t\right)& =\frac{exp\left(-\frac{t}{{\tau }_{a1}}\right)}{{\tau }_{o1}/{\tau }_{a1}-1}+\frac{exp\left(-\frac{t}{{\tau }_{a2}}\right)}{{\tau }_{o2}/{\tau }_{a2}-1}\hfill \end{array}$$

(15a)

$$\begin{array}{cc}\hfill H_o\left(t\right)& =\frac{exp\left(-\frac{t}{{\tau }_{o1}}\right)}{{\tau }_{a1}/{\tau }_{o1}-1}+\frac{exp\left(-\frac{t}{{\tau }_{o2}}\right)}{{\tau }_{a2}/{\tau }_{o2}-1}\hfill \end{array}$$

(15b)

As demonstrated in Appendix A, $H_a\left(t\right)$ and $H_o\left(t\right)$ can be simplified as in (A3) and (A5) and the output voltage reported in (14) turns into (8) where

$$\begin{array}{c}\hfill C_a=\frac{C_{a1}+C_{a2}}{2}\Rightarrow {\tau }_a=\frac{{\tau }_{a1}+{\tau }_{a2}}{2}=\frac{C_a}{g_m}\end{array}$$

(16a)

$$\begin{array}{c}\hfill C_o=\frac{C_{o1}+C_{o2}}{2}\Rightarrow {\tau }_o=\frac{{\tau }_{o1}+{\tau }_{o2}}{2}=\frac{C_o}{g_{dp}}\end{array}$$

(16b)

It is worth emphasizing that, although the MCML universal gate is asymmetrical, it behaves as if it were symmetrical as long as all capacitive contributions are averaged between the two branches of the logic gate.

As a final remark, due to the above discussion, the PD is expressed by (12) where the time constants are evaluated as in (16).

3.4. Evaluating the Parameters of the Delay Model

As for the MCML inverter, this delay model is also based on the linearity assumption of the logic gate. Indeed, (12) requires the evaluation of the time constants, ${\tau }_o=C_o/g_{dp}$ and ${\tau }_a=C_a/gm$, where $C_o$, $C_a$, $g_{dp}$, and $g_m$ should be small-signal parameters. However, since the universal gate works with large signals, we cannot use any small-signal parameter evaluated in a single bias point.

To maintain the delay model as simple as possibile, we use the average value over the two bias conditions that the logic gate assumes during transitions T9/T10. In particular, referring to Figure 5, and maintaining M3–M4 in the ‘H’ state, the first bias point refers to M1–M2 in the ‘H’ state and the second bias point refers to M1–M2 in the ‘L’ state. Therefore, for transconductance $g_m$ and conductance $g_{dp}$, we consider

$$\begin{array}{cc}\hfill g_m& =\frac{g_{m3}^{\left(\mathrm{H}\right)}+g_{m3}^{\left(\mathrm{L}\right)}}{2}=\frac{g_{m5}^{\left(\mathrm{H}\right)}+g_{m5}^{\left(\mathrm{L}\right)}}{2}\hfill \end{array}$$

(17a)

$$\begin{array}{cc}\hfill g_{dp}& =\frac{g_{d1}^{\left(\mathrm{H}\right)}+g_{d1}^{\left(\mathrm{L}\right)}}{2}=\frac{g_{d2}^{\left(\mathrm{H}\right)}+g_{d2}^{\left(\mathrm{L}\right)}}{2}\hfill \end{array}$$

(17b)

Observe that the universal gate is symmetrical for the transistors’ transconductances and conductances so that $g_{m3}^{\left(\mathrm{H},\mathrm{L}\right)}=g_{m5}^{\left(\mathrm{L},\mathrm{H}\right)}$ and $g_{dp1}^{\left(\mathrm{H},\mathrm{L}\right)}=g_{dp2}^{\left(\mathrm{L},\mathrm{H}\right)}$.

Referring to the capacitive contributions, we have to average the values between the left and the right side of the universal gate as well as the values between the ‘H’ and the ‘L’ states. Therefore, we have

$$\begin{array}{cc}\hfill C_a& =\frac{\frac{C_{a1}^{\left(\mathrm{H}\right)}+C_{a2}^{\left(\mathrm{H}\right)}}{2}+\frac{C_{a1}^{\left(L\right)}+C_{a2}^{\left(\mathrm{L}\right)}}{2}}{2}=\frac{C_{a1}^{\left(\mathrm{H}\right)}+C_{a1}^{\left(\mathrm{L}\right)}+C_{a2}^{\left(\mathrm{H}\right)}+C_{a2}^{\left(\mathrm{L}\right)}}{4}\hfill \end{array}$$

(18a)

$$\begin{array}{cc}\hfill C_o& =\frac{\frac{C_{o1}^{\left(\mathrm{H}\right)}+C_{o2}^{\left(\mathrm{H}\right)}}{2}+\frac{C_{o1}^{\left(\mathrm{L}\right)}+C_{o2}^{\left(\mathrm{L}\right)}}{2}}{2}=\frac{C_{o1}^{\left(\mathrm{H}\right)}+C_{o1}^{\left(\mathrm{L}\right)}+C_{o2}^{\left(\mathrm{H}\right)}+C_{o2}^{\left(\mathrm{L}\right)}}{4}\hfill \end{array}$$

(18b)

Similarly to the MCML inverter, as we shall validate in the next section, these simplifications allow a nonlinear circuit to be treated as if it were linear, provided that its equivalent small-signal parameters are evaluated as described above.

4. Delay Model Validation and Comparison

To provide a validation of the proposed PD models, the MCML inverter gate reported in Figure 1 and the MCML universal gate shown in Figure 4 were designed using a 65-nm standard CMOS and a 28-nm FD-SOI process.

4.1. 65-nm Standard CMOS

Using the nominal supply voltage, $V_{DD}=1.2$ V, and following the design strategy in [14,32], we designed the MCML inverter and the universal gate with a nominal bias current, $I_o$, of about 20 $\mathsf{\mu }$A, a differential peak-to-peak voltage swing, $2\Delta V_o$, of 0.8 V and transistor dimensions, as in

Table 2. Transistors’ aspect ratios.

Transistor	65-nm CMOS $\mathit{W}/\mathit{L}$ [nm/nm]	28-nm FD-SOI $\mathit{W}/\mathit{L}$ [nm/nm]
M0	2000/240	1000/120
M1, M2, M3 *, M4 *, M5 *	300/60	320/30
MP1, MP2	135/205	80/94

* Only in the MCML universal gate.

.

For the evaluation of the PD, transistor level simulations were carried out in the Cadence Virtuoso environment referring to the test-benches reported in Figure 8a,b for the MCML inverter and the universal gate, respectively. The input terminals of the digital gate under the test are driven by the cascade of two MCML inverters which act as waveform shapers and provide realistic input waveforms. The output of the logic gate under the test is loaded by another MCML inverter which emulates a realistic load. The inverters of waveform shapers and digital load have the same aspect ratios reported in Table 2.

The PD of the MCML inverter is established in (3) and depends on the time constant associated to the output node, ${\tau }_o=C_o/g_{dp}$. Parameters $C_o$ and $g_{dp}$ are obtained from (4) using the values reported in

Table 3. Simulated parameters’ values of the MCML inverter. ‘H’ and ‘L’ denote the two logic states as defined in Section 2. The third column is the corresponding average value between these two logic states.

Parameter	65-nm CMOS			28-nm FD-SOI
	‘H’	‘L’	avg	‘H’	‘L’	avg
$C_{o1}$ [fF]	0.821	0.964	0.893	0.532	0.589	0.561
$C_{o2}$ [fF]	0.964	0.821	0.893	0.589	0.532	0.561
$g_{dp1}$ [$\mathsf{\mu }$S]	32.38	66.63	49.50	16.10	49.38	32.74
$g_{dp2}$ [$\mathsf{\mu }$S]	66.63	32.38	49.50	49.38	16.10	32.74

that were computed as detailed in Appendix B. The PD evaluated from (3) results in $t_{PD}=12.5$ ps. This theoretical value was compared to the PD computed in the transient simulations reported in Figure 9. The input signal is switched from high to low, as in Figure 9a, and back from low to high, as in Figure 9b. The inverted output signal, $v_o=v_{o1}-v_{o2}$, is plotted accordingly. The propagation delays result in $t_{PD}=13.61$ ps in both cases, with an error lower than 9%, thus confirming the good agreement of the proposed linearized model.

The PD of the MCML universal gate is established in (12) and depends on the time constant associated to the output node, ${\tau }_o=C_o/g_{dp}$, and on that associated to the internal node, ${\tau }_a=C_a/g_m$. Parameters $g_m$, $g_{dp}$, $C_a$, and $C_o$, are obtained from (17) and (18), using the values reported in

Table 4. Simulated parameters’ values of the MCML universal gate. ‘H’ and ‘L’ refer to input $v_X$ and denote the two logic states as defined in Section 3. The third column is the corresponding average value between these two logic states.

Parameter	65-nm CMOS			28-nm FD-SOI
	‘H’	‘L’	avg	‘H’	‘L’	avg
$C_{o1}$ [fF]	0.833	0.962	0.898	0.426	0.518	0.472
$C_{o2}$ [fF]	1.164	1.044	1.104	0.636	0.543	0.589
$C_{a1}$ [fF]	0.968	0.779	0.873	0.530	0.433	0.482
$C_{a2}$ [fF]	0.569	0.740	0.654	0.317	0.411	0.364
$g_{dp1}$ [$\mathsf{\mu }$S]	35.11	66.25	50.68	16.76	49.33	33.04
$g_{dp2}$ [$\mathsf{\mu }$S]	66.16	34.95	50.55	48.30	16.66	32.98
$g_{m3}$ [$\mathsf{\mu }$A/V]	149.2	8.900	79.05	141.0	1.440	71.22
$g_{m5}$ [$\mathsf{\mu }$A/V]	8.800	149.4	79.10	1.440	140.9	71.17

that were computed as detailed in Appendix B. For the two time constants, we obtained ${\tau }_a=9.66$ ps and ${\tau }_o=19.78$ ps so that, from (12), the PD results $t_{PD}=24.32$ ps. This theoretical value was compared to the PD computed in the transient simulations depicted in Figure 10. Specifically, Figure 10a reports the details of transition T9 while Figure 10b is focused on transition T10. In both cases, the input $v_Y$ is maintained in the ‘H’ state and is not shown. In transition T9, the simulated PD results in $23.72$ ps that becomes $25.30$ ps in transition T10. Considering both cases, the error is lower than $\pm 4\%$, once again confirming the good agreement of the proposed linearized model. As a final consideration, observe that the evaluation of the PD using a single-pole approximation would lead to $t_{PD}={\tau }_{0}ln\left(2\right)=13.71$ ps, with an error of $-42$% and $-46$% compared to the values simulated in transitions T9 and T10, respectively.

4.2. 28-nm FD-SOI

According to the strategy in [14,32], we designed the MCML inverter and the universal gate to operate at the nominal supply voltage of 1.0 V with a bias current, $I_o$, of 10 $\mathsf{\mu }$A. The differential peak-to-peak voltage swing, $2\Delta V_o$, was set to 0.6 V thus leading to the transistor sizes in Table 2.

The two MCML gates were simulated in the Cadence Virtuoso environment with the test-benches shown in Figure 8a,b. The inverters of waveform shapers and the digital load are designed with the aspect ratios reported in Table 2.

For the MCML inverter, parameters $C_o$ and $g_{dp}$ are obtained from (4) with the values in Table 3 that were computed as detailed in Appendix B without considering parasitic junction capacitors $C_{jd}$ and $C_{js}$, because of the SOI process. The expected PD evaluated from (3) is $t_{PD}=11.88$ ps. With a 11.1% error, it agrees very well with the simulated PD of $10.69$ ps evaluated in both the falling and the rising edges of the waveforms in Figure 11.

As far as the MCML universal gate is concerned, parameters $g_m$, $g_{dp}$, $C_a$, and $C_o$, are obtained from (17) and (18), using the values reported in Table 4 that were computed as detailed in Appendix B, without considering parasitic junction capacitors, $C_{jd}$ and $C_{js}$, because of the SOI process. The two time constants result in ${\tau }_a=5.94$ ps and ${\tau }_o=16.1$ ps so that, from (12), the PD results in $t_{PD}=17.7$ ps.

This value was compared to the PD carried out from the transient simulations shown in Figure 12a,b, for transitions T9 and T10, respectively. In transition T9, the simulated PD results in $18.5$ ps ($-4.3$%) that becomes $21.9$ ps ($-19.2$%) in transition T10. Considering both cases, the error is lower than $20\%$, thus reaffirming the good agreement of the proposed linearized model. Also in this case, the evaluation of the PD using a single-pole approximation would lead to $t_{PD}={\tau }_{0}ln\left(2\right)=11.2$ ps, with an error of $-39.5$% and $-49$% compared to the values simulated in transitions T9 and T10, respectively.

5. Conclusions

In this article, we have developed a simple and accurate model for evaluating the propagation delay in MCML gates. The model describes the behavior of MCML circuits in a linear fashion, despite the circuits themselves being non-linear. Indeed, we have demonstrated that a linear model can be used provided that, for each small-signal parameter, its average value calculated between the two different switching logic states is used. The proposed model was validated through simulations of MCML universal gates that were designed using modern nanometer processes. The theoretical values of the propagation delays were able to forecast the corresponding simulated values with an error lower than 4% and 20% in 65-nm standard CMOS and 28-nm FD-SOI, respectively.

As a final remark,

Table 5. Summary of different approaches for the estimation of the propagation delay in CML gates.

	[1,2,3,4]	[5,6]	[8,9]	[10,11,12]	[17,18,19,20]	This Work
Technology	Bipolar	Bipolar	Bipolar	Bipolar	MOS	MOS
Strategy	Sensitivity analysis	Average branch current	Linear device model	Small-signal model (1 pole)	Small-signal model (1 pole)	Small-signal model (2 poles)
Model complexity	Complex	Simple	Average	Simple	Simple	Simple
Number of parameters	High	Average	Average	Low	Low	Low
Model accuracy	Average	Low	Low	High	High	Higher

summarizes the properties of different approaches for estimating propagation delay in CML ports. Properties such as model complexity, number of parameters, and model accuracy are expressed qualitatively. The table shows that approaches based on small-signal models are the simplest with the fewest parameters. Among them, the proposed model is the most accurate.