# Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies

## Abstract

**:**

## 1. Introduction

## 2. Integrated Inductive Components: Loss Phenomena and Main Design Guidelines

_{IN}, the metal width, w, and the metal spacing, s. The process parameters, such as the metal BEOL, the thickness and permittivity of the insulation layers, and the substrate conductivity, cannot be modified. Generally, the design of inductive devices is aimed at minimizing energy loss. The main energy dissipation phenomena of silicon-integrated inductive components are shown in Figure 1b. They occur in the metal layers that form the coil (series losses), as well as in the conductive layers below (parallel losses). The former is mainly due to the current crowding on the internal sides of the coil, due to skin and proximity effects. Current crowding rises with an increase in the operating frequency, thus increasing the equivalent resistance of the inductor. Thick conductive metals and multi-layer structures are common arrangements to lower the series losses, but their effectiveness degrades at RF/mm-wave frequencies. According to Faraday’s law, current crowding is stronger in the inner turns. Therefore, the adoption of spirals with a low fill ratio, ρ, is a common rule [10].

_{DC}. The inductance maximum value reduces with an increase in the operating frequency, due to self-resonance. Actual inductors have a typical inductance range from a few hundred picohenrys to tens of picohenrys, moving from tens of gigahertz to 100 GHz and beyond. Since inductance is mainly dependent on n, the inner diameter, d

_{IN}, is adjusted to trade off the silicon area with current crowding phenomena, by using a low fill ratio, ρ, while the metal width, w, is typically tuned to set the peak quality factor, Q

_{MAX}, at the operating frequency. The metal spacing, s, must be set at the minimum value to maximize the coil auto-inductance. For the purpose of completeness, Table 1 summarizes the relationship between the electrical performance and the layout/process parameters of an integrated inductor.

## 3. The Body Biasing Technique

_{T}, according to the well-known expression reported below for an n-MOS device:

_{BS}is the voltage between the body and the source, V

_{T0}is the threshold voltage for zero V

_{BS}, $\varnothing $

_{F}is the bulk Fermi potential, and γ is the body effect coefficient. Changing V

_{BS}modifies V

_{T}, and, thus, the transistor can be operated at a reduced bias voltage, with almost equivalent characteristics in terms of gain, linearity, and noise. Forward (reverse) biasing of n-MOS (p-MOS) transistors has been largely used at low frequencies, but it has also been proven to be effective for RF/mm-wave operations [19,20,21,22,23,24]. It is worth mentioning that for n-MOS (p-MOS) transistors, a forward (reverse) body bias turns on the source-to-body diode, and, thus, an exponential DC current flows across the junction. This produces additional power consumption and can also cause latch-up failure. A simple, but effective, solution to limit the junction current is to add a resistor to the body terminal.

_{T}variation with respect to bulk technologies and the lack of leakage currents. Figure 4a shows the simplified cross-section of a commercial FD-SOI CMOS technology [19,20,21,22,23,24]. Transistors are fabricated in a 7-nm layer of silicon sitting over a 25-nm buried oxide (BOX). An ultra-thin body (UTB) guarantees an isolated electrical conduction channel between the source and drain, since the channel is fully depleted. Figure 4a shows flipped-well low-V

_{T}(LVT) transistors that use an n-well body and p-well body for n-MOS and p-MOS devices, respectively. In these transistors, the BOX layer works as a second gate oxide, and the body as a gate terminal (i.e., back gate terminal) that allows the tuning of V

_{T}by means of the body voltage. The body gain factor (i.e., the sensitivity of V

_{T}to the body voltage) is almost four times that of the traditional bulk technology (i.e., 90 mV/V). The lower V

_{T}characteristics of flipped-well devices are well exploited in low-voltage ICs.

## 4. Circuit Topologies for Low-Voltage Operation of RF/mm-Wave Blocks

_{T}, and maximum oscillation frequency, f

_{MAX}, values close to, or even higher than, 200 GHz. Such performance improvements have been obtained at the cost of a considerable reduction in the transistor breakdown voltage (BV), and, consequently, of the maximum supply voltage in comparison with equivalent HBT BiCMOS technologies. This poses new challenges for the design of RF/mm-wave CMOS front ends that are still the very bottleneck for several applications (e.g., 5G, automotive radar, and imaging). The turning point is to properly adjust the well-established RF/mm-wave topologies to mitigate low-voltage operation drawbacks. To this aim, the following simple guidelines can be applied to the main circuit blocks, such as LNA, mixers, and PAs:

- ▪
- Reduce the operative threshold voltage, V
_{T;} - ▪
- Increase the transconductance, g
_{m}, by means of positive feedback; - ▪
- Use only one transistor between the supply voltage, V
_{DD}, and ground; - ▪
- Adopt transformer-based power combining techniques.

_{T}is strongly suggested to operate the transistor with a lower gate–source voltage, V

_{GS}[26]. It can be achieved by exploiting the body biasing technique in standard CMOS, and more profitably in FD-SOI CMOS technologies, as discussed in Section 3. This approach is very effective, but often requires the implementation of additional circuitry, namely, body biasing generators [27,28]. Moreover, reducing V

_{T}by means of body biasing could be in contrast with the exploitation of such a technique to compensate for the process–voltage–temperature (PVT) variations, which are typically quite large in nanometer CMOS, especially for automotive applications [29,30].

_{DD}and the ground. In this perspective, the classical n-MOS cascode topology, largely adopted in high-frequency amplifiers (e.g., LNAs and PAs), thanks to its intrinsic advantages in terms of gain, stability and input–output isolation, cannot be used below a supply voltage of 1 V (i.e., V

_{DD}> 2V

_{DS_SAT}). Viable circuit alternatives could include the following:

- ▪
- Neutralized common source (CS) topology;
- ▪
- Folded cascode topology;
- ▪
- Reactive resonant coupling: capacitive coupling;
- ▪
- Reactive resonant coupling: transformer coupling.

_{G}, and source, L

_{S}, inductance. Moreover, they can also be used to implement a PA stage. The choice of the most suitable solution depends on both the application (e.g., frequency band and current consumption/silicon area specs) and the adopted CMOS technology node.

_{gd}, thus improving the input/output isolation and guarantying frequency stability. Neutralization can be implemented with simple integrated capacitors, C

_{N}, or by means of an additional pair of MOS transistors, to better track the process variation. Neutralized CS is a very effective solution for low-voltage operations (i.e., V

_{DD}> V

_{DS_SAT}), but it requires a very careful design to prevent oscillations in the amplifier.

_{d}, with consequent extra silicon area consumption [38]. It is also possible to save silicon area and, at the same time, increase the voltage gain by replacing the inductor with the primary winding of a transformer, whose secondary coil is exploited as a load inductor, L

_{D2}. In this way, positive feedback is easily implemented by means of transformer magnetic coupling [31].

_{F}, L

_{F}), properly sized to exhibit low impedance at the operating frequency, as shown in Figure 5d. Indeed, both inductors, L

_{D1}and L

_{S2}, resonate with the capacitances at nodes

**A**and

**B**, respectively. The performance of a capacitive-coupled (CC) cascode amplifier is affected by the Q-factor of the LC network and, especially, of the inductor. Therefore, it can also be used a pure capacitive coupling through by-pass capacitors if the area consumption is tolerable [39].

_{DS_MAX}). A common solution is to adopt a classical cascode topology made up of a thin-oxide CS transistor and a thick-oxide CG transistor to allow for a higher supply voltage. More complex solutions exploit multistacked devices [44,45]. However, both cascode and multistacked topologies are not viable when the PA is integrated within a transceiver operated at low voltage. In this case, only low-voltage circuit topologies (as shown in Figure 5) can be adopted. However, the achieved output power is not sufficient for the application. Integrated transformers can further increase the output power of an RF/mm-wave PA by exploiting the power-combining technique at the output stage [46,47,48,49,50,51,52,53,54,55,56].

- ▪
- Implement single-ended-to-differential and differential-to-single-ended conversions, providing inherent virtual ground for differential operations;
- ▪
- Transform impedance for impedance matching and output power matching;
- ▪
- Provide simple DC biasing of power devices via the center tap, avoiding the use of RF chokes and DC blocks.

_{OPT}, and is equal to the following:

_{LOAD,}M

_{S}, and N are the load resistance, the number of PA units and the transformer turn ratio, respectively. Indeed, according to Equation (2), when M

_{S}increases, R

_{OPT}reduces, thus requiring larger power transistors with lower maximum available gain, due to the RLC parasitics. Therefore, voltage combining is not used for an M

_{S}higher than four.

_{OPT}is equal to the following:

_{LOAD}, M

_{P}, and N are the load resistance, the number of PA units and the transformer turn ratio, respectively. From Equation (3), it is evident that the current-combining technique is more flexible in the selection of the optimum resistance, since the turn ratio, N, can be properly used to tune the optimum impedance, R

_{OPT}. In particular, a larger turn ratio is required to lower the R

_{OPT}when a higher M

_{P}is used. Unfortunately, increasing N often produces lossy and area-consuming integrated transformers. Moreover, only integer number turn ratios can be practically implemented.

_{S}= M

_{P}= 2. Generally, the output powers of M

_{S}× M

_{P}PA units can be increased up to M

_{S}× M

_{P}times. This hybrid approach gives more freedom to designers, with respect to pure voltage or current technique, since the optimum resistance is given by the following:

## 5. Conclusions

_{T}operations of nanometer CMOS transistors to reactive resonant coupling for sub 1-V circuits. A special insight was dedicated to transformer-based power-combining approaches to boost the PA output power, especially at mm-wave frequencies. Thanks to proper combinations of the described techniques, several high-frequency applications can be addressed by using sub 1-V CMOS ICs. This process started with RF wireless communications and now involves mm-wave applications, such as W-band automotive radar and beyond. Nanometer FD-SOI CMOS technologies are the natural candidates for future low-voltage RF/mm-wave ICs, especially with thick BEOL for better passive components.

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**(

**a**) SEM cross-section of a silicon-integrated spiral inductor; (

**b**) simplified representation of main loss phenomena in silicon-integrated inductive components. Reprinted with permission from Ref [9]. Copyright 2020, IEEE.

**Figure 2.**Integrated transformer configurations for RF/mm-wave operation. Reprinted with permission from Ref [9]. Copyright 2020, IEEE.

**Figure 4.**The 28-nm FD-SOI CMOS technology: (

**a**) simplified cross-section of LVT flipped-well transistors, (

**b**) V

_{T}variation with respect to the body voltage for the LVT flipped-well devices. Reprinted with permission from Ref [25]. Copyright 2019, IEEE.

**Figure 5.**(

**a**) Cascode; (

**b**) neutralized common source (CS); (

**c**) folded cascode; (

**d**) capacitive-coupled (CC) cascode; (

**e**) transformer-coupled (TC) cascode.

**Figure 6.**Double-balanced mixer topologies: (

**a**) traditional Gilbert cell mixer; (

**b**) TC Gilbert cell mixer; (

**c**) CC Gilbert cell mixer.

**Figure 9.**Power-combining techniques (

**a**): voltage–current combining (SPCT); (

**b**) current–voltage combining (PSCT).

**Figure 10.**Example of a series–parallel-combining transformer (SPCT) for 4 PA voltage–current combining.

Inductor Parameters | Peak Q-Factor (Q _{MAX}) | Low-Frequency Inductance (L _{DC}) | Self-Resonance Frequency (SRF) | |
---|---|---|---|---|

Number of turns, n | ▲ | ▼ | ▲ | ▼ |

Metal width, w | ▲ | ▲ | ▼ | ▼ |

Metal spacing, s | ▲ | ▼ | ▼ | ▼ |

Fill ratio, ρ | ▲ | ▲▼ | ▲▼ | ▼ |

Metal thickness, t | ▲ | ▲ | ▼ | ▲ |

Oxide thickness t_{ox} | ▲ | ▲ | — | ▲ |

Substrate resistivity, ρ_{SI} | ▲ | ▲ | ▲ | ▲ |

Performance Parameters | Transformer Structures | |||
---|---|---|---|---|

Interleaved | Stacked | Interstacked | Stacked Folded | |

Magnetic coupling factor, k | + | ++ | +++ | ++ |

Winding Q-factors | +++ | + | ++ | + |

Self-resonance frequency (SRF) | +++ | + | + | ++ |

Turn ratio, N | ++ | + | - | - |

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**MDPI and ACS Style**

Ragonese, E.
Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies. *Appl. Sci.* **2022**, *12*, 2103.
https://doi.org/10.3390/app12042103

**AMA Style**

Ragonese E.
Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies. *Applied Sciences*. 2022; 12(4):2103.
https://doi.org/10.3390/app12042103

**Chicago/Turabian Style**

Ragonese, Egidio.
2022. "Design Techniques for Low-Voltage RF/mm-Wave Circuits in Nanometer CMOS Technologies" *Applied Sciences* 12, no. 4: 2103.
https://doi.org/10.3390/app12042103