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Open AccessArticle

Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates

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Electroinformatics Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba 3058568, Japan
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Computer Science Course, Fundamental Science and Technology, Graduate School of Science and Technology, Meiji University, 1-1-1 Higashi-Mita Tama, Kawasaki 2148571, Japan
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Author to whom correspondence should be addressed.
This is an extended version of a paper that was presented at the IEEE S3S Conference 2014.
Academic Editors: David Bol and Steven A. Vitale
J. Low Power Electron. Appl. 2015, 5(2), 116-129; https://doi.org/10.3390/jlpea5020116
Received: 20 February 2015 / Accepted: 20 May 2015 / Published: 25 May 2015
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips. View Full-Text
Keywords: SOTB; FD-SOI; ultra-low voltage; measurement on silicon SOTB; FD-SOI; ultra-low voltage; measurement on silicon
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Ogasahara, Y.; Nakagawa, T.; Sekigawa, T.; Tsutsumi, T.; Koike, H. Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates. J. Low Power Electron. Appl. 2015, 5, 116-129.

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