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A Time-Domain z^{−1} Circuit with Digital Calibration

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## Abstract

**:**

^{−1}operation which is suitable, as a basic building block, for time-domain topologies and signal processing. The proposed circuit employs a time register circuit which is based on the capacitor discharging method. The large variation of the capacitor discharging slope over technology process and chip temperature variations which affect the z

^{−1}accuracy is improved using a novel digital calibration loop. The circuit is designed using a 28 nm Samsung FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate the theoretical analysis presenting a variation of capacitor voltage discharging slope less than 5% over worst-case process corners for temperature between 0 °C and 100 °C while consuming only 30 μA. Also, the worst-case accuracy of z

^{−1}operation is better than 33 ps for input pulse widths between 5 ns and 45 ns presenting huge improvement compared with the uncalibrated operator.

## 1. Introduction

^{−1}operation belongs among the basic signal processing procedures in the traditional discrete-time digital signal processing (DT-DSP). In recent years the z

^{−1}operation extended in the discrete-time continuous signal processing (DT-CSP) finding applications in time-domain circuits and systems [4]. DT-CSP needs a voltage-to-time (V/T) converter instead of an A/D converter which can be based on the well-known pulse-width modulation (PWM) or based on specific V/T converters [5,6].

^{−1}operation circuit can be based on circuits which are known as time register (TR) circuits. The main operation of the TR is to handle the time of the pulse width of the input pulses or time difference between the pulse edges, store this time and recover it when needed. It is assumed that the pulse-width is modulated by a voltage e.g., pulse-width is proportional to the input voltage. TR can be used in the construction of time-based arithmetic circuits such as time amplifiers [7,8,9], time adders/subtractors, time-integrators, time-to-digital converters [10,11,12] and time-domain processing blocks [13,14].

^{−1}circuit which is based on a novel time register [16]. The z

^{−1}circuit topology employs four TR in series achieving high accuracy in the time storage generating also synchronized output pulses with the reference sampling clock. The discharging slope of the TR register is calibrated over PT variation using a novel digital loop. The digital loop can be disabled after the end of calibration cycles minimizing the current consumption of the entire circuit.

^{−1}circuit is presented and analyzed while the associated digital calibration loop is analyzed in Section 5. The simulation results are reported in Section 6.

## 2. Pulse Width Modulation (PWM) and Time-Domain Approach

_{IN}. The main procedure to convert V

_{in}to a corresponding pulse width T

_{in}is achieved using the pulse width modulation (PWM) technique [17]. The input signal which is in the voltage domain is firstly sampled using a sample and hold circuit (S/H). As shown in Figure 1a, the input voltage is maintained for a time interval equal to the sampling period T

_{sampling}. The output of the PWM modulator is a pulse train with frequency equal to the sampling frequency with pulse width proportional to V

_{in}.

_{in}in our case, by one clock of the sampling period, in other words the z

^{−1}operation. Figure 1b presents a conceptual diagram of a z

^{−1}operator. As depicted in Figure 1c, S/H produces the samples of V

_{in}(n) and the PWM converts them into a pulse train with different pulse width T

_{in}(n) for each sampling period. T

_{in}(n) is fed to the z

^{−1}operator and then the signal is delayed by the foul clock cycle of the sampling frequency.

## 3. Operation of Novel Time Register

_{1}acts as a switch which when it is ON charges the capacitor to V

_{DD}, where V

_{DD}is the supply voltage. The OR gate sends a signal to the transistor M

_{2}which acts also as a switch but when it is ON the capacitor discharges. M

_{3}acts as a current source and controls the discharging slope through its gate voltage CTRL. As it will be explained in Section 5, the gate voltage CTRL of M

_{3}can be used to calibrate the variation of the discharging slope through a digital calibration loop. To be more precise, when voltage CTRL decreases/increases the drain current decreases/increases as well, and therefore, the discharging slope value decreases/increases. Lastly, the AND gate combined with the fast comparator [16] and a NOT gate in order to synchronize the output with CLK. The fast comparator which is presented in Figure 2c, is based on a current starving topology and is designed for fast transient response while its triple point voltage V

_{tp}is tuned to be equal to V

_{DD}/2 (0.5 V).

_{in}is related with the input pulse IN, and it is equal to its pulse width. Time interval T

_{CLK}is a pulse with constant pulse width with 25% duty cycle of the SET signal. When the SET voltage is zero, it pulls up the capacitor voltage V

_{cap}to the supply voltage V

_{DD}otherwise when SET is V

_{DD}the capacitor discharges due to OR gate when IN or CLK is V

_{DD}. When both IN and CLK are zero the capacitor voltage remains unchanged. Larger pulse width T

_{in}of the IN signal means more discharging time due to T

_{in}but on the other hand the discharging time due to CLK is always the same. T

_{CLK}is the time interval that the capacitor is permitted to discharge to V

_{DD}/2, assuming the discharging slope does not change while T

_{CLK}is constant. Therefore, when the capacitor is discharged by the IN signal then for larger T

_{in}, the capacitor voltage becomes V

_{DD}/2 sooner compared to the discharged due to CLK. Concluding, the output of the circuit is a pulse with a time interval value of T

_{CLK}-T

_{in}achieving in this manner the storing of the value of T

_{in}while the output pulse is synchronized with CLK signal.

_{tune}that modifies the current of the starved devices stabilizing in this manner the triple point voltage. Also, the device dimensions are chosen in order to increase the comparison speed minimizing the time delay of the output pulse.

## 4. Time-Domain z^{−1} Operator Circuit

^{−1}is to generate an output pulse with pulse width equal to T

_{in}which is synchronized with the sampling signal. As discussed in the previous section, unfortunately a TR circuit can store the pulse width T

_{in}of the IN signal in the form of an output pulse with pulse width equal to T

_{CLK}-T

_{in}which is synchronized with CLK signal and with the sampling reference clock.

^{−1}circuit, and Figure 3b depicts the basic waveforms that illustrate its operation. A combination of four TR circuits series realizes a z

^{−1}circuit. The SAMPLING signal is assumed to be the SET1 signal of the TR1 circuit, the input signal IN is equal to the input IN1 of TR1, while the final output signal OUT is the output of OUT4 of TR4.

_{OUT2}= T

_{CLK}-T

_{OUT1}= T

_{CLK}-(T

_{CLK}-T

_{in}) = T

_{in}and OUT2 is synchronized with CLK2. OUT2 is delayed by T

_{SAMPLING}/2 in relation to the sampling signal. Expanding the previous characteristic OUT4 pulse width is T

_{in}and is delayed by T

_{CLK}. Taking this into consideration, by using in cascade placement of four TR the z

^{−1}operator is created. Lastly, due to the subtraction that takes place after every TR constant error that can occur eliminate the others. Combining, z

^{−1}circuits in series can create time-domain z

^{−n}operation, where n is the number of used z

^{−1}operators. Also, other time-domain operations such as addition, subtraction and multiplication can be implemented with the proposed z

^{−1}circuit [10].

## 5. Digital Calibration

_{discharge}/C, where I

_{discharge}represents the discharging current (which is equal to the drain current M

_{2}) and C refers the capacitance. If the drain current of M

_{2}is not calibrated, it can vary a lot between process and temperature corners. A current variation of around 20% is very common in the integrated bias current generators. In our procedure, the variance of the used capacitor is roughly 15%. Therefore, the slope variation without calibration is expected to have a lot of spread over corners. As a result, the capacitor voltage may drop excessively slowly in some corners without crossing the comparator’s triple point (0.5 V) during the CLK time interval. Even for minor T

_{in}time interval, the capacitor voltage could cross the triple point in the event of a large discharge slope, reducing the dynamic range of TR. The calibration loop ensures the best operating condition, in which the capacitor crosses the triple point for a time interval equal to CLK. The digital loop ensures an almost dynamic range across process and temperature corners in this way.

_{2}as a result of the OR gate. The inverted CLK signal is also applied to the clock of D flip-flop.

_{LSB}defines the LSB current of the current mirror and is applied to the diode-connected transistor M

_{b}. The channel width of transistors M

_{0}to M

_{6}increases in binary fashion.

_{cap}.

_{leader}is set to V

_{DD}(b) b<6:0> = 0,000,000 and (c) the output current of current mirror is set equal to zero and, therefore, the output of the comparator will be V

_{comp}.

_{leader}= V

_{DD}because V

_{cap}.

_{leader}is larger than V

_{tp}. Therefore, CLK through the AND gate is applied to the counter as a result (a) the digital output of asynchronous counter increases by one (b) the output of current mirror increases by an I

_{LSB}and (c) the discharging slope increases at each calibration cycle.

_{cap}.

_{leader}will be lower than V

_{tp}the V

_{comp}.

_{leader}becomes zero. Therefore, when CLK = 0, at each calibration cycle, this will result in zero input of the AND gate, and the counter stops because CLK is not applied to the counter any more and stores the last digital word.

## 6. Results

#### 6.1. Digital Calibration over Technology Process and Chip Temperature (PT) Corners

_{cap}is towards V

_{DD}with small discharging slope. In each calibration cycle the discharging slope increases because the current applied by the binary-weighted current mirrors increases and, therefore, V

_{cap}moves towards V

_{tp}which is set to 0.5 V. The calibration cycles continue until the V

_{cap}crosses V

_{tp}. Then, the discharging slope takes the right value and the calibration process stops storing at the same time as the last values of calibration bits, b<6:0>. It should be noted that the calibration process, as presented, in Figure 7 is for the typical process conditions at 27 °C; the calibration process is valid for all the PT corners. Due to the quantization error of the current mirror, the discharge slope of the corners slightly differs. Table 1 shows the slope for the most significant corners in contrast with the slope of a non-calibrated time register. The calibrated discharging slopes present 5% spread over PT variations.

#### 6.2. z^{−}^{1} and z^{−}^{2} Operations

^{−1}operation. By using n number of z

^{−1}circuits in cascade fashion the z

^{−n}operation can be achieved. The Figure 8 displays the simulation results of two cascaded z

^{−1}operators. The input pulses IN with gradually decreased pulse widths pass through two cascaded z

^{−1}operators generating two output signals z

^{−1}and z

^{−2}. Comparing the outputs with SET signal it is obvious that the first operator delays the pulses for one cycle when the second does so for two cycles. Using this technique, the pulses of a signal can be delayed by n cycles by using n operators.

#### 6.3. z^{−1} Accuracy

^{−1}operation is the time error between the input and output pulse widths, time error = T

_{in}-T

_{out}. The time error should be as small as possible for every input pulse width and for every PT corners after the end of the calibration process. Figure 9 illustrates the time error over PT corners after calibration. The input pulse width T

_{in}ranges between 5 ns and 45 ns. It is obvious that the time error is at acceptable levels with worst-case error around ±33 ps. The time error is less than 0.9% for 40 ns full scale of T

_{in}.

_{in}can theoretically be anywhere between 0 and 50 ns. Using T

_{in}.

_{min}= 5 ns or T

_{in}.

_{max}= 45 ns, the shorter pulses emerge inside z

^{−1}circuit is 5 ns in both cases, based on the circuit topology. Our approach has a worst-case timing inaccuracy of roughly 33 ps over corners. The T

_{in}.

_{min}is around 43.6 dB higher than the worst case time error, according to our findings, which is quite good (20 log (T

_{in}.

_{min}/33 ps) = 43.6 dB). If the input pulse width becomes smaller than 5 ns (or larger than 45 ns) the time error increases but the architecture is still functional.

## 7. Discussion

^{−1}operator based on cascaded time-registers that uses the discharging slope technique. The discharging slope is calibrated over PT variations using a novel digital loop presenting around 5% spread while the time error of the z

^{−1}operation is less than 0.9% for 40 ns input range. Also, the digitally controlled calibration is disabled when the calibration completed cuts down the current consumption. The average current consumption is 30 μA for 5 MHz sampling frequency.

^{−1}operator, basic arithmetic functions such as adders, subtractors, time amplifiers and integrators can be also implemented. Also, by combining these functions more sophisticated systems can be built and explored, as time-based analog-to-digital converters, digital filters, discrete-time control systems. Also, a very beneficial aspect of this work is that all these types of time-based systems are composed mostly of CMOS digital building blocks and their performance is pretty stable against device size shrinking and low voltage supplies.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**(

**a**) Voltage-to-time conversion using a sample and hold circuit (S/H) and pulse width modulation (PWM), (

**b**) conceptual diagram of a z

^{−1}operator in time domain, (

**c**) basic waveforms of the voltage-to-time conversion and z

^{−1}operation.

**Figure 2.**(

**a**) Time register circuit, (

**b**) symbol, (

**c**) fast comparator topology [16] and (

**d**) main waveforms diagram.

**Figure 9.**Time error of a z

^{−1}over different technology process and chip temperature (PT) corners versus pulse width of T

_{in}.

PT Corner | Calibrated TR Slope (MV/s) | Digital Word (7 bit) | Uncalibrated TR Slope (MV/s) |
---|---|---|---|

Typical | 10.306 | 1000001 | 10.010 |

Cmin_ff_0° | 9.953 | 0110010 | 14.842 |

Cmin_ff_100° | 9.899 | 0110100 | 12.192 |

Cmin_ss_0° | 10.286 | 0110101 | 9.786 |

Cmin_ss_100° | 10.358 | 0111000 | 8.071 |

Cmax_ff_0° | 9.935 | 1001011 | 10.833 |

Cmax_ff_100° | 9.858 | 1001110 | 8.448 |

Cmax_ss_0° | 10.375 | 1010010 | 6.669 |

Cmax_ss_100° | 10.259 | 1011110 | 5.478 |

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**MDPI and ACS Style**

Panetas-Felouris, O.; Vlassis, S.
A Time-Domain *z*^{−1} Circuit with Digital Calibration. *J. Low Power Electron. Appl.* **2022**, *12*, 3.
https://doi.org/10.3390/jlpea12010003

**AMA Style**

Panetas-Felouris O, Vlassis S.
A Time-Domain *z*^{−1} Circuit with Digital Calibration. *Journal of Low Power Electronics and Applications*. 2022; 12(1):3.
https://doi.org/10.3390/jlpea12010003

**Chicago/Turabian Style**

Panetas-Felouris, Orfeas, and Spyridon Vlassis.
2022. "A Time-Domain *z*^{−1} Circuit with Digital Calibration" *Journal of Low Power Electronics and Applications* 12, no. 1: 3.
https://doi.org/10.3390/jlpea12010003